Abstract: There is provided a light-emitting element array having a plurality of light-emitting elements of different emission colors each comprising a light extraction electrode, a reflecting electrode, and an organic layer disposed between the electrodes, said organic layer comprising a light-emitting layer and a carrier-transporting layer disposed between the light-emitting layer and the reflecting electrode, wherein the geometrical distances between the reflecting electrode and light-emitting layer are the same irrespective of the emission color, and the specific relational equations (1), (2), and (3) are satisfied.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A highly efficient III-nitride/II-Oxide light emitting device that has a n++-tunneling layer, which comprises at least one material selected from a group consisting of n++-GaN, n++-InGaN, n++-AlGaN, n++-AlGaInN, n++-ZnO, n++-ZnCdO, n++-ZnMgO, n++-ZnMgCdO, that is deposited on top of the p-layer in a LED structure. After that, a top n-layer is deposited above that n++-tunneling layer that may be a n+-layer and comprises at least one material selected from a group consisting of n+-GaN, n+-InGaN, n+-AlGaN, n+-AlGaInN, n+-ZnO, n+-ZnCdO, n+-ZnMgO, n+-ZnMgCdO or a top n-layer may also be a n++-layer and comprises at least one material selected from a group consisting of n++-GaN, n++-InGaN, n++-AlGaN, n++-AlGaInN, n++-ZnO, n++-ZnCdO, n++-ZnMgO, n++-ZnMgCdO so that the top n-layer is made highly conductive and show very rough surface.

Abstract: A semiconductor optical device comprises a first conductive type III-V compound semiconductor layer, a second conductive type III-V compound semiconductor layer, and an active region. The first conductive type III-V compound semiconductor layer is provided on a substrate. The second conductive type III-V compound semiconductor layer is provided on the substrate. The active region is provided between the first conductive type III-V compound semiconductor layer and the second conductive type III-V compound semiconductor layer. The active region includes a III-V compound semiconductor layer. The III-V compound semiconductor layer contains nitrogen and arsenic as V-group element. The hydrogen concentration of the III-V compound semiconductor layer is greater than 6×1016 cm?3. The III-V compound semiconductor layer of the active region is doped with n-type dopant.

Abstract: To enhance the super-junction effect of a semiconductor device having the super-junction structure and prevent lowering in the breakdown voltage, a semiconductor device described herein has a first-conductivity-type substrate having an element forming region having a gate electrode and a source electrode formed therein, and a periphery region formed around the element forming region and having an element isolating region formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the substrate, as extending from the element forming region to the periphery region, wherein, in the periphery region, a plurality of p-type column regions are provided outwardly from the element-forming region; and the gate electrode is a trench gate buried in the substrate, being formed so as to surround the p-type column regions also in the periphery region similarly to as in the element forming region.

Abstract: An integrated circuit chip includes a formation of integrated layers configured to define at least one integrated electronic component. The integrated layers further define an integrated electron tunneling device, which includes first and second non-insulating layers spaced apart from one another such that a given voltage can be provided thereacross. The integrated electron tunneling device further includes an arrangement disposed between the first and second non-insulating layers and serving as a transport of electrons between and to the first and second non-insulating layers. The arrangement includes at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling. The integrated electron tunneling device further includes an antenna structure connected with the first and second non-insulating layers, and the integrated electron tunneling device is electrically connected with the integrated electronic component.

Abstract: A pixel having an organic light emitting diode (OLED) and method for fabricating the pixel is provided. A planariza-tion dielectric layer is provided between a thin-film transistor (TFT) based backplane and OLED layers. A through via between the TFT backplane and the OLED layers forms a sidewall angle of less than 90 degrees to the TFT backplane. The via area and edges of an OLED bottom electrode pattern may be covered with a dielectric cap.

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: Organic electronic devices are fabricated by a process includes forming an organic layer including: placing a first liquid composition over a first portion of a surface of a substrate without a well structure connected to or adjacent the first portion of the surface of the substrate, i) the first portion of the surface of the substrate has a first surface energy, ii) the first liquid composition includes a first liquid medium and iii) the first liquid composition has a second surface energy that is higher than the first surface energy; and evaporating the first liquid medium while the first liquid composition overlies the first portion of the surface of the substrate.

Abstract: To provide a high throughput film deposition means for film depositing an organic EL material made of polymer accurately and without any positional shift. A pixel portion is divided into a plurality of pixel rows by a bank, and a head portion of a thin film deposition apparatus is scanned along a pixel row to thereby simultaneously apply a red light emitting layer application liquid, a green light emitting layer application liquid, and a blue light emitting layer application liquid in stripe shapes. Heat treatment is then performed to thereby form light emitting layers luminescing each of the colors red, green, and blue.

Abstract: Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1240) having a substrate (1240), at least one active layer (1240) and at least one surface layer (1240), Current control can be achieved through the formation of patterns (1240) surrounding contacts (1215), said patterns (1240) including insulating implants and/or sacrificial layers formed between active devices represented by said contacts (1215). Current flows through active regions (1260) associated with said contacts (1215) and active devices. Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.

Abstract: A liquid crystal display apparatus comprises a liquid crystal display panel including a first substrate containing a color filter including a plurality of coloring layers, a second substrate arranged opposite to the first substrate and including a display surface on an opposite side to the first substrate and a liquid crystal layer held between the first substrate and the second substrate, and a circular polarization element arranged opposite to the display surface of the second substrate.

Abstract: A thin film transistor substrate structure for using a horizontal electric field includes a substrate; a gate line and a first common line formed on the substrate parallel to each other from a first conductive layer; a gate insulating film formed on the substrate, the gate line, and the first common line; a data line formed from a second conductive layer on the gate insulating film crossing the gate line and the common line with the gate insulating film therebetween to define a pixel area; a thin film transistor connected to the gate line and the data line; a protective film covering the data line and the thin film transistor; a common electrode formed from a third conductive layer connected to the common line through a hole passing through the protective film and the gate insulating film; and a pixel electrode formed from the second conductive layer connected to the thin film transistor to define a horizontal electric field between the pixel electrode and the common electrode.

Abstract: A liquid crystal display panel and a fabricating method thereof for reducing the number of data lines and the capacitance of a parasitic capacitor between pixel electrodes are disclosed. A first switching part has at least two thin film transistors for applying a first pixel signal that is supplied to a first data line to a first pixel electrode under control of the second control line and the gate line. A second switching part has at least two thin film transistors for applying a second pixel signal supplied to the second data line to the second pixel electrode under control of the first control line and the gate line. A turn-on current value of wither of the two thin film transistors, in each of the first and second switching parts, is more than that of the other thin film transistor.

Abstract: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.

Abstract: To prevent a point defect and a line defect in forming a light-emitting device, thereby improving the yield. A light-emitting element and a driver circuit of the light-emitting element, which are provided over different substrates, are electrically connected. That is, a light-emitting element and a driver circuit of the light-emitting element are formed over different substrates first, and then electrically connected. By providing a light-emitting element and a driver circuit of the light-emitting element over different substrates, the step of forming the light-emitting element and the step of forming the driver circuit of the light-emitting element can be performed separately. Therefore, degrees of freedom of each step can be increased, and the process can be flexibly changed. Further, steps (irregularities) on the surface for forming the light-emitting element can be reduced than in the conventional technique.

Abstract: Edge-emitting LED light source, and method for fabricating an edge-emitting LED light source. The edge-emitting LED light source has a plurality of edge-emitting LEDs arranged in close proximity to one another to define an array of edge-emitting LEDs. Light beams separately emitted by each of the plurality of edge-emitting LEDs in the array together form a single light beam that has a generally two-dimensional cross-sectional shape, for example, a square or other rectangular shape, and an increased overall light flux.

Abstract: A fully solution-processed polymer electroluminescent device has a hole injection layer fabricated using a crosslinkable hole injection/transport material doped with conductivity dopants.

Abstract: Diode comprising a substrate and an organic electroluminescent layer interposed between a lower electrode and an upper electrode, at least one of which electrodes is formed from a multilayer which is itself formed by the stack of adjacent sublayers made of amorphous carbon, having different refractive indices n1, n2. The amorphous carbon contains no added silicon, thereby making it possible to avoid using silane for the manufacture. The multilayer provides an electrode function, a multimirror function and an encapsulation function.

Abstract: A method for manufacturing a p-type gallium nitride compound semiconductor includes providing a gallium nitride compound semiconductor containing a p-type impurity on a surface of a conductive substrate, immersing in an electrolytic solution the conductive substrate on which the gallium nitride compound semiconductor is provided, providing a cathode to be in contact with the electrolytic solution, and applying a current between the cathode and the conductive substrate serving as an anode to activate the p-type impurity.

Abstract: A light emitting chip carrier structure includes a basin with a predetermined height protruded from the surface of a substrate for containing a carrier of a light emitting chip, and a package material for packaging the light emitting chip and the basin, so as to greatly increase the light emitting angle of the light emitting chip, while increasing the contact area of the package material, enhancing the adhesion between the package material and the substrate, and improving the overall brightness performance and reliability of the light emitting diode.

Abstract: The present invention relates to a light-emitting device having a substrate and a light-emitting layer comprising an electroluminescent material, wherein the light-emitting layer (p-n junction) is sandwiched between a p-type cladding layer with a p-electrode layer and an n-type cladding layer with an n-electrode layer. The light-emitting device is characterized in that a light control portion is deposited on a light-exiting surface of the light-emitting device. Said light control portion comprises at least one light-tunneling layer. Said light-tunneling layer has a refractive index with respect to the wavelength of the main emitting-light from the light-emitting layer lower than the refractive indices of the substrate, the cladding layers and the electrode layers.

Abstract: An omni-directional reflector having a transparent conductive low-index layer formed of conductive nanorods and a light emitting diode utilizing the omni-directional reflector are provided. The omni-directional reflector includes: a transparent conductive low-index layer formed of conductive nanorods; and a reflective layer formed of a metal.

Abstract: A disclosed semiconductor device includes a substrate, an element provided on the substrate, an encasing structure encasing the element and including an organic material part formed of an organic material, and a protective film covering the organic material part. The protective film is formed of an inorganic material.

Abstract: A light-emitting diode including a curved surface portion 14aA formed in the front face of a sealing member 14 with the cross-sectional shape of the curved surface portion being in the shape of an undulating curve that has a concave curve C1 near the optical axis and convex curves C2 on both sides of concave curve C1, thus allowing the light emitted from a light-emitting chip 12 at a small divergence angle centered on the optical axis Ax to reach the concave curve C1 and to be directed forward as diffused light deflected from the optical axis and further allowing the light emitted at a large divergence angle centered on the optical axis Ax to reach the convex curves C2 and to be directed forward as light deflected toward line L positioned at the divergence angle ?.

Abstract: In a side view LED, elongated first and second lead frames each have a finger extending therefrom. The finger of the first lead frame is disposed in parallel with that of the second lead frame. An LED chip and a protective device are mounted on mounting areas of the first and second lead frames, respectively and electrically connected to the first and second lead frames. A package body houses the first and second lead frames to form first and second opened areas. The first opened area is externally opened around the LED chip, the second opened area is externally opened around the protective device, and the partition wall is formed therebetween. First and second encapsulants are provided to the first and second opened areas, respectively to encapsulate the LED chip and protective device, respectively. At least the first encapsulant is transparent.

Abstract: A blue light-emitting phosphor emitting light with high efficiency by ultraviolet light of long wavelength as well as blue (to violet) light of short wavelength emitted from a semiconductor light-emitting element, particularly by the light having the wavelength in the range from 380 nm to 430 nm, is provided. A light-emitting device exhibiting high luminance and stable chromaticity is also provided by using the blue light-emitting phosphor. The blue light-emitting phosphor includes a divalent europium-activated or divalent europium- and manganese-activated aluminate phosphor, substantially represented by the general formula: a[(MI1-c-dSrcEud)(Mg1-eMe)]O.bAl2O3, where MI represents at least one kind of element selected from Ca and Ba, and a, b, c, d and e are numbers satisfying 0.1?a/b?1.0, 0.2?c?0.8, 0.01?d?0.5, and 0?e?0.05.

Abstract: A color filter substrate has a transmissive portion through which light rays are transmitted and a reflective portion on which light rays are reflected. A color filter substrate manufacturing method includes providing a transmissive base, forming a foundation layer over the transmissive base such that a depressed portion is formed at the transmissive portion, forming a reflective film over the foundation layer so as to have an opening at the transmissive portion, forming banks over the reflective film so as to define a deposit region, and forming a coloring element over the reflective film with droplet discharge onto the deposit region defined by the bank.

Abstract: A method of manufacturing an element having a microstructure of an excellent grating groove pattern or the like is obtained. This method of manufacturing an element having a microstructure comprises steps of forming a metal layer on a substrate, forming a dot column of concave portions on the surface of the metal layer and anodically oxidizing the surface of the metal layer formed with the dot column of concave portions while opposing this surface to a cathode surface thereby forming a metal oxide film having a grating groove pattern. When the interval between the concave portions of the dot column is reduced, therefore, a linear grating groove pattern having a large depth with a uniform groove width along the depth direction is easily formed in a self-organized manner.

Abstract: The present invention discloses a light device and the fabrication method thereof. An object of the present invention is to provide the light device and the fabrication method thereof an electric/thermal/structural stability is obtained, and a P-type electrode and an N-type electrode can be simultaneously formed. In order to achieve the above object, the inventive light device includes: a GaN-based layer; a high concentration GaN-based layer formed on the GaN-based layer; a first metal-Ga compound layer formed on the high concentration GaN-based layer; a first metal layer formed on the first metal-Ga compound layer; a third metal-Al compound layer formed on the first metal layer; and a conductive oxidation preventive layer formed on the third metal-Al compound layer.

Abstract: A submount for mounting an LED chip includes a substrate, a die attach pad configured to receive an LED chip on an upper surface of the substrate, a first meniscus control feature on the substrate surrounding the die attach pad and defining a first encapsulant region of the upper surface of the substrate, and a second meniscus control feature on the substrate surrounding the first encapsulant region and defining a second encapsulant region of the upper surface of the substrate. The first and second meniscus control features may be substantially coplanar with the die attach pad. A packaged LED includes a submount as described above and further includes an LED chip on the die attach pad, a first encapsulant on the substrate within the first encapsulant region, and a second encapsulant on the substrate within the second encapsulant region and covering the first encapsulant. Method embodiments are also disclosed.

Abstract: An LED package comprises: a package body having therein a LED receiving part including a reflecting surface; an LED mounted within the LED receiving part; a lead mounted within the package body such that first and second ends of the lead are exposed to the outside of the package body. The lead includes first and second conductive parts which are electrically connected to the LED and a non-conductive part which insulates the first and second conductive parts from each other.

Abstract: In a nitride semiconductor light-emitting device, a cap is pressure-bonded on the top surface of a stem under electric discharge to form a package. The package encloses a heatsink, a nitride semiconductor laser element, electrode pins, and wires, and has sealed inside it a gas containing oxygen as a sealed atmosphere. At least the inner surface of the cap is plated with Ni and Pd, which are metals that can occlude hydrogen.

Abstract: The invention relates to an LED with an improved soldering structure, a method of assembling the LED to a PCB, and an LED assembly manufactured by the method. The LED includes an LED chip and a pair of leads with an end electrically connected the LED chip and the other end to be connected to an external power source, having a hole or a cutout part formed therein. The LED also includes a package body housing a part of the lead in the side of the LED chip, and a transparent lens placed on a surface of the package body in the side of the LED chip, for emitting light laterally. This improves soldering conditions for soldering with the other end of the lead placed on the solder, saving the amount of a solder paste while enhancing bonding strength after soldering.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.

Abstract: In a transistor in which the majority carriers are holes, at least one narrow bandgap region or layer is doped p-type or contains an excess of holes and is subject to compressive mechanical strain, whereby hole mobility may be significantly increased. In a p-channel quantum well FET, the quantum well InSb well p-type layer 5 (modulation or directly doped) lies between In1-xAlxSb layers 4, 6 where x is of a value sufficient to induce strain in layer 5 to an extent that light and heavy holes are separated by much more than kT. Transistors falling within the invention, including bipolar pnp devices, may be used with their more conventional electron majority carriers counterparts in complementary logic circuitry.

Abstract: The structure and method of measuring the capacitance comprising a first buried doped area and a heavily doped area in a semiconductor substrate. The heavily doped area is parallel to the buried doped area. Several second buried doped areas, the first oxide layers and the second oxide layers are formed in the semiconductor substrate. Any of the second buried doped areas is perpendicular to the first buried doped area. One end of the second buried doped area is connected to the first buried doped area, and another end is connected to the heavily doped area. Any of the first oxide layers is overlaid on the second buried doped area. Any of the second oxide layers is placed between any two first oxide layers, and the thickness of the second oxide layer is thinner than the thickness of the first oxide layer. At least two first and several second polysilicon rows are formed on the semiconductor substrate, and wherein two first polysilicon rows are respectively placed on two sides of the second buried doped areas.

Abstract: The present invention relates to a programmable semiconductor device, preferably a FinFET or tri-gate structure, that contains a first contact element, a second contact element, and at least one fin-shaped fusible link region coupled between the first and second contact elements. The second contact element is laterally spaced apart from the first contact element, and the fin-shaped fusible link region has a vertically notched section. A programming current flowing through the fin-shaped fusible link region causes either significant resistance increase or formation of an electric discontinuity in the vertically notched section. Alternatively, the vertically notched section may contain a dielectric material, and application of a programming voltage between a gate electrode overlaying the vertically notched section and one of the contact elements breaks down the dielectric material and allows current flow between the gate electrode and the fin-shaped fusible link region.

Abstract: A field effect transistor includes a first semiconductor region of a first conduction type, a gate electrode formed on the channel region of the first semiconductor region via a gate insulating film, source and drain electrodes formed to interpose the channel region, second semiconductor regions of a second conduction type formed between the source and drain electrodes and the channel region, the second semiconductor regions giving rise to an extension region of the source and drain electrodes, and third semiconductor regions of the second conduction type formed between the source and drain electrodes and each of the first and second semiconductor regions, the third semiconductor regions formed by segregation from the source and drain electrodes and having an impurity concentration higher than that of the second semiconductor regions.

Abstract: In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.

Abstract: A CMOS image sensor includes a substrate including a sensing part and a peripheral driving part; a first insulating interlayer formed over an entire surface of the substrate; a first metal line formed on the first insulating interlayer in each of the sensing and peripheral driving parts; a second insulating interlayer formed over the entire surface of the substrate including the first metal line; a second metal line formed on the second insulating interlayer in each of the sensor and peripheral drive parts; an etch-stop layer formed over the entire surface of the substrate including the second metal line; a third insulating interlayer formed on the peripheral driving part of the etch-stop layer; a third metal line formed on the third insulating interlayer; a fourth insulating interlayer formed on the third insulating interlayer including the third metal line, to be disposed in the peripheral driving part; and a fourth metal line formed on the fourth insulating interlayer.

Abstract: An image-processing unit for an image sensor is provided. The image-processing unit comprises a plurality of photodiodes arranged inside the image sensor. The photodiodes have different sensing area according to its location. Typically, the sensing area of the photodiodes increases from the center toward the periphery. Therefore, the attenuation of sensitivity caused by a larger incident angle away from the central region can be compensated to enhance image quality.

Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

Abstract: A semiconductor image sensor includes: a semiconductor imaging element including an imaging area, a peripheral circuit area, and an electrode area; cylindrical electrodes provided on electrode terminals so as to be electrically connected with an external device; and a transparent resin layer provided on the upper surface of the semiconductor imaging element. The upper surface of each cylindrical electrode and the upper surface of the transparent resin layer are substantially of the same height.

Abstract: Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.

Abstract: An electronic circuit is formed by closely spacing metallic gate and drain interconnects to a flexible portion of a source interconnect. A gate voltage results in electrostatic attraction and lateral mechanical movement of the flexible source interconnect portion and causes an electrical short between source and drain. VanderWaals attraction between contacting source and drain can be used to provide volatile switching (springy thicker source portion) and non-volatile switching (limp thinner source portion). In accordance with the invention, an easily fabricated, high speed, low power, radiation hard, temperature independent, integrated reconfigurable electronic circuit with embedded logic and non-volatile memory can be realized. The switch uses patterned interconnect material for its structure and can be incorporated to a 3D layered structure consisting of three dimensional interconnect in which different layers and portions of the circuits are linked through volatile and non-volatile switches.

Abstract: A liquid crystal display (LCD) and a method for driving the same include a timing control unit that outputs a first timing signal including a data signal and a load signal and a second timing signal including a gate selection signal and an output enable signal, a delay unit that delays the output gate selection signal by a predetermined period of time, a data driver that converts the data signal into predetermined data voltages according to the load signal and outputs the data voltage, a gate driver that outputs gate-on/off signals according to the delayed gate selection signal, and a liquid crystal panel that displays an image by driving pixel electrodes according to the data voltages and the gate-on/off signals.

Abstract: A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.

Abstract: A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with the source/drain implants for the first type of transistor; the varactor insulator is formed simultaneously with the gate insulator for one type of transistor; and the lower electrode is formed simultaneously with a well for the first type of transistor, so that no additional mask is required.

Abstract: One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed by a nitridation process that adds nitrogen to a semiconductor substrate.