Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

Abstract: A field effect transistor (FET) with high withstand voltage and high performance is realized by designing a buffer layer structure appropriately to reduce a leakage current to 1×10?9 A or less when a low voltage is applied. An epitaxial wafer for a field effect transistor comprising a buffer layer 2, an active layer, and a contact layer on a semi-insulating substrate 1 from the bottom, and the buffer layer 2 includes a plurality of layers, and a p-type buffer layer composed of p-type AlxGa1?xAs (0.3?x ?1) is provided as a bottom layer (undermost layer) 2a. A Nd product of a film thickness of the p-type buffer layer and a p-type carrier concentration of the p-type buffer layer is within a range from 1×1010 to 1×1012/cm2.

Abstract: A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.

Abstract: A substrate support assembly and method for controlling the temperature of a substrate within a process chamber are provided. A substrate support assembly includes an thermally conductive body comprising a stainless steel material, a substrate support surface on the surface of the thermally conductive body and adapted to support a large area substrate thereon, one or more heating elements embedded within the thermally conductive body, a cooling plate positioned below the thermally conductive body, a base support structure comprising a stainless steel material, positioned below the cooling plate and adapted to structurally support the thermally conductive body, and one or more cooling channels adapted to be supported by the base support structure and positioned between the cooling plate and the base support structure. A process chamber comprising the substrate support assembly of the invention is also provided.

Abstract: Methods, and structures formed thereby, are disclosed for forming laterally grown structures with nanoscale dimensions from nanoscale arrays which can be patterned from nanoscale lithography. The structures and methods disclosed herein have applications with electronic, photonic, molecular electronic, spintronic, microfluidic or nano-mechanical (NEMS) technologies. The spacing between laterally grown structures can be a nanoscale measurement, for example with a spacing distance which can be approximately 1-50 nm, and more particularly can be from approximately 3-5 nm. This spacing is appropriate for integration of molecular electronic devices. The pitch between posts can be less than the average distance characteristic between dislocation defects for example in GaN (?=1010/cm2?d=0.1 ?m) resulting an overall reduction in defect density.

Abstract: An electro-optical device includes first switching elements which are correspondingly provided at intersections of a plurality of scanning lines and a plurality of data lines in a display region, at least three metal layers which are provided in the display region, a wiring line portion which is provided in an adjacent region of the display region and supplies signals to second switching elements through signal lines formed of at least two metal layers of the three metal layers, and an electromagnetic shield which is provided in the adjacent region of the display region. The electromagnetic shield has a first shield portion which covers the wiring line portion using metal layers other than the metal layers forming the signal lines, and a second shield portion which is electrically connected to the first shield portion and is disposed between the signal lines.

Abstract: An electronic system includes apparatus having a transmission line circuit with an associated high permeability material. The high permeability material may include a layered structure of a nickel iron compound.

Abstract: The present invention relates to inter-chip electrostatic discharge (ESD) protection structures for high speed, and high frequency devices that contain one or more direct, inter-chip signal transmission paths. Specifically, the present invention relates to a structure that contains: (1) a first chip including a first circuit, (2) a second chip including a second circuit, (3) an intermediate insulator layer located between the first and second chips, wherein the first and second circuits form a signal transmission path for transmitting signals through the intermediate insulator layer. An electrostatic discharge (ESD) protection path is provided in the structure between the first and the second chip through the intermediate insulator layer, to protect the signal transmission path from ESD damages.

Abstract: An over-molded leadframe (e.g., a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the QFN package are disclosed. The QFN package includes a capacitance lead configured to substantially reduce and/or offset the inductance created by one or more wirebonds used to connect an integrated circuit (IC) chip on the package to an input/output (I/O) lead. The IC chip is connected to the capacitance lead via one or more wirebonds, and the capacitance lead is then connected to the I/O lead via at least a second wirebond. Thus, inductance created by the one or more wirebonds on the package is substantially reduced and/or offset by the capacitance lead prior to a signal being output by the package and/or received by the IC chip.

Abstract: System and method for a thermal and space efficient integrated circuit package. A preferred embodiment comprises a first lead frame with a first surface to which a first die is attached and a second surface external to a multi-die package, a second lead frame with a first surface to which a second die is attached, wherein the first die and the second die are arranged so that they face each other. The present invention further comprises a first plurality of pins arranged around the first lead frame and a second plurality of pins arranged around the second lead frame. Finally, a package body encapsulates the first lead frame and the second lead frame with a portion of each pin in the first plurality of pins and the second plurality of pins extending outside the package body.

Abstract: A plastic lead frame with snap-together electrical connectors, electrical component system, and method using plastic-injection, plating, and known photolithography techniques is disclosed. The plastic lead frame and electrical component system operates with an integrated circuit, which functions as a sensor, such as a Hall-Effect sensor. The snap-together connectors allow interference joints to become electrical connections. Using a plastic lead frame, simple sensors may be electrically connected to the integrated circuit without a metal lead frame.

Abstract: A semiconductor package presents Z-shaped outer leads. The outer leads have a first portion located near an upper surface of a package body, a second portion, and a third portion located near a lower surface of a package body. A second similar semiconductor package may be stacked on the first semiconductor package with the third portion of the second semiconductor package located on and electrically connected to the first portion of the first semiconductor package. In each of the first and second semiconductor packages, a distance between the bottom surface of the third portion of the outer lead and the lower surface of a package body may be greater than a distance between the top surface of the first portion of the outer lead and the upper surface of the package body.

Abstract: A rectify element as a semiconductor device has a disk section, a first solder part, a buffer plate, a second solder part, a semiconductor chip, and a lead, and a sealing member with which the semiconductor chip is sealed. A cylindrical concave part is formed at one end surface of the disk section. A side wall of the cylindrical concave part faced to an inner peripheral wall at the upper surface of the disk section has a sloped shape of an angle of more than 90° to a contact surface of the upper surface of the disk section on which the semiconductor chip is placed.

Abstract: A semiconductor device including: a semiconductor substrate having an electrode; a resin protrusion formed on a surface of the semiconductor substrate on which the electrode is formed, the resin protrusion extending along a straight line and having a sloping region of which a height decreases along the straight line as a distance from a center of the resin protrusion increases; and an interconnect electrically connected to the electrode and extending over the sloping region of the resin protrusion.

Abstract: A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.

Abstract: In an electronic parts packaging structure of the present invention, an electronic parts is mounted or formed on a silicon circuit substrate having a structure in which wiring layers on both sides thereof are connected to each other through a through electrode, and a protruded bonding portion which is ring-shaped and is made of glass, of a seal cap having a structure in which a cavity is constituted by the protruded bonding portion, is anodically bonded to a bonding portion of the silicon circuit substrate, thus, the electronic parts is hermetically sealed in the cavity of the sealing cap.

Abstract: A jig structure for manufacturing a stacked memory card, wherein the stacked memory card has a substrate forming with a package area and at least a electrical element, the jig structure is formed with a penetrated slot corresponding to the mounted area of the substrate and at least a protection cover corresponding to the electrical element.

Abstract: Electronic parts 12, 13 and a terminal 14 are provided on a substrate 11, an upper surface 18A of a terminal main body portion 18 is set higher than surfaces 12A, 13A of the electronic parts 12, 13, a sealing resin is provided to expose the upper surface 18A of the terminal main body portion 18, and the terminal 14 and the wiring pattern 16 are connected directly to each other.

Abstract: A semiconductor pressure sensor can reduce the damage of bonding wires to increase their life time even under an environment in which the temperature and pressure change rapidly and radically. The semiconductor pressure sensor includes a package (1) made of a resin and having a concave portion (1a), a lead (2) formed integral with the package (1) by insert molding, with its one end exposed into the concave portion (1a) and its other end extended from the package (1) to the outside, a sensor chip (3) arranged in the concave portion (1a) for detecting pressure, and a bonding wire (4) electrically connecting the sensor chip (3) and the lead (2) with each other. An interface between the lead (2) and the package (1) on the side of the concave portion (1a) is covered with a first protective resin portion (6) of electrically insulating property, and the bonding wire (4) is covered with a second protective resin portion (7) that is softer than the first protective resin portion (6).

Abstract: A connector layout for arranging a plurality of parallel electrical connectors between two electronic devices. In one device, each connector has a strip connected to a bump pad. The bump pad is superimposed on and electrically connected to a bump pad on the other device. Each strip has a certain required strip width and each bump pad has a certain required pad width. The connectors are grouped into a group of three or more. Within each group, a strip is connected to a bump pad along one side edge thereof, and the bump pads are offset in two directions such that after the bump pads are superimposed, the pattern of the connected connectors in each group of connectors resembles a plurality of zigzag paths offset to maintain a constant gap between two strips. As such, the gap between two connectors can be minimized.

Abstract: An apparatus and method to provide a micro-electromechanical systems (MEMS) radio frequency (RF) switch module with a vertical via. The MEMS RF switch module includes a MEMS die coupled to a cap section. The vertical via passes through the cap section to electrically couple an RF switch array of the MEMS die to a printed circuit board (PCB). In one embodiment, the MEMS die includes a trace ring surrounding at least a portion of the RF switch array so that a signal may enter or exit the MEMS RF switch module using the vertical via without crossing the trace ring.

Abstract: A stack package may have a plurality of unit packages. Each unit package may include a first substrate, a semiconductor chip, and a second substrate. Conductive supports may stack the second substrate on the first substrate. Conductive bumps may be provided on the bottom surface of the first substrate. An encapsulant may seal the semiconductor chip exposing the top surface of the second substrate. The conductive bumps of an upper unit package may be connected to the second substrate of the lower unit package.

Abstract: According to one embodiment of the invention, a power system for a die comprises a plurality of supply voltage lines, a plurality of ground lines, a plurality of metallized rails, and a via. Each of the plurality of supply voltage lines are in communication with at least one supply voltage pad. Each of the plurality of ground lines are in communication with at least one ground pad. The plurality of ground lines are interlaced with the plurality of supply voltage lines. The plurality of metallized rails are disposed across the plurality of supply voltage lines and the plurality of ground lines. The via communicatively couples at least one of the plurality of metallized rails to at least one of the supply voltage lines or at least one of the ground lines.

Abstract: A semiconductor device may have a plurality of dielectric layers and at least one termination circuit line between the dielectric layers. The termination circuit lines may be formed over the active surface of a semiconductor substrate.

Abstract: A multilayered circuit substrate and a semiconductor package using the multilayered circuit substrate are provided to increase the number of bonding pads arranged on the circuit substrate without reducing the pitch of the bonding pads, and to further increase the routing feasibility of high speed signals by the use of signal wirings instead of vias. An embodiment may include bonding pads provided on different layers, in which the bonding pads arranged on one layer are staggered with the bonding pad arranged on another layer. Ball lands may be connected to the bonding pads using wirings wherein the bonding pads connected to the signal wirings may be provided on the same layer as the corresponding ball lands.

Abstract: Flexible, adhesive materials are used to secure integrated circuit package components together. The die is secured to the heat sink, the ringframe to the heat sink and the leadframe to the ringframe, using epoxy materials that flex over the operational temperature range of the circuit package. The flexibility of the adhesives accommodates large differences in expansion and contraction of CTE-mismatched materials. The heat sink and ringframe materials are neither restricted to CTE-compatible materials nor to materials that are compatible with high-temperature attachment processes. Adhesive mounting of the die avoids the use of lead-based solders used in typical assembly processes.

Abstract: The invention relates to a method and apparatus for controlling the temperature of integrated circuit chips. Specifically, the invention relates to method and apparatus for controlling the temperature gradient across integrated circuit chips.

Abstract: A semiconductor package (10; 14) comprises a semiconductor die (2; 2?) with a plurality of contact areas (4) on its active surface and an electrically conductive bump (7) on each contact area (4). The die (2; 2?) and electrically conductive bumps (7) are encapsulated in a plastic housing (11) so that the plastic housing (11) encapsulates at least sides of the die (2; 2?) and sides of the electrically conductive bumps (7).

Abstract: A wiring substrate 11 having a power feeding layer 24 and a ground conductive layer 27 is provided, and also an inverted F-type antenna 20 is provided on a sealing resin 17, which covers a semiconductor chip 12 and a chip parts 13 connected to the wiring substrate 11, and an inverted F-type antenna 20 is connected electrically to the power feeding layer 24 and the ground conductive layer 27.

Abstract: The package module comprising a first substrate, a first package, a second package and a molding compound. The first substrate has a first surface. The first package comprises a first chip and a liquid encapsulating compound. The first chip is disposed on the first substrate and electrically connected to the first substrate by a first gold wire. The liquid encapsulating compound encloses a second surface of the first chip and part of the first gold wire. A surface of the liquid encapsulating compound provides a platform. The molding compound encloses at least partial first surface of the first substrate, the first package and the second package.

Abstract: An integrated circuit (IC) includes a semiconductor material, electronic circuitry formed on the semiconductor material, a contact layer formed on the electronic circuitry, a final passivation layer formed on the contact layer and an under-bump metallurgy (UBM) formed on at least a portion of the final passivation layer. The contact layer includes a plurality of contacts pads for providing external access to the electronic circuitry. The final passivation layer includes a plurality of windows that extend through the final passivation layer to the contact pads. The UBM includes an aluminum layer having a thickness of about 800 angstroms to about 1200 angstroms, a nickel/vanadium (Ni/V) layer having a thickness of about 800 angstroms to about 1200 angstroms and a copper (Cu) layer having a thickness of about 800 angstroms to about 1200 angstroms.

Abstract: A wiring substrate 20, comprising a glass substrate, formed by integrally bundling a plurality of glass fibers and provided with through holes 20c, and conductive members 21, disposed at through holes 20c, is used. Input portions 21a of conductive members 21, formed on an input surface 20a of this wiring substrate 20, are connected to bump electrodes 17, which are provided on an output surface 15b of a PD array 15 in one-to-one correspondence with respect to conductive members 21, thereby arranging a semiconductor device 5. A radiation detector is arranged by connecting a scintillator 10 via an optical adhesive agent 11 to a light-incident surface 15a of PD array 15 and connecting a signal processing element 30 via bump electrodes 31 to output surface 20b of wiring substrate 20. A semiconductor device, with which the semiconductor elements and the corresponding conductive paths of the wiring substrate are connected satisfactorily, and a radiation detector using this semiconductor device are thus provided.

Abstract: A semiconductor device includes a semiconductor substrate having an electrode and a conductive pad; a resin projection formed on the semiconductor substrate; and a wiring electrically connected to the electrode, the wiring having a first portion formed on the electrode, a second portion formed on the conductive pad and a third portion formed on the resin projection between the first portion and the second portion.

Abstract: A semiconductor device including: a semiconductor substrate on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the semiconductor substrate, arranged along a straight line, and extending in a direction which intersects the straight line; and a plurality of electrical connection sections formed on the resin protrusions and electrically connected to the electrodes.

Abstract: A semiconductor device includes a semiconductor substrate in which an integrated circuit is formed and which includes interconnects and electrodes, the interconnects electrically connected with the semiconductor substrate, and the electrodes being formed on the interconnects; a resin layer formed on the semiconductor substrate; redistribution interconnects electrically connected with the electrodes; a plurality of external terminals which are formed on the redistribution interconnects and supported by the resin layer; and a plurality of dummy terminals supported by the resin layer without being electrically connected with the electrodes.

Abstract: Provided is a board-on-chip package and stack package using the same to reduce the likelihood that bonding wires in an encapsulant may be damaged due to mechanical stresses applied during a package stacking process. A semiconductor package may have a spacer provided along the opposing sides of an encapsulant. The spacer may be spaced away from bonding wires embedded in the encapsulant. The height of the spacer may be greater than the height of the encapsulated bonding wire from the bottom surface of the semiconductor package. The spacer may be formed of a bar or a protrusion. In a stack package using the semiconductor package, the spacer may be provided between a semiconductor chip of a lower semiconductor package and an encapsulant of an upper semiconductor package.

Abstract: A capacitive structure and technique for allowing near-instantaneous charge transport and reliable, wide-band RF ground paths in integrated circuit devices such as integrated circuit dies, integrated circuit packages, printed circuit boards, and electronic circuit substrates is presented. Methods for introducing resistive loss, dielectric loss, magnetic loss, and/or radiation loss in a signal absorption ring implemented around a non-absorptive area of one or more conductive layers of an integrated circuit structure to dampen laterally flowing Electro-Magnetic (EM) waves between electrically adjacent conductive layers of the device are also presented.

Abstract: A resistor element formed of a peel-preventive film, a recording layer made of chalcogenide, and an upper electrode film is formed on a semiconductor substrate, first and second insulation films are formed so as to cover the resistor element, a via hole for exposing the upper electrode film is formed through the first and second insulation films, and a plug for electrical connection to the upper electrode film is formed in the via hole. To form the via hole, the first insulation film made of silicon nitride is used as an etching stopper to perform dry etching on the second insulation film. Then, dry etching is performed on the first insulation film to expose the upper electrode film from the via hole.

Abstract: An interconnection structure includes a lower interconnection layer formed on a substrate and composed of a copper layer, an interlayer insulating layer formed on the lower interconnection layer and having a via reaching the lower interconnection layer, an upper interconnection layer electrically connected to the lower interconnection layer through the via, and composed of a copper layer formed in the interlayer insulating layer, and a barrier metal layer formed between the upper interconnection layer and the interlayer insulating layer. The barrier metal layer has an opening in a bottom portion of the via, and through that opening, the upper interconnection layer comes in direct contact with the lower interconnection layer in the bottom portion of the via. Thus, an interconnection structure suppressing concentration of voids in an interconnection under a via due to stress migration can be attained.

Abstract: According to one embodiment of the invention, there is provided a lead-free solder including an alloy rolled into a shape of sheet. The alloy includes: tin; from 10 wt % to less than 25 wt % of silver; and from 3 wt % to 5 wt % of copper. The alloy is free from lead.

Abstract: An electrical component having reduced substrate area is suggested, in which a substrate (S) having component structures (BS), on one surface of which solder metal platings (LA), which are electrically connected to the component structures, are positioned, is electrically and mechanically connected in a flip chip arrangement to a carrier (T) via bump connections formed by solder bumps (B). The solder bumps are seated on the solder metal platings of the substrate. At least one of the bump connections is seated on a non-round solder metal plating, which has a relatively small dimension along a first axis and a larger dimension along a second axis positioned transversely thereto.

Abstract: A chip packaging structure without leadframe includes a bare chip having one surface provided with a plurality of contacts, and an adhesive and a fixing layer sequentially attached to the surface of the bare chip with the contacts, and a plurality of lead wires sandwiched between the adhesive and the fixing layer. Each of the lead wires has an inner end electrically connected to one of the contacts on the bare chip via an inner connecting window area provided on the adhesive layer corresponding to the contacts on the bare chip, and an outer end extended to one of multiple outer connecting window areas provided on the fixing layer to electrically connect to one of many external conducting bodies implanted in and exposed from the outer connecting window areas, such that no leadframe is needed to enable further reduced volume and decreased packaging cost of the whole chip packaging structure.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component mounted to a substrate. The substrate carries a plurality of bond pads at a location substantially coplanar with a terminal surface of the microelectronic component. This enables a smaller package to be produced by moving the bond pads laterally inwardly toward the periphery of the microelectronic component.

Abstract: An epoxy resin composition is provided comprising (A) an epoxy resin, (B) a phenolic resin curing agent, (C) an inorganic filler, (D) a cure accelerator, (E) an adhesion promoter, and (F) a metal oxide. The metal oxide (F) is a combination of a magnesium/aluminum ion exchanger, a hydrotalcite ion exchanger, and a rare earth oxide in a ratio of 0.5-20:0.5-20:0.01-10 pbw, relative to 100 pbw of epoxy resin (A) and curing agent (B) combined.

Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant detach member on a top surface thereof, and is attached via its bottom surface to a chip mounted on a chip carrier. The detach member is sized larger than the heat sink and can be easily removed from the top surface of the heat sink. Subsequently, a molding process is performed to form an encapsulant for completely encapsulating the chip, the heat sink and the detach member. Then, a singulation process is performed to cut along predetermined cutting lines located between sides of the heat sink and corresponding sides of the detach member. Finally, the detach member and a portion of the encapsulant formed on the detach member are removed from the heat sink. The above fabrication method reduces the packaging cost.

Abstract: A method of dividing a wafer having a plurality of areas, which are sectioned by the streets formed on the front surface in a lattice pattern and a plurality of devices, which are formed in the sectioned areas, along streets, the method comprising a first cutting step for holding the front surface of the wafer on a chuck table of a cutting machine and forming a first groove having a depth that is about half of the thickness of the wafer, along the streets from the rear surface of the wafer; a second cutting step for holding the rear surface of the wafer on a chuck table and forming a second groove which does not reach the first groove, along the streets from the front surface of the wafer; and a dividing step for breaking an uncut portion between the first groove and the second groove by exerting external force along the streets of the wafer, on which the first grooves and the second grooves have been formed.

Abstract: A dehumidification and energy recovery device includes a casing defining an interior that is divided into two vertically stacked sections, a channel extending vertically between the sections and forming upper and lower openings, absorption devices arranged inside the channel corresponding to the sections respectively, and a tank arranged below the lower opening of the channel and containing a liquid that is driven by a pump to a position above the upper opening of the channel to drop onto and flow through the absorption devices. Intake airflow and exhaust airflow respectively pass through the sections, contacting the liquid flowing through the channel in a cross-flow fashion, whereby exchange of humidity and heat is performed between the airflows and the liquid to effect dehumidification and energy recovery with a simple structure and low costs.

Abstract: A pattern transfer method includes first through third steps. In the first step, a desired pattern is transferred onto a resin layer formed on a substrate, a release layer being disposed between the substrate and the resin layer. In the second step, which is executed after the first step, the pattern having been transferred onto the resin layer is transferred to the substrate and the release layer is partially exposed. In the third step, which is executed after the second step, the release layer present between the substrate and the resin layer is dissolved and is thus removed from the substrate.

Abstract: A carbon foam article useful for, inter alia, composite tooling or other high temperature applications, which includes a carbon foam having a ratio of compressive strength to density of at least about 7000 psi/g/cc.

Abstract: An air inversion and steam cure apparatus for installing a flexible resin impregnated cured in place liner in an existing conduit is provided. The apparatus has a low friction seal between a moving liner and the stationary apparatus gland. The gland is operated and adjusted by displaceable members that move substantially perpendicular to the liner being inverted to engage the moving liner as it passes through the gland. No part of the gland extends into the chamber so that once a pre-shaped gland is adjusted, the pressure on the moving liner is not increased. As the liner reaches the distal end, it enters a sample and porting pipe with an exhaust pipe gland and exhaust pipe and is pierced by a rigid porting tool. Steam is then introduced into the liner to cure the resin and is exhausted through an exhaust hose connected to the porting tool. After cure, steam is replaced with air to cool the liner and the ends are cut to restore service through the existing conduit.