Abstract: A power-on control circuit includes a coupling device coupled to a first voltage supply. A first inverter, coupled between the coupling device and a complementary voltage, has an input node coupled to a second voltage supply with a supply voltage level lower than that of the first voltage supply. A level shifter, coupled between the first voltage supply and the complementary voltage, has a first input node connected to an output node of the first inverter and a second input node coupled to the second voltage supply, for generating the power-on control signal when the first voltage supply is powered up and the second voltage supply is turned off and for disabling the power-on control signal when the second voltage supply is subsequently powered up. The coupling device eliminates a leakage current path from the first voltage supply to the complementary voltage through the first inverter.

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Abstract: A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.

Abstract: A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; a variable delay device (VDD), responsive to the control signal and a selection signal, to produce a delayed version of the external clock signal on a VDD output line, the variable delay device being configured such that, if the external clock signal undergoes a change from a first frequency to a second frequency significantly different than the first frequency, then a resultant load on the VDD output line nonetheless remains substantially the same.

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Abstract: A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power consuming portion operating at a relatively lower clock rate, by adjusting the duration of the cycles of the higher frequency clock. The adjustment may be according to the supply voltage changes that result from logic switching activity of the more power consuming portion, and may be performed in a manner that substantially matches the delay behavior of the logic. The phase of the higher frequency clock remains locked to the lower frequency clock. An embodiment of the present invention may reduce the area and cost of an integrated circuit by minimizing the need for other on-chip power supply noise mitigation approaches, while also improving device throughput and performance.

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Abstract: In a delay cell, a capacitor and a current mirror are configured to have an equivalent capacitance, and the current mirror establishes a capacitor displacement current to charge the capacitor, by which it is equivalently generated a much smaller current to charge the capacitor for a desired delay time. Therefore, the actual layout is much reduced in size for the capacitor, and the capacitor could be implemented within a chip.

Abstract: An object is to provide a clock supply circuit capable of supplying a clock signal with a short oscillation stabilization waiting time. There is provided a clock supply circuit having a filter removing from a first clock signal pulses having a shorter pulse width than a threshold value and passing pulses having a longer pulse width than the threshold value to thereby output a second clock signal; and a divider dividing the second clock signal to thereby output a third clock signal.

Abstract: A voltage switching circuit is provided which is constructed from a minimum number of transistors and prevents the threshold voltage margin from being lowered by causing high-voltage cutoff and supply voltage transfer functions heretofore performed by a single depletion transistor to be shared between two series-connected depletion transistors different in gate insulating film thickness or threshold voltage. Thus, without using enhancement transistors which involve an increase in pattern area a voltage switching circuit can be provided which is small in chip area, low in cost and high in yield and reliability and provides a stable operation with a low supply voltage which is impossible with one depletion transistor.

Abstract: A temperature detector circuit using a MOS transistor capable of reducing manufacture variation of a mobility and realizing stable output characteristics which are not affected by temperature dependency may be offered. In one example, the temperature detector circuit includes a pair of depression type transistors to output a voltage which is proportional to temperature from a connecting point of a source of a first transistor and a drain of a second transistor. The transistors are the same conducted type of current and are formed in different channel size, which are connected between power supplies in series, and have a configuration in which first transistor's gate and source are connected each other and a first transistor's drain is connected with a second power supply and second transistor's gate and drain are connected each other and a second transistor's source is connected with a first power supply.

Abstract: The present invention relates to a temperature-compensated bias source circuit. The temperature-compensated bias source circuit includes a bandgap reference circuit that outputs a first temperature-compensated reference voltage and a second reference voltage having a positive slope with respect to temperature; a voltage/current converter that converts the first and second reference voltages into a reference current; and an output buffer that is connected to the bandgap reference circuit and the voltage/current converter and buffers the first and second reference voltages, output by the bandgap reference circuit, so as to output to the voltage/current converter.

Abstract: A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the signature signal output by the signature program circuit during operation in a normal mode, and configured to pass the signature signal during operation in a test mode; and a pad-driving transistor directly coupled to the pad, configured to drive the pad during operation in the normal mode in response to an operation command, and configured to drive the pad during operation in the test mode in response to the signature signal output by the signature output circuit. The signature circuit outputs the signature information through a transistor for adjusting impedance to reduce a chip size by omitting an additional logic circuit for the signature circuit.

Abstract: A boosted voltage generator includes first and second pumping units and a pumping ratio controller. The first pumping unit is for pumping a first pumping ratio of charge at an output node in response to a first signal, and the second pumping unit is for pumping a second pumping ratio of charge at the output node in response to a second signal. The pumping ratio controller is for setting the first and second pumping ratios.

Abstract: A voltage reference generating method, source, memory device and substrate containing the same include a voltage reference generator comprised of a bandgap voltage reference circuit including a first complementary-to-absolute-temperature (CTAT) signal and a second complementary-to-absolute-temperature (CTAT) signal. The voltage reference generator further includes a differential sensing device for generating a reference signal substantially insensitive to temperature variations over an operating temperature range by differentially sensing the first and second CTAT signals. The method includes generating first and second complementary-to-absolute-temperature (CTAT) signals and generating a reference signal that is substantially insensitive to temperature variations over an operating temperature range.

Abstract: A voltage converting circuit has an output terminal for supplying an output current at an output voltage to a load. In response to a transient of the load, a current sinking circuit allows a current source to provide a sink current flowing from the output terminal of the voltage converting circuit into a ground potential. The sink current is finite and stable. When the output voltage decreases below a threshold voltage, the current sinking circuit allows the current source to keep providing the finite and stable sink current for an extension time, causing the output voltage to decrease from the threshold voltage to a regulated value.

Abstract: A constant current circuit that generates a constant output current corresponding to an input voltage, comprises a differential amplifying unit to which the input voltage and a feedback voltage to be compared therewith are applied, the differential amplifying unit outputting a differential voltage between the input voltage and the feedback voltage, a first transistor with a first control electrode to which the differential voltage is applied, a first diode element that is connected to a power-supply side electrode of the first transistor, one or a plurality of second transistors that generates the output current duplicated from a diode current by applying to a second control electrode a voltage drop in the first diode element developed as a result of the diode current flowing through the first diode element due to drive of the first transistor, a feedback voltage conversion block that converts the duplicated current of the diode current flowing through the second transistor into the feedback voltage, which is

Abstract: A current mirror circuit includes a pair of first and second transistors having bases connected together and emitters connected to a power line, a resistor connected between the bases of the first and second transistors and the power line, a third transistor for providing base currents of the first and second transistors and a resistor current flowing through the resistor, and a current compensation circuit that adds a compensation current to an input current to the first transistor. The amount of the compensation current is approximately equal to that of the resistor current divided by a current gain of the third transistor. Thus, the compensation current compensates the difference between a collector current of the first transistor and the input current.

Abstract: A leakage current control circuit with a single low voltage power supply is provided. The circuit includes a first power supply line, a second power supply line, a ground line, a high voltage generating circuit, a power transistor and a control circuit. The high voltage generating circuit generates a voltage in response to an internal sleep signal. The gate electrode of the power transistor is connected to the output of the high-voltage generating circuit such that the power transistor is controlled by the high voltage generating circuit. When the power transistor turns on, the circuit is in operation mode; when the power transistor is off, the circuit is in sleep mode. The control circuit connects to the first power line, the second power line, and the ground line to output the internal sleep signal in response to the sleep signal.

Abstract: An amplifier including an electronic tube with an axial electron beam, provided with a cathode and at least two collectors, and at least two sources of DC voltage. Each collector is connected to a DC voltage source having a potential difference such that, the further the collector is from the cathode, the lower the potential difference between this collector and the cathode. The DC voltage sources are connected together at a common point situated at the collector whose potential difference with the cathode is the lower but not zero.

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback, semiconductor devices, wafers and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a Complementary Metal Oxide Semiconductor (CMOS) amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor operably couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor operably couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion.

Abstract: An apparatus for effecting signal chopping in an amplifier device having an amplifier section, a modulation section, a ramp generating section and a clock section includes: at least one signal treating unit coupled among the clock section, the amplifier section and the ramp generating section. The at least one signal treating unit cooperates with the clock section to effect providing a chopping signal to the amplifying unit at a chopping frequency and to effect providing a ramping signal at a ramping frequency to the ramp generating section. The chopping frequency is neither a fundamental frequency nor a harmonic frequency of the ramping frequency.

Abstract: A class D amplifier includes a driver circuit and a reset circuit. The driver circuit is configured to amplify a PWM (pulse width modulation) signal to generate an amplified PWM signal. The reset circuit applies a predetermined voltage at an input of the driver circuit for a time period after a power supply voltage is applied or before the power supply voltage is deactivated, for eliminating pop-up noise.

Abstract: A high-frequency receiver has both interference characteristic and reception characteristic. The high-frequency receiver includes an electronic switch that is connected in parallel to input and output terminals of antenna amplifying circuit, and an antenna control unit that controls the electronic switch and an antenna amplifying circuit. When an antenna control signal output from a high-frequency receiving unit is input to the antenna control unit, the electronic switch is opened and simultaneously power supply to the antenna amplifying circuit starts in a weak electric field area, and the electronic switch is closed and simultaneously power supply to the antenna amplifying circuit stops in a strong electric field area.

Abstract: A circuit capable of improving communication quality. In this circuit, constant-envelope signal generating section (101) generates a first constant-envelope signal and a second constant-envelope signal from input signals (Si, Sq). Phase-shifter (102a) shifts the phase of the first constant-envelope signal by +?° and phase-shifter (102b) shifts the phase of the second constant-envelope signal by +?°. Local signal phase-shifter (107a) shifts the phase of the local signal from local oscillator (106) by ??°, and local signal phase-shifter (107b) shifts the phase of the local signal from local oscillator (106) by ??°. Mixers (103a, 103b) performs frequency-conversion of the first constant-envelope signal and the second constant-envelope signal from phase shifters (102a, 102b) using the local signals from local signal phase-shifters (107a, 107b). Amplifiers (104a, 104b) amplify signals from mixers (103a, 103b). Combining circuit (105) combines signals from amplifiers (104a, 104b).

Abstract: An integrated LDMOS power detection circuit for radio frequency power detection is disclosed wherein the circuit includes a first LDMOS transistor, a first resistor coupled between the first LDMOS transistor and a power source, a second LDMOS transistor coupled to the first LDMOS transistor, a input resistive voltage divider and at least one PMOS transistors coupled between the second LDMOS transistor and a second resistor, wherein the PMOS transistor functions as a current mirror for the circuit and the first and the second resistors function as a indirect resistor divider for the circuit.

Abstract: A transmitter includes generating unit configured to generate a feedback signal and an analyzing unit configured to analyze transmission quality in a time domain and in a frequency domain by using the feedback signal. The transmitter also includes an adapting unit configured to adapt the pre-distorter if the transmission quality is below the threshold.

Abstract: A data amplifying circuit for an output driver has a swing level that is controllable according to an operation mode. The data amplifying circuit includes a mode responding circuit supplying an additional source current to a source node of an amplifying circuit in response to a mode selection signal. The mode responding circuit controls the supply of the additional source current in accordance with an operation mode. Another data amplifying circuit of a semiconductor device, according to the invention, includes a small-swing amplifier and a full-swing amplifier. The small-swing amplifier causes a swing level of the output signal to be relatively smaller, while the full-swing amplifier causes the output signal swing level be relatively larger. The small-swing and full-swing amplifiers are alternatively enabled in response to the mode selection signal.

Abstract: A system for producing a control signal to a plurality of amplifiers sections to vary the gain of each one of the plurality of amplifier sections as a linear natural logarithmic function of an input gain control signal. The system includes a master circuit for producing a pair of currents with a ratio proportional to the linear natural logarithmic function of the input gain signal and a differential voltage. Each one of the amplifier sections includes: a replica of a portion of the master circuit fed by the produced differential voltage for producing a pair of currents produced in the master circuit; and an amplifier fed by the produced replicated currents, such amplifier having a gain proportional to the ratio of such replicated currents.

Abstract: An electrical load is supplied with power from a driving power source, and a microprocessor (CPU) controls the opening/closing current supply rate (duty factor) of an opening/closing element in accordance with target current and driving power source voltage so that open loop control is carried out to achieve predetermined target current. The voltage between both the ends of a current detecting resistor connected to the ground side of the opening/closing element is input as a monitoring voltage from a current detecting amplifying circuit portion through a multichannel AD converter to CPU. When the error between the comparison target voltage corresponding to the target current and the monitoring voltage is above a first permissible error, CPU judges that there is an abnormality sign, and if the error is above a larger second permissible error, CPU judges that there is appearing abnormality.

Abstract: A differential amplifier comprises an operational amplifier, comprising a positive output terminal, a negative output terminal, and a feedback terminal; a common mode sensing circuit coupled to the positive output terminal and the negative output terminal, for generating a sensed common mode voltage of the positive output terminal and the negative output terminal of the operational amplifier; and a feedback circuit comprising a common mode input terminal for receiving the sensed common mode voltage, a reference input terminal for receiving a reference voltage, and a first resistive component coupled between the common mode input terminal and the reference input terminal, the feedback circuit generating a feedback signal according to the common mode voltage and the reference voltage; wherein the feedback terminal of the operational amplifier receives the feedback signal of the feedback circuit.

Abstract: An amplifier has a voltage to current converter coupled between a first potential and a reference potential and includes a control input coupled to a voltage at an input of the amplifier for converting the voltage at the amplifier input into a corresponding output current. A current multiplier is fed by the output current for producing an increased current. The increased current is fed to a control electrode of a transistor. A feedback element provides the first potential to the voltage to current converter by coupling a voltage produced by the feedback element in response current through the transistor to the voltage to current converter.

Abstract: Reconfigurable distributed active transformers are provided. The exemplary embodiments provided allow changing of the effective number and configuration of the primary and secondary windings, where the distributed active transformer structures can be reconfigured dynamically to control the output power levels, allow operation at multiple frequency bands, maintain a high performance across multiple channels, and sustain desired characteristics across process, temperature and other environmental variations. Integration of the distributed active transformer power amplifiers and a low noise amplifier on a semiconductor substrate can also be provided.

Abstract: An amplifying circuit having a bias voltage setting mechanism includes: a first amplifying element that amplifies an input signal and outputs the amplified signal as an output signal; a bias voltage setting unit that generates a bias voltage from the output signal on the basis of a control signal, such as an AGC voltage; and a high impedance element (third resistor) by which the bias voltage is applied to an input portion of the first amplifying element and which, when a component for bias voltage setting, such as a fourth resistor, is externally provided in the bias voltage setting unit, prevents a capacitive component of the component for bias voltage setting from being equivalently connected with respect to the input portion.

Abstract: Providing a high frequency power amplifier circuit and a radio communication system which can control output power by a power voltage, produce sufficient output power in high regions of demanded output power and improve power efficiency in low regions of demanded output power. In a high frequency power amplifier circuit (RF power module) which comprises two or more cascaded FETs for amplification and controls output power by controlling power voltages of the FETs for amplification to gate terminals of which bias voltages of a predetermined level are applied, different transistors for power voltage control are provided for a last-stage FET for amplification and preceding-stage FETs for amplification. The transistors for power voltage control generate and apply the power voltage so that the preceding-stage FETs for amplification saturate when a demanded output level is relatively low.

Abstract: Control loops in a voltage regulator can be stabilized using minimal silicon area. A current limit signal, generated by a current limit control loop in the voltage regulator, can be divided to minimize a zero provided in a compensation set associated with a voltage control loop, thereby stabilizing both loops. The compensation set can include a resistor (the zero) and a capacitor (a pole) connected in series between output and input terminals of an amplifier. Dividing the current limit signal can include injecting a first portion of the current limit signal on a first side of the resistor and injecting a second portion of the current limit signal on a second side of the resistor. The ratio of the first and second portions can be based on a gain of the amplifier, thereby minimizing an effect of the resistor.

Abstract: A signal amplification apparatus which supplies an input signal to a signal processing section to perform signal processing on the input signal, amplifies a power supply voltage supplied from a power source section in accordance with the processed signal, and outputs the amplified power supply voltage. The apparatus includes output decrease prediction means for predicting decrease of the output signal on the basis of an amplitude of the input signal; power supply voltage correction signal generation means for generating a power supply voltage correction signal for correcting the power supply voltage of the power source section on the basis of the predicted decrease of the output signal; and feedforward control means for performing feedforward control of the power supply voltage of the power source section by using the power supply voltage correction signal.

Abstract: An amplifier, which has good linearity and noise performance, includes first, second, third, and fourth transistors and an inductor. The first and second transistors are coupled as a first cascode pair, and the third and fourth transistors are coupled as a second cascode pair. The third transistor has its gate coupled to the source of the second transistor, and the fourth transistor has its drain coupled to the drain of the second transistor. The first transistor provides signal amplification. The second transistor provides load isolation and generates an intermediate signal for the third transistor. The third transistor generates distortion components used to cancel third order distortion component generated by the first transistor. The inductor provides source degeneration for the first transistor and improves distortion cancellation. The sizes of the second and third transistors are selected to reduce gain loss and achieve good linearity for the amplifier.

Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: In order to reduce the area of a charge pump PLL, one may separate proportional component and integral component of the loop filter voltage, and add additional circuitry so as to make the integral component appear as though it is affected by a much larger value of capacitance than is actually used. In an aspect, a current mirror may be used to subtract a portion of the integral component of the loop filter voltage from the total loop filter voltage. The difference signal is then used to drive an oscillator in the charge pump PLL. In another aspect, a third integrator or auto-calibration loop is used to set a center frequency of the oscillator.

Abstract: To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal.

Abstract: Provided are a voltage controlled digital analog oscillator and a frequency synthesizer using the same, the oscillator comprising an oscillator having a frequency of an output signal being determined by a voltage inputted to an analog input end and a digital value inputted to a digital input end; and a digital tuner for comparing the voltage inputted to the analog input end to first and second threshold voltages and changing the digital value inputted to the digital input end according to the result, whereby it is possible to obtain a broadband frequency output with less noise.

Abstract: There is provided a voltage controlled oscillator (VCO) stably generating a clock of a 50% duty from a simple circuit to have an excellent duty correction function in noise. The VCO includes a VCO unit and a duty correction unit. The VCO unit generates first and second signals having a 180° phase difference to each other with an oscillation frequency according to a control voltage to output the first and second signals through first and second oscillation output terminals. The duty correction unit generates a clock signal of a 50% duty according to the first and second signals through the first and second oscillation terminals.

Abstract: Disclosed is a booster circuit comprising a voltage detection circuit for outputting a decision output signal for detecting a boosted voltage and controlling a voltage boosting operation, an oscillation circuit, and a plurality of charge pump circuits. The oscillation circuit includes an odd number of stages of control-type inverters. When the decision output signal from the voltage detection circuit indicates the voltage boosting operation (oscillation), the odd number of stages of inverters constitute a closed path. Oscillation outputs from outputs of the control-type inverters are thereby extracted, respectively. When the decision output signal indicates a stop of the voltage boosting operation (stop of the oscillation), output values of the control-type inverters are not inverted and held, and the oscillation is thereby stopped. The charge pump circuits receive output signals from the control-type inverters as clock signals, respectively, and operate.

Abstract: A crystal oscillator in which phase noise is reduced includes: a resonance circuit having a crystal unit and split capacitors connected to the crystal unit; a transistor for oscillation having a base connected to the connection node of the crystal unit and the split capacitors; an output line for connecting the node for connecting together the split capacitors and the emitter of the transistor; a crystal resonator inserted in the output line; and a resistor connected in parallel to the crystal resonator.

Abstract: A method of manufacturing a temperature compensated oscillator including the steps of assembling an oscillator in which an IC chip constituting a temperature compensation circuit with an oscillation circuit and a compensation data storage circuit, and a resonator for the oscillation circuit are mounted in a package; adjusting the resonator with an oscillation frequency of the oscillation circuit to a desired oscillation frequency in condition that the oscillator is kept at a reference temperature, in condition that a temperature compensation function of the temperature compensation circuit is disabled; sealing the resonator hermetically; creating temperature compensation data and storing it into the compensation data storage circuit; and enabling the temperature compensation function of the temperature compensation circuit.

Abstract: An oscillator circuit and system are provided having a peak detector that can determine a peak voltage value from the oscillator. The peak voltage value can then be compared against a predetermined voltage value by a controller coupled to the peak detector. The comparison value is then used to change a bias signal if the peak voltage value is dissimilar from the predetermined voltage value. A variable capacitor or varactor can be formed from a transistor and is coupled to the oscillator for receiving the bias signal upon a varactor bias node. The bias signal is used to regulate the capacitance within the varactor as applied to the oscillator nodes. Another controller can also be coupled to the peak detector to produce a second bias signal if the peak voltage is dissimilar from a second predetermined voltage value. The second bias signal can then be forwarded into an amplifier having a variable gain to regulate the gain applied to the oscillator.

Abstract: A variable capacitance network is disclosed, comprising a plurality of capacitance arms connected in parallel with each other between first and second terminals of the network. Each capacitance arm has a varactor and a series capacitor in series with the varactor A control input applies a common control signal to the junctions between the varactors and their associated series capacitors, to allow for simultaneous control of each varactor.

Abstract: A variable capacitance network is disclosed, comprising a plurality of capacitance arms connected in parallel with each other between first and second terminals of the network. Each capacitance arm has a varactor and a series capacitor in series with the varactor A control input applies a common control signal to the junctions between the varactors and their associated series capacitors, to allow for simultaneous control of each varactor.

Abstract: A cathode for use in a magnetron may include a plurality of longitudinally oriented emitter regions disposed around a longitudinal axis of the cathode. Each emitter region may be configured to emit electrons and adjacent emitter regions may be separated from one another by openings.