Abstract: A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

Abstract: A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant columns of memory is associated with a corresponding one of a plurality of memory sub-arrays. The columns of memory of the sets of local redundant columns of memory are adapted to replace defective columns of memory of the respective memory sub-arrays. The column redundancy system further includes columns of shared redundant memory that are adapted to replace defective columns of memory of the plurality of memory sub-arrays.

Abstract: A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant enable signal generating circuit programming defective addresses, during a mode setting operation and generating a redundant enable signal when the defective addresses are applied during an operation. The redundant decoder including decoders selecting a corresponding redundant column selecting signal line in response to the redundant enable signal, a corresponding block address, and a lower and upper block address, wherein each of the of decoders is electrically connected to one of the lower and upper blocks.

Abstract: Source potential connection transistors, each supplying a source control potential from a source potential wiring to a source node, are disposed so as to be dispersed in a memory cell array. In addition, a source potential control circuit is disposed inside a row decoder block. With this configuration, the number of the cells connected to each word line can be increased, and the area of the memory core can be reduced. Furthermore, the pattern shape of the diffusion layer constituting the source potential connection transistor is made the same as that of the diffusion layer of a memory cell transistor, whereby mask creation can be facilitated.

Abstract: A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.

Abstract: A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of storage cells are tested in a first retention test to identify rows that fail to retain data over the specified time interval. The rows that fail to retain data over the specified time interval are tested in a second retention test to identify rows that retain data over an abbreviated time interval, the abbreviated time interval being shorter than the specified time interval.

Abstract: An data recording device according to an aspect of the present invention includes a memory cell array in a memory chip, a refresh circuit which executes a refreshing of the memory cell array, a refresh control circuit which executes refreshing at a time interval which is shorter than a data hold time and manages a data hold time, and an internal power source which supplies a power source electric potential to the refresh circuit and the refresh control circuit in a state in which the data recording device is removed from an external device.

Abstract: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.

Abstract: A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

Abstract: Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large memory arrays the leakage current is a considerable portion of the overall power consumption, leakage reduction in memory arrays, manufactured by advanced processing technologies, is a major challenge. To reduce leakage, methods and apparatus are presented for memory access and for power- and ground-supply monitoring and management at memory sub-array level.

Abstract: The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one shadow memory bank which are each designed to store a multiplicity of binary data items, the same data as in the first memory bank being stored in the shadow memory bank; receiving a command for reading data which are to be read from the first memory bank; utilizing a state checking device of the semiconductor memory to check whether the first memory bank is in an open memory bank state, and, if the first memory bank is in the open memory bank state, reading the data which are to be read from the at least one shadow memory bank, and, if the first memory bank is not in the open memory bank state, reading the data which are to be read from the first memory bank, the open memory state being such a memory state of the memory bank which does not allow the data which are to be read to be read without previously closing an

Abstract: A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable buffers vary the strength of at least some of the output signals in response to a configuration control signal, such that the output signals can be optimized for the loads to which they will be connected.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty cycle irrespective of the duty cycle of the clock input to the DCC circuit. A DCC initialization scheme selectively activates the frequency division and edge detection operations in the DCC based on the lock status of the DCC during initialization. Upon initialization, the frequency division and edge detection operations are turned off or disabled. After the DCC is properly locked, these operations are enabled to obtain the 50% duty cycle output clock. This approach initializes the reduced-frequency DCC without output glitches, which can affect locking of a DLL with which the DCC may be used. The prevention of instability in locking of the DCC and DLL upon system initialization results in swift establishment of DCC and DLL locks without significant power consumption or loss of clock cycles.

Abstract: An apparatus for testing or programming a nonvolatile memory in a micro control system and a method thereof is provided. The micro control system comprises: a nonvolatile memory for storing data; an address register for storing an address; a data register for storing serial data; control logic for controlling the nonvolatile memory, the address register and the data register; a clock pin for receiving a clock; a data pin for receiving serial data synchronized with the clock; and a timer for measuring time.

Abstract: Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on the direction of current flow, and a page buffer driven to map three data bits to threshold voltage groups of the two charge trap regions. The charge trap-type non-volatile semiconductor memory device has charge trap regions each storing 1.5 bits of data. That is, a single memory element has charge trap regions for storing 3 bits of data, thereby improving device integration while maintaining a high operating speed during programming and reading operations.

Abstract: A blender has a container body, a push plate, a blade assembly that is mounted on the push plate and a guide rod mounted to the container body and affixed to the push plate limiting the push plate to substantially vertical movement. A variety of well known lifting mechanisms can be mechanically actuated by the handle and can also be actuated by a squeeze mechanism where the handle travels linearly as opposed to rotationally. To overcome the stickiness drawback in blender container bodies, the present invention uses a push plate to push the contents out of the container body.

Abstract: A food processor includes a drive unit, a food processing tool driven rotatably by the drive unit, a rotary support, and a transmission device. The transmission device includes a first transmission unit driven rotatably by the drive unit and defining a first drive axis, a second transmission unit driving rotation of the rotary support and defining a second drive axis, and a coupling member that couples the first transmission unit to the second transmission unit. The coupling member permits movement of the first transmission unit relative to the second transmission unit from a first position, where the first drive axis is aligned with the second drive axis, to a second position, where the first drive axis forms an angle with the second drive axis. The coupling member enables transmission of drive power from the drive unit to the rotary support when the first transmission unit is at the first position.

Abstract: A system for pumping or mixing a fluid using a rotating pumping or mixing element and various other components for use in a pumping or mixing system are disclosed.

Abstract: A method and apparatus for use in seismic prospecting are disclosed. The method includes: attenuating coherent noise in a seismic data set generated from a sweep signal; and correlating the coherent noise-attenuated seismic data set to the sweep signal. The apparatus includes a program storage medium encoded with instructions that, when executed by a computing device perform the method and a computer programmed to perform the method.

Abstract: A method of characterizing shear wave anisotropy in a formation includes obtaining crossed-dipole waveforms from a borehole penetrating the formation over a range of depths and frequencies, determining far-field slowness in a fast-shear and slow-shear direction using a low-frequency portion of the crossed-dipole waveforms, and determining near-wellbore slowness in the fast-shear and slow-shear directions using a high-frequency portion of the crossed-dipole waveforms. The method also includes marking a selected depth of the formation as having intrinsic anisotropy if at the selected depth the far-field slowness in the fast-shear direction is less than the far-field slowness in the slow-shear direction and the near-wellbore slowness in the fast-shear direction is less than the near-wellbore slowness in the slow-shear direction.

Abstract: An acoustic telemetry apparatus and method for communicating encoded digital data from a down-hole location through a borehole to the surface is described including an acoustic channel terminated at a down-hole end by a reflecting terminal (133, 134), an acoustic wave generator (140) located at the surface and providing an acoustic wave carrier signal through said acoustic, channel, a modulator (162, 163) located down-hole to modulate amplitude and/or phase of said carrier wave in response to an encoded digital signal and one or more sensors (150) located at the surface adapted to detect amplitude and/or phase related information of acoustic waves traveling within said acoustic channel to determine the encoded digital data.

Abstract: Systems and methods for locating the shooter of supersonic projectiles based on shockwave-only measurements are described. Muzzle blast signals are neither sought nor required. The system uses at least five, preferably seven, acoustic sensors that are spaced apart at least 1 meter. The sensor signals are acquired with a time resolution in the order of microseconds and processed to find and disambiguate the shockwave arrival angle unit vector. Two different Time-Difference-Of-Arrival (TDOA) measurement techniques are described, with one technique using counters in each signal channel and the other technique using cross-correlation between signal channels. A genetic algorithm can be used to efficiently disambiguate the results.

Abstract: The invention relates to a timer device capable of performing one or more control actions in response to the time lapsed since a user initiated action took place. The timer device comprises contact means operatable between two conditions, timer means, and means for storing first and second time stamps. The device further comprises control means for setting a first time stamp in response to the contact means being operated between first and second conditions, setting a second time stamp in response to the contact means being operated between the second and first conditions, calculating the time elapsed between the two time stamps, comparing the elapsed time with a preset time value, and performing a control action if the elapsed time is greater than the preset time value.

Abstract: An alarm clock device includes a monitor for monitoring a transmission of a selected station, a detector for detecting, in the transmission of the selected station, at least one milestone. A controller operating in response to detection of the milestone is provided to store, in a memory, data of the transmission after the milestone was detected, and to initiate playing of the data at a selected wakeup time. According to the present invention, the data is recorded in response to detecting a transmission of a selected station selected from a plurality of stations.

Abstract: A multiple-drive recording and reproduction apparatus of the invention includes a system controller which, upon duplication of information recorded on a hard disc onto an optical disc, on the hard disc device side, compresses and tentatively reproduces, at a bit rate changed, predetermined time's worth of video data from the beginning of a video and displays the video on a display part, and, if the user views and approves rough image quality of the video tentatively reproduced and displayed, compresses the video data targeted for duplication and then starts the duplication. According to this configuration, when the recording bit rate is changed upon the duplication of the information from the hard disc to the optical disc, the video at this point can be confirmed.

Abstract: When a multi layer record carrier comprimising video information is to be duplicated on another multi layer record carrier the data spread over two recording layers on the source record carrier must also be spread over the two layers of the target record carrier. Once an appropriate layer transition for the target record carrier has been established the size of the first layer is adjusted by moving the first logical address, thus limiting logical address space on the first layer of the target record carrier to exactly fit the video information obtained from the first layer of the source record carrier. Once the logical address space has been adjusted the layer transition will happen automatically at the correct point in the video information during the recording.

Abstract: A magnetic recording disk drive with rotational vibration (RV) cancellation uses the position error signal (PES) and the signal from a RV sensor to determine when to enable and disable RV cancellation. An RV feedforward compensation signal to be summed with the VCM control signal is “switchable”, meaning that it can be enabled or disabled by the disk drive servo control processor. The determination to enable or disable is made from a comparison of the PES with a threshold PES, which may be an estimate of the off-track position of the head calculated from the RV sensor signal. The estimated off-track is compared to the absolute value of the actual or measured PES. If the estimated off-track is smaller than the actual PES, then the state of the RV cancellation is switched, i.e., if it is enabled it is disabled and if it is disabled it is enabled.

Abstract: The present invention has an object to stably reproduce wobble signals of all disks of CD-R/RW, DVD-R/RW and DVD-RAM by one wobble signal reproducing circuit. In the wobble signal reproducing circuit, an AGC (AUTOMATIC GAIN CONTROL) circuit for equating a push-pull circuit output of a wide range and an RF amplitude of an optical detector output of two systems obtained by push-pull, and an AGC (AUTOMATIC GAIN CONTROL) circuit for making a wobble amplitude uniform are provided with a function to hold a gain or to change over a response time constant, and at the time of reproduction of the DVD-R/RW, a land pre-pit region is detected by the push-pull output to hold AGC (AUTOMATIC GAIN CONTROL) or change over a response time constant. Besides, in an address information recording region (PID region) at the time of reproduction of the DVD-RAM, the AGC (AUTOMATIC GAIN CONTROL) is held or the response time constant is changed over.

Abstract: An optical pickup performing recording, reproduction and deletion of information onto an optical recording medium, said optical pickup includes light sources of blue wavelength zone, red wavelength zone and infrared wavelength zone; a single object lens which condenses a light from any of the light sources; and a single aberration correction device disposed in a common light path between each of the light sources and the object lens.

Abstract: A method for automatically correcting an operation type of a disk drive sets a number of times of normal track seeking of the disk drive as a standard. When executing track seeking commands, the method also detects whether a number of times of track seeking in the track seeking commands is greater than the standard, judges occurrence of an abnormal track seeking phenomenon, judges a correct operation type according to an operation type setting of the disk drive and a track seeking direction, automatically corrects and switches a misjudged operation type into the correct operation type setting, and restores to the original operation type setting after the operation type is controlled and switched for a predetermined number of times so as to timely and automatically revise the misjudged operation type setting.

Abstract: An optical disc apparatus is capable of performing at least one of recording, reproduction and erasure of information, the optical disc apparatus. An optical pickup device irradiates a light onto an optical disc and receives the light reflected by the optical disc so as to output an output signal. A servo signal detection circuit detects a focus error signal from the output signal. An automatic gain control circuit amplifies the focus error signal according to one of a plurality of gains including a previously set fixed value. A control part sets the gain of the automatic gain control circuit to the previously set fixed value when the optical disc is set to a predetermined position in the optical disc apparatus.

Abstract: An information recording apparatus is provided with: a recording device for recording information onto an information recording medium; a detrack detecting device for detecting occurrence of detrack during the recording of the information; and a controlling device for controlling said recording device to return to a location where the detrack has occurred and restart the recording if the occurrence of the detrack is detected

Abstract: A method is described for compensating tilt (0) of an optical disc (2). An optical lens (34), which is pivotably mounted, is pivoted to an optimum pivot position (WoPT) such that the amplitude (ATE) of the push-pull tracking error signal (STE) is maximal. Said optimum pivot position (WOPT) is determined by measuring said amplitude (ATE) at different pivot positions (yr(i)) and calculating a maximum point (yroPT, ATE,MAx) of a best parabolic fit (80) through the measurements (y(i), ATE(i)).

Abstract: Modified HDD sector formats have multiple sets of preamble data. The preambles are well separated so that any defect long enough to wipe out both preambles would also overwhelm the ECC.

Abstract: A super-resolution information recording medium, a recording/reproducing apparatus, and a recording/reproducing method uses an information recording medium provides a super-resolution effect by fluid bubbles. The fluid bubbles are formed in at least a portion of the medium by a light beam radiated to reproduce a signal from the information recording medium. Accordingly, the super-resolution information recording medium has improved optical characteristics, so that better recording/reproduction is possible.

Abstract: An optical disk device which decodes data recorded on an optical disk, comprises a first measuring unit which measure a cycle of a plurality of first synchronous signal regions VFO contained in a reproduction signal from an optical pickup, a cycle comparing unit which compares the measurement result of the first measuring unit with a first predetermined cycle, a second measuring unit which measures a cycle of a plurality of second synchronous signal regions SYNC which are contained in the reproduction signal from the optical pickup and have the cycle shorter than that of the plurality of first synchronous signal regions VFO, a cycle comparing unit which compares the measurement result of the second measuring unit with a second predetermined cycle, and an oscillator which generates a clock signal CKS for sampling the reproduction signal on the basis of the comparison results of the first and second cycle comparing units.

Abstract: A method of determining a recording power used to record information to an optical disc, includes carrying out test recording which records predetermined data to a predetermined area of the optical disc to determine the recording power, and recording predetermined data with a power equal to or more than the determined recording power to an area adjacent to the predetermined area.

Abstract: An optical disc includes tracking polarity information. The optical disc includes a clamping area, a lead-in area, a data area, and a burst cutting area (BCA). The BCA is present between the clamping area and the lead-in area and in which information regarding the optical disc is recorded, and the information is read before performing tracking in the data area. Accordingly, it is possible to obtain the tracking polarity information and/or reflectivity information without trial and error and directly record or reproduce user data in a data area of the optical disc.

Abstract: The invention relates to a system and a method of estimating the tangential tilt of an optical data carrier (302) intended to store a primary data signal (301), said method comprising a cross-correlating step for correlating a first data signal (m) derived from a readout data signal (z) with a second data signal (w) derived from a data decision signal (DDS), said readout data signal (z) being derived from said primary data signal (301).

Abstract: A system and method for writing and extracting tamper resistant security data onto optical media such as for example CDs and DVDs. A unique digital identifier may be embedded onto the lead-in area and/or lead-out area of an optical media, which areas are inaccessible in conventional optical media readers. The digital identifier includes data which, when read, may be used to validate the authenticity of the media, including for example a unique digitally signed serial number for the media, the time and date the media was fabricated and a location where the media was fabricated.

Abstract: The present invention relates to a method and apparatus for finalizing a dual layer disc medium. The present invention checks whether particular areas on each recording layer of a dual layer recording medium separated from each other, e.g., the innermost circumference of data zone and around an area of radius 4 cm, are unrecorded and records null data in a particular area found to be unrecorded and carries out finalization. The present invention has an advantage in that time needed for finalization is considerably reduced compared with a traditional procedure of recording null data throughout the entire unrecorded data section.

Abstract: A disc drive apparatus (1) is described, comprising a data engine system (20) and a data processing system (30) in data communication with each other. The data engine system (20) and the data processing system (30) are also in a conferring communication with each other regarding the timing of recalibration. The data engine system (20) is designed to determine (step 120; 320) a moment when a recalibration procedure would be desirable, and to send (step 121; 321) a recalibration request signal to the data processing system (30). The data processing system (30) may or may not send (step 230; 430) a recalibration permission signal to the data engine system (20). The data engine system (20) only performs (step 132; 332) a recalibration procedure after having received the recalibration permission signal from the data processing system (30).

Abstract: A light source driving unit includes a modulating signal generating section generating modulating signals based on driving waveform generating information of a light source, a current source selecting section selecting one or more currents output from current sources based on the modulating signals, a light source driving section generating a current having multi-levels based on the one or more currents selected and supplying the generated current to the light source to drive the light source so that light in multi-levels is generated from the light source, and a cancelling section adding a signal error amount which cancels differences in amounts of signal delays generated between the modulating signal generating section and the light source driving section at a stage prior to the current source selecting section.

Abstract: A light source driving unit includes a modulating signal generating section generating modulating signals based on driving waveform generating information of a light source, a current source selecting section selecting one or more currents output from current sources based on the modulating signals, a light source driving section generating a current having multi-levels based on the one or more currents selected and supplying the generated current to the light source to drive the light source so that light in multi-levels is generated from the light source, and a cancelling section adding a signal error amount which cancels differences in amounts of signal delays generated between the modulating signal generating section and the light source driving section at a stage prior to the current source selecting section.

Abstract: A method of storing/retrieving information to/from an optical disc by means of an optical system with a cut-off frequency ?cut-off, above which frequencies cannot be detected, is disclosed. The invention relates to Run Length Limited encoded information. According to the invention, some frequencies of the encoded information can be higher than cut-off frequency of the optical system, such that the equation 4*(d+1)*Lcd*NA/?laser<1 is satisfied, where d+1 is the minimum run length of the coding, Lcd is the length of a channel bit, NA is the numerical aperture and ?laser is the wavelength of the optical system. Hereby, the capacity of the optical disc is increased, while the prevailing coding technique is used. Moreover, the invention relates to a disc for storing of data, a drive capable of storing data and an apparatus for manufacturing optical discs.

Abstract: An apparatus writes and reads data with respect to a holographic storage medium. The holographic data writing apparatus includes a laser beam irradiating device irradiating a laser beam onto a storage medium which is capable of writing a holographic data thereon; and a reflective data mask arranged adjacent to the storage medium and storing data for copy thereon, and when the laser beam is transmitted through the storage medium and is incident on the reflective data mask, the reflective data mask reflects the incident laser beam in the form of a signal beam corresponding to the data, and irradiates the signal beam onto the storage medium, such that interference patterns of the laser beam and the signal beam are written in the storage medium.

Abstract: An optical pickup has a semiconductor laser, a diffractive optical element that has first diffraction regions and second diffraction regions and diffracts a beam emitted by the semiconductor laser, an objective lens that focuses the diffracted beam on an optical disc, and a detection unit that detects a tracking error signal using the diffracted beam reflected by the optical disc. When a zero order diffraction beam is focused on the optical disc, a first order diffraction beam is diffracted by the first diffraction regions to be focused at a position between the objective lens and the optical disc, and diffracted by the second diffraction regions to be focused at a position beyond the optical disc. The first order diffraction beam has a beam width that, on the optical disc in a radial direction thereof, is two times or greater a track pitch of the optical disc.