Patents Issued in February 13, 2007
  • Patent number: 7176559
    Abstract: An integrated circuit package includes a balanced-part structure. The condition of thermal stress of chips connected on a substrate decides the amount, locations, weights, and the material of at least a balanced-part fastened on a substrate. The balanced-part is fastened on the substrate to balance stress distribution before an adhering heat sinks process and a packaging molding compound process. The balanced-part also decreases thermal stress affection and avoid warpage defects of the integrated circuit packages.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: February 13, 2007
    Assignee: Via Technologies, Inc.
    Inventors: Kwun Yao Ho, Moriss Kung, Terry Ku, Andy Liao
  • Patent number: 7176560
    Abstract: A semiconductor device having a chip-on-chip structure wherein; a first semiconductor chip with a memory macro control circuit where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; and a second semiconductor chip with memory macro having input/output terminals for the normal operation mode and for the test mode where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; are adhered to each other in a form so that the surfaces of the chips are opposed to each other and so that the inter-chip connection terminals of the first semiconductor chip and the inter-chip connection terminals of the second semiconductor chip are connected to each other; is provided wherein a multiplexer circuit and a demultiplexer circuit are provided with the first semiconductor chip and the second semiconductor chip so that a signal is inputted to, or is outputted from, the
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenji Motomochi
  • Patent number: 7176561
    Abstract: A semiconductor device includes a first package, a second package, a contact part for electrically coupling a first wiring pattern to a second wiring pattern, and a reinforcer. The thermal expansion coefficient of the first package is larger than that of the second package. The second package is disposed so that the second interposer overlaps the first semiconductor chip and the first interposer. The contact part is provided between the first and second interposers so that a first end is coupled to the first wiring pattern and a second end is coupled to the second wiring pattern. The reinforcer is provided to expose part of the contact part and cover the circumference of the first end of the contact part.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: February 13, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Akiyoshi Aoyagi
  • Patent number: 7176562
    Abstract: A semiconductor wafer includes a semiconductor substrate having a plurality of integrated circuits and electrical interconnections electrically connected to each of the integrated circuits. The semiconductor substrate includes bonding pads formed on a surface of the semiconductor substrate. Each of the bonding pads is part of a corresponding electrical interconnection. First resin layers are each disposed on each of a plurality of areas on the semiconductor substrate and have ridged edges. Wirings are each disposed over a corresponding bonding pad and a corresponding first resin layer and are electrically connected to the corresponding bonding pad. External connection terminals are each disposed on a corresponding wiring and are electrically connected to the corresponding wiring.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: February 13, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Takayoshi Obinata
  • Patent number: 7176563
    Abstract: Electronically grounded heat spreaders are employed in connection with the dissipation of heat, which is generated by electronic devices, such as semiconductor chips. Also provided is a novel method for the adhesive fastening of metallic heat spreaders to semiconductor chips through the combined use of electrically conductive and non-conductive adhesive materials.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: February 13, 2007
    Assignee: International Business Machine Corporation
    Inventors: Eric Duchesne, Michael A. Gaynes
  • Patent number: 7176564
    Abstract: A heat spreader includes thin films opposite to each other; cooling liquid filling an internal space between the thin films; and a vibration generating means for vibrating the liquid. Accordingly, the heat spreader has excellent heat spread performance compared to a conventional heat spreader, so can have an ultra slim type structure. Also, the heat spreader has excellent heat spread performance regardless of a direction of gravity, and a space between the thin films is sealed in a state of an atmospheric pressure, to maintain the improved heat spread performance for a long time.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: February 13, 2007
    Assignee: Korea Institute of Science
    Inventor: Seo Young Kim
  • Patent number: 7176565
    Abstract: A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Yuan-Liang Li, David G. Figueroa, Chee-Yee Chung
  • Patent number: 7176566
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: February 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Tim J. Bales
  • Patent number: 7176567
    Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: February 13, 2007
    Assignee: Advanced Chip Engineering Technology Inc.
    Inventors: Wen-Kun Yang, Kuang-Chi Chao, Cheng-hsien Chiu, Chihwei Lin, Jui-Hsien Chang
  • Patent number: 7176568
    Abstract: A semiconductor device is provided having: a board; a metallization pattern formed on the first face of the board; a first layer formed so as to not cover the first portion of the metallization pattern but to cover the second portion; and a semiconductor chip mounted on the first face of the board and electrically connected with the metallization pattern in the first portion. A resin portion is provided between the semiconductor chip and the board and from there onto the first portion of the metallization pattern outside the semiconductor chip so as to not reach a boundary between the first and second portions. A second layer is provided on the second face of the board so as to overlap the boundary of the metallization pattern and not overlap the resin portion.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: February 13, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuhiro Urushido
  • Patent number: 7176569
    Abstract: Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud bump of the semiconductor chip and an interconnect of a tape substrate, wherein an adhesive layer formed integral as a film is adhered to each block made of substrates corresponding to a plurality of semiconductor devices and contact bonding under heat is conducted. The adhesive layer corresponding to the plurality of semiconductor devices is thus formed continuously and with this adhesive layer, the interconnect formation surface at the end portion of the substrate is covered. Moreover, with a thermosetting resin used as the adhesive layer, the semiconductor chip and substrate are adhered by contact bonding under heat while placing the substrate on a rigid heat insulating plate.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: February 13, 2007
    Assignees: Renesas Technology Corp., Renesas Eastern Japan Semiconductor, Inc.
    Inventor: Tsukio Funaki
  • Patent number: 7176570
    Abstract: A tip of a wire formed in the shape of a ball is bonded to an electrode by using a tool. A part of the wire is drawn from the tip bonded to the electrode. A bump is formed on the electrode by deforming a portion of the wire continuous with the tip on the tip by using the tool. The wire is cut while leaving the bump on the electrode.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: February 13, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Takuya Takahashi
  • Patent number: 7176571
    Abstract: A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: February 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yi-Lung Cheng, Ying-Lung Wang
  • Patent number: 7176572
    Abstract: A semiconductor wafer includes a redistribution layer which is electrically connected with a pad which is an end portion of an interconnect, a first resin layer which is formed over the redistribution layer, a second resin layer which is formed over the first resin layer and covers the side surface of the first resin layer, and an external terminal which is formed to be electrically connected with the redistribution layer in a manner to avoid the pad.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: February 13, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Terunao Hanaoka
  • Patent number: 7176573
    Abstract: A semiconductor device includes a semiconductor die and a multi-level interconnect structure that has a first insulating layer formed on the die, conductive horizontal bodies, each of which is connected to a respective bonding pad of the die and has an extension formed on the first insulating layer, a second insulating layer formed on the first insulating layer, and conductive vertical bodies, each of which is connected to the extension of a respective conductive horizontal body and extends through the second insulating layer.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: February 13, 2007
    Inventor: Yu-Nung Shen
  • Patent number: 7176574
    Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: February 13, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
  • Patent number: 7176575
    Abstract: An electronic device includes a material having a first dielectric constant (K) value, and a material having a second dielectric constant (K) value. The first dielectric constant (K) value is lower than the second dielectric constant (K) value. The electronic device also includes input/output connection conductors for transmitting signals to and from a die. The input/output connection conductors are routed through the material of the interposer having the first dielectric constant. The electronic device also includes power connection conductors for delivering power to the die, and ground connection conductors. The power and ground connection conductors are routed through the material having the second dielectric constant.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Larry E. Mosley, Cengiz A. Palanduz, Victor Prokofiev
  • Patent number: 7176576
    Abstract: A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material comprising the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may comprise annealing the first and second layer. An exemplary first metal comprises copper, and an exemplary second metal comprises aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: February 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Dinesh Chopra, Fred Fishburn
  • Patent number: 7176577
    Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the fist conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: February 13, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yusuke Harada
  • Patent number: 7176578
    Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1), having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V 50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10–V60) are chosen having mutually different thermoelectric properties.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: February 13, 2007
    Assignee: Senseair AB
    Inventors: Hans Evald Goran Martin, Klas Anders Hjort, Mikael Peter Erik Lindberg
  • Patent number: 7176579
    Abstract: The present invention realizes the miniaturization of a semiconductor module. The semiconductor module includes a module board having external electrode terminals and a heat radiation pad over a lower surface thereof, a first semiconductor chip incorporating an initial-stage transistor of a high frequency power amplifying device therein, a second semiconductor chip incorporating a next-stage transistor and a final-stage transistor therein, and an integrated passive device which constitutes a matching circuit. At least one of the first semiconductor chip and the second semiconductor chip and the integrated passive device are mounted over an upper surface of the module board in an overlapped manner.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Satoru Konishi, Tsuneo Endoh, Hirokazu Nakajima, Masaaki Tsuchiya
  • Patent number: 7176580
    Abstract: Disclosed are structures and methods that facilitate the use of wire bonding technology over active areas of an IC chip. The invention is also suitable for use with IC structures that use brittle dielectric materials such as low K dielectrics.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: February 13, 2007
    Inventor: Joseph Fjelstad
  • Patent number: 7176581
    Abstract: A surface, which is opposite to a plane polygon of a resin layer, includes a third side opposed to a first side of the plane polygon, and a fourth side oppose to a second side of the plane polygon. A first space between the first side and third side is narrower than a second space between the second side and fourth side. A plurality of electrodes are arranged in a first region located between the second side and the fourth side and are spaced apart from a second region located between the first side and the third side. The third side comprises a first curved line and a pair of second curved lines connected to both ends of the first curved line. The first curved line is convexly bent toward the inside of the resin layer and each of the second curved lines is convexly bent toward the outside of the resin layer.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: February 13, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Takeshi Yuzawa
  • Patent number: 7176582
    Abstract: In an example embodiment, the semiconductor device comprises a carrier and a semiconductor element, such as an integrated circuit. The carrier is provided with apertures, thereby defining connecting conductors having side faces. Notches are present in the side faces. The semiconductor element is enclosed in an encapsulation that extends into the notches in the carrier. As a result, the encapsulation is mechanically anchored in the carrier. The semiconductor device can be made in a process wherein, after the encapsulating step, no lithographic steps are necessary.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: February 13, 2007
    Assignee: NXP B.V.
    Inventors: Hendrik Klaas Kloen, Gerardus Henricus Franciscus Willebrordus Steenbruggen, Peter Wilhelmus Maria Van De Water
  • Patent number: 7176583
    Abstract: A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: February 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • Patent number: 7176584
    Abstract: A wind power apparatus utilizing an anchor which is rotatably fixed to a surface. A chute attaches to the anchor and is provided with a chamber. A restriction is located in the chamber to concentrate the wind within an annular are of the chute and direct it to a power generator. The power generator is then used to produce electricity, move an object, and the like.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: February 13, 2007
    Inventor: C. Raymond Green
  • Patent number: 7176585
    Abstract: A power management device (200) and a method for use in a power distribution network (100) receives electrical energy and first determines if the power is a primary or secondary power source. When a secondary power source, the power management device (200) waits in standby mode, but when the power is primary power source the power management device (200) configures itself to route power to another node in the power distribution network (100). Power levels and faults within the network can be monitored and controlled by a central controller. Likewise loads (218, 220) may then be powered on as determined by a central controller to reduce LdI/dt voltage spikes and other undesirable side effects.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: February 13, 2007
    Assignee: Temic Automotive of North America, Inc.
    Inventor: Walton Fehr
  • Patent number: 7176586
    Abstract: Grip actuated control system to provide operational control of vehicle functions at a gripping surface of handlebar equipped vehicles. The system can be provided as original equipment and as an aftermarket addition or replacement for existent vehicle controls. The system includes one or more grip controls positioned adjacent a user's fingertips in a grip or glove assembly which are in communication with a control module. The control module is connected to existent or provided vehicle wiring and thus to respective operational equipment such that user actuation of a grip control induces the control module to provide a corresponding output to activate/deactivate or regulate the operation of the respective vehicle equipment. Communication between the grip controls and control module can be wireless for increased flexibility in installation and placement of the module on the vehicle. Combinations, sequences, and relative timing of the grip controls can provide numerous distinct control functions.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: February 13, 2007
    Inventors: Timothy Gerald Ledford, Steven O'toole Dodson
  • Patent number: 7176587
    Abstract: A sensor adapted for connection to a bus and a method for supplying power to a sensor connected to a bus are described, which serve to minimize the power consumption of a sensor connected to the bus. To this end, power for a sensor is stored in an energy storage device in a first time period and is discharged in a second time period, that is, the measurement time, in order to supply the sensor element with power. A capacitor is used as the energy storage device, and the charging of the capacitor is monitored by a voltage monitoring device.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: February 13, 2007
    Assignee: Robert Bosch GmbH
    Inventors: Werner Nitschke, Klaus-Dieter Meier, Knut Balzer, Ewald Mauritz, Heiko Buehring, Hans Bogenrieder, Bernd Pfaffeneder, Holger Wulff
  • Patent number: 7176588
    Abstract: A starter drive device which drives a starter motor by, upon actuation of a starter switch, turning a starter relay ON and OFF via an electronic control device, wherein the electronic control device includes: an interface circuit; a power source control circuit; a calculation device and a delay circuit; a buffer; an addition circuit; a latch circuit; a first pull up circuit; a second pull up circuit; and wherein, if the power source control circuit has detected a drop of voltage of the power source when the starter motor is being driven, along with stopping the calculation device, the buffer disconnects the calculation device from the latch circuit, and controls the starter relay by operating the driver circuit via the latch circuit based upon the signals from the interface circuit and the second pull up circuit.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: February 13, 2007
    Assignees: Keihin Corporation, Honda Motor Co., Ltd.
    Inventors: Takuya Yahagi, Takashi Hisaki, Shuji Tomimatsu, Satoshi Arai, Shigeki Baba
  • Patent number: 7176589
    Abstract: An underwater cable arrangement includes systems and method for distributing and/or transferring power and/or data to internal devices and external devices disposed along an underwater cable. Under water coupling systems and underwater electrical devices may be used in the distribution and/or transfer of the power and/or data.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: February 13, 2007
    Assignee: Input/Output, Inc.
    Inventor: Robert E. Rouquette
  • Patent number: 7176590
    Abstract: A motor producing a rectilinear drive force can be simultaneously provided with a small size and a lightweight, high accuracy and a large drive force. In a spiral linear motor 1, a rotator 3 and stator 2 are both constituted having a spiral shape and, by joining together both spiral-shaped parts, a drive force is produced in the axial direction during rotation in a spiral shape. By affording the spiral linear motor a spiral shape, a large drive force can be obtained similarly to that of a reduction gear and a large drive force can be obtained by utilizing a large area that lies opposite in the axial direction of the rotator and stator.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: February 13, 2007
    Assignee: Yokohama TLO Company, Ltd.
    Inventor: Yasutaka Fujimoto
  • Patent number: 7176591
    Abstract: The invention relates to a system consisting of carbon brushed and circular pot-like carriers (10) having at least one electrical interconnection and surrounding a commutator of a motor, and a frame (18) that projects peripherally over the carrier and can be fixed into position between a motor housing and a transmission housing, proceeding from the peripheral surface of the carrier. In order to attain a simplification in the manufacture of carriers for different applications, it is proposed that the carrier be connected form and/or force-locking to one frame of several frames of different configurations via locking projections (22, 24) and locking recesses (25, 26).
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: February 13, 2007
    Assignee: K-TEC Kunststoffverarbeitung GmbH
    Inventor: Wolfgang Kasdorf
  • Patent number: 7176592
    Abstract: Disclosed is a stator structure of a rotary device and its forming method.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: February 13, 2007
    Assignee: Delta Electronics Inc.
    Inventors: Kuo-Cheng Lin, Shou Te Yu, Yao Lung Huang
  • Patent number: 7176593
    Abstract: An actuator coil with a race track winding that generates a magnetic field. A cooling tube has cooling liquid flowing therethrough and is wrapped around a periphery of the race track winding. A plurality of thermal conductive strips are arranged generally transverse to at least portions of the race track winding so as to conduct heat from the racetrack winding to the cooling tube.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: February 13, 2007
    Assignee: ASML Holding N.V.
    Inventor: Daniel N. Galburt
  • Patent number: 7176594
    Abstract: A motor that can prevent damages on the fluid dynamic bearing. A ball is press-fitted into the end surface of the shaft body, and the ball is disposed in such a manner that the tip portion of the ball comes to the higher position with respect to the end surface of the annular body. When the shaft is at rest, the ball abuts against the upper surface of the counter plate, and the end surface of the annular body is brought into a state of being raised from the upper surface of the counter plate, so that the situation in which the end surface of the annular body and the upper surface of the counter plate are brought into almost fully touch each other can be avoided. Therefore, when the operation is started, the circulation speed of a fluid increases and a fluid layer is quickly formed. As a consequent, the fluid circularity blocking action, which could be occurred in the relate art, is avoided, and generation of scratch caused by starting rotation in the tightly sticked state can be positively prevented.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: February 13, 2007
    Assignee: Minebea Co., Ltd.
    Inventors: Rikuro Obara, Akio Okamiya
  • Patent number: 7176595
    Abstract: A support device of a motor shaft includes a shaft, a shaft seat and a bearing. The shaft is joined to a fan blade set at an end thereof and provides a circular shape at another end thereof. The shaft seat has a circular recess corresponding to the circular end so as to join with the shaft. The bearing fits with the shaft to support the shaft during the shaft rotating and the shaft seat further has a hollow space at the center thereof to receive the shaft. Due to being attached to the shaft seat and supported, the shaft is capable of rotating steadily to overcome deficiency of swinging residing in the prior art.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: February 13, 2007
    Assignee: Asia Vital Component Co., Ltd.
    Inventor: Chu-Hsien Chou
  • Patent number: 7176596
    Abstract: The invention relates to a pivot joint structure of the motor rotor including a spindle and a snap ring. The spindle is centrally disposed in the rotor and the end thereof near the urging part has a scoop channel with smaller outer diameter. The urging part has at least one plane surface along the axial direction and the cross section is formed in a non-circular shape. The center hole of the snap ring takes the shape corresponding to that formed by the cross section(s) of the urging part and the gap therebetween provides a minimum space for the inserting in the urging part. Consequently, regardless of the assembly or disassembly of the rotor, the snap ring structure won't be affected and the deformation or fracture thereof won't take place.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: February 13, 2007
    Assignee: Sunonwealth Electric Machine Industry Co., Ltd.
    Inventors: Alex Hong, Wang Ko Chien
  • Patent number: 7176597
    Abstract: An electromagnetic retarder (1) for a vehicle includes a disc (20), a first rotor (5) and a second rotor (6), the disc being arranged to couple the first rotor and the second rotor to a transmission shaft of a vehicle. In order to facilitate fitting of this transmission shaft on the electromagnetic retarder, the invention provides for positioning the disc on one of the two rotors in such a way that the disc is placed in a position offset longitudinally, with respect to an axis (21) of the retarder, towards one of the two rotors. The disc includes fastening means for fastening the disc on the corresponding rotor, which fastening means (22) are such that they are positioned between curved arms (9, 10) of the rotor.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: February 13, 2007
    Assignee: Telma
    Inventor: Zeng Gang Liu
  • Patent number: 7176598
    Abstract: A bridge (8) in conformity with a tooth opening angle of the stator (1) is provided between a permanent magnet (5) and a permanent magnet (5) in a rotor (4), so that a magnetic flux for a reluctance torque is made to pass an inner side of the permanent magnet (5). An opening angle of each of ribs (7) on both sides of the permanent magnet (5) is set to be equal to or smaller than the teeth interval opening angle and equal to or larger than a half thereof. Thereby, reluctance of the rib (7) against a magnetic flux in a circumferential direction is increased and leakage of the magnetic flux of the permanent magnet (5) is prevented.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: February 13, 2007
    Assignee: Koyo Seiko Co., Ltd.
    Inventors: Sadaaki Mori, Hirohide Inayama, Atsushi Ishihara, Tomofumi Takahashi, Minoru Kitabayashi, Tetsuo Horie
  • Patent number: 7176599
    Abstract: A surface acoustic wave device includes: interdigital transducers; first electrode pads that are connected to the interdigital transducers through wire patterns; and a piezoelectric substrate on which the interdigital transducers, the first electrode pads, and the wire patterns, are formed. In this surface acoustic wave device, at least one of the first electrode pads is not connected to a ground pattern, and the piezoelectric substrate has a conductivity in the range of 10?12/?·cm to 10?6/?·cm.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: February 13, 2007
    Assignee: Fujitsu Media Devices Limited
    Inventors: Osamu Kawachi, Yoshiro Fujiwara
  • Patent number: 7176600
    Abstract: A circuit provides energy to a plurality of piezoelectric diaphragm structures formed in a two-dimensional array. Each piezoelectric diaphragm structure includes a piezoelectric element in operational contact with at least a first side electrode and a second side electrode. A switching system includes a first connection for a first power source, for application of power to the first side electrode and a second connection for a second power source, for application of power to the second side electrode. In a first state, power appropriate for performing a poling operation of the piezoelectric material is available for application to the first electrode, and the second electrode, and in a second state, power appropriate to activate the piezoelectric material to cause operational movement of the poled piezoelectric diaphragm structure is available for application to the first electrode and the second electrode.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: February 13, 2007
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Steven A. Buhler, John S. Fitch, Meng H. Lean, Karl A. Littau
  • Patent number: 7176601
    Abstract: A piezoelectric power generation system which performs a highly efficient power generation using a piezoelectric element without dependency on the direction of an externally driven vibration. The piezoelectric power generation system includes a vibrator having a beam in the form of a rod, and an impact element such as a steel ball. At one end of the beam is fixed the impact element, and at the other end of the beam, the beam is fixed to the base. The outer circumference of the impact element carries the cylinder shaped piezoelectric element. When the base vibrates due to an externally driven vibration, the vibrator vibrates in synchronization with the given vibration in the radial direction of the base to cause the impact element of the base to impact with the inner surface of the cylindrical piezoelectric element, forcing the piezoelectric element to deform and thereby generate electrical power.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: February 13, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Hidetoshi Tanaka, Norio Ohkubo
  • Patent number: 7176602
    Abstract: An apparatus and method for producing a substantially uniform bond line thickness by utilizing a crosshatch, grid pattern, or spacers of like patterns in a receptacle of a transducer housing. Certain embodiments include a housing configured to retain a transducer. The housing includes an annular wall and a receptacle adjacent to the wall. The receptacle has a member configured to allow radiation to pass through it. The member has a first surface and a second surface. The spacers on the first surface are configured in a grid pattern to maintain uniform spacing and a uniform bond line thickness between the transducer and the member. The bond line is further controlled by the depth of the spacers, which are configured to maintain a generally constant bond line thickness.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: February 13, 2007
    Assignee: SSI Technologies, Inc.
    Inventor: David T. Schlenke
  • Patent number: 7176604
    Abstract: A piezoelectric device includes a substrate, a buffer layer on the substrate, a lower electrode layer on the buffer layer, a piezoelectric layer on the lower electrode layer, and an upper electrode layer on the piezoelectric layer. The piezoelectric layer has a base portion extending outwardly at its lower portion of its periphery. The piezoelectric device provides enhanced bonding strength between the substrate and the stacked structure including the upper electrode layer, the lower electrode layer, and the piezoelectric layer.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masaya Nakatani
  • Patent number: 7176605
    Abstract: A plasma display device includes a plasma display panel. A chassis base is disposed substantially parallel to the plasma display panel, and a thermal conduction medium is interposed between and closely contacting the plasma display panel and the chassis base. The thermal conduction medium is a composite sheet having a thermal conductivity which is greater in a planar direction of the composite sheet than the thermal conductivity in a thickness direction of the composite sheet.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: February 13, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Sung-Won Bae, Joon-Hyeong Kim
  • Patent number: 7176606
    Abstract: A lamp includes a transparent envelope having a first region defining an enclosed interior volume and a closure region adjacent to the first region, a light source in the interior volume and electrically coupled through the closure region, an interference filter coating on the exterior of the first region, and a light absorbing coating that is 7–40 nanometers thick on the exterior of the first region, except in a ring-shaped portion adjacent to the closure region that has a thickness of 50–200 nanometers.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: February 13, 2007
    Assignees: Patent-Treuhand-Gesellschaft fur Elektrisch Gluhlampen mbH, Deposition Sciences Incorporated
    Inventors: Reinhard Schaefer, Robert Nichols, Florence Taitel
  • Patent number: 7176607
    Abstract: The present invention provides a light reflecting polymeric composition that includes at least one halogenated-flame-retardant-additive-free polymer having dispersed therein a pigment package including a combination of Sb2O3 and TiO2. The Sb2O3 and TiO2 preferably have an average particle size within the range of from about 0.05 ?m to about 1.0 ?m, and more preferably about 0.2 ?m. When used in combination, the Sb2O3 and TiO2 pigments synergistically interact together to provide a polymeric composition exhibiting a reflectivity that is substantially higher than can be obtained by the use of either of the pigments alone.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: February 13, 2007
    Assignee: Ferro Corporation
    Inventors: Deenadayalu Chundury, Richard Abrams, Ronald M. Harris, Mir Ali, Theophilus G. McGee, II, Susan T. Schmidt
  • Patent number: 7176608
    Abstract: A spark plug is disclosed as including a metal shell 10 formed with first and second bores 10c, 10d and a stepped section 10e between the first and second bores, and a porcelain insulator 20 having a largest-diameter section 20d, which is accommodated in the first bore and a small-diameter section 20e accommodated in the second bore. The first and second bores of the metal shell have a dimensional relationship, lying in a value equal to or less than 1.8 mm, which is expressed as (D1?D2)/2 where D1 represents an inner diameter of the first bore of the metal shell and D2 represents an inner diameter of the second bore of the metal shell.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: February 13, 2007
    Assignee: Denso Corporation
    Inventor: Keiji Kanao
  • Patent number: 7176609
    Abstract: An electron emitter has an emitter made of a dielectric material, and an upper electrode and a lower electrode to which a drive voltage is applied to emit electrons. The upper electrode is formed on a first surface of the substance serving as the emitter, and the lower electrode is formed on a second surface of the substance serving as the emitter. The upper electrode has a plurality of through regions through which the emitter is exposed. The upper electrode has a surface which faces the emitter in peripheral portions of the through regions and which is spaced from the emitter.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: February 13, 2007
    Assignee: NGK Insulators, Ltd.
    Inventors: Yukihisa Takeuchi, Tsutomu Nanataki, Iwao Ohwada, Takayoshi Akao