Patents Issued in February 13, 2007
  • Patent number: 7176710
    Abstract: The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: February 13, 2007
    Assignee: Altera Corporation
    Inventors: Mei Luo, Wilson Wong, Sergey Shumarayev
  • Patent number: 7176711
    Abstract: Disclosed is an on-die termination (‘ODT’) impedance calibration device. The ODT impedance calibration device comprises: a pulse generator for outputting a calibration signal of a pulse type for calibrating an ODT impedance; an M-bit counter for counting the number of pulses of the calibration signal; a first maximum counter trigger signal generator controlled by the M-bit counter; an N-bit counter for counting the number of pulses of the calibration signal; a second maximum counter trigger signal generator controlled by the N-bit counter; a delay unit for receiving a delay signal and outputting the delay signal after a predetermined period of time; an update trigger signal generator for outputting a pulse signal which is toggled according to an output signal of the delay unit; and an ODT impedance calibration unit for receiving the calibration signal and outputting a control signal for calibrating an ODT impedance.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: February 13, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Nak Kyu Park, Seong Ik Cho
  • Patent number: 7176712
    Abstract: A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately-preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: February 13, 2007
    Assignee: University of Southern California
    Inventors: Lars G. Svensson, William C. Athas
  • Patent number: 7176713
    Abstract: The present invention relates to electronic circuits that retain identical functionality and performance under RAM and hard-wire ROM fabrication options. An integrated circuit (IC) providing identical functionality and performance in two selectable fabrication options, wherein: a first selectable option comprises a user configurable circuit; and a second selectable option comprises a hard-wired circuit in lieu of said user configurable circuit. Such a programmable to hard-wire conversion provides a significant IC cost reduction at minimal NRE cost and improved reliability.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: February 13, 2007
    Assignee: Viciciv Technology
    Inventor: Raminda Udaya Madurawe
  • Patent number: 7176714
    Abstract: The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: February 13, 2007
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Brian D. Johnson
  • Patent number: 7176715
    Abstract: Disclosed is a device and method for configuring a register in a PLD to operate as a logical AND gate. So configuring a register allows it to be used in a multiplication carried out by the PLD. A logic element includes a combinatorial logic section and at least one register interconnected with the combinatorial logic section. The register is configured to operate as a logical AND gate. The logic element can include a data input, a clear input, and a load input wherein the load input can be held high, a first bit to be ANDed can be input on the data input and a second bit to be ANDed can be input on the clear input. The logic element can, for example be configured to carry out at least a portion of a multiplication of a multiplicand and a multiplier.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: February 13, 2007
    Assignee: Altera Corporation
    Inventor: Marcel LeBlanc
  • Patent number: 7176716
    Abstract: A multiple input look up table (LUT) structure adapted for carry-logic implementation, wherein each input is received in true and compliment levels, comprising: an output of an intermediate stage within the LUT structure; and a LUT value input of a stage next to said intermediate stage; and a multiplexer (MUX) structure coupled between the output and the LUT value input, wherein the MUX structure further comprises: a plurality of secondary inputs, including a carry-in logic signal; and a configuration circuit to couple one of the output or a said secondary input to said LUT value input.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: February 13, 2007
    Assignee: Viciciv Technology
    Inventor: Raminda Udaya Madurawe
  • Patent number: 7176717
    Abstract: A programmable logic structure is disclosed that has a set of dedicated lines which extend internally throughout different dedicated logic cells within a logic and routing block (LRB), extend from a previous logic routing block to the present logic and routing block, or extend from the present logic and routing block to the next logic and routing block. One set of dedicated lines from a first logic and routing block can be stitched to another set of dedicated lines of a second logic and routing block for extending the reach as well as bypassing a logic and routing block, or bypassing a dedicated logic cell in the same logic and routing block. The dedicated lines between logic and routing blocks allow a logic and routing block to receive more inputs from its own switch box or to drive more outputs than provided by the logic and routing block as specified by a given function.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: February 13, 2007
    Assignee: Velogix, Inc.
    Inventors: Ravi Sunkavalli, Hare K. Verma, Chandra Mulpuri, Elliott Delaye
  • Patent number: 7176718
    Abstract: A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: February 13, 2007
    Assignee: Altera Corporation
    Inventors: Michael D Hutton, Bruce Pedersen, Sinan Kaptanoglu, David Lewis, Tim Vanderhoek
  • Patent number: 7176719
    Abstract: A level restore circuit includes differential sides and a capacitive network having capacitors cross-coupled between the differential sides to provide a capacitively-coupled positive feedback between the differential sides. The level restore circuit further includes a reset network for resetting input and output nodes of one differential side to a first reset voltage and for resetting input and output nodes of the other differential side to a second reset voltage independent from the first reset voltage. The capacitive network reduces the effect of transistor mismatches and offsets in the level restore circuit. The level restore circuit is useful to generate output signals with a full logic levels based on input signals with a relatively low signal swing.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: February 13, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 7176720
    Abstract: Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: February 13, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Stephen M. Prather, Jeffrey F. Waldrip, Matthew S. Berzins, Charles A. Cornell
  • Patent number: 7176721
    Abstract: In a data-precessing receiver, a sampling circuit generates a plurality of samples of an incoming signal and stores the plurality of samples one after another in a first storage buffer. A first subset of the plurality of samples are transferred from the first storage buffer to a decoder circuit in response to each assertion of a first control signal, and a second subset of the plurality of samples are transferred from the first storage buffer to a tap weight update circuit in response to each assertion of a second control signal, the second strobe signal being asserted asynchronously with respect to the first control signal. The tap weight update circuit generates a plurality of updated tap weights based, at least in part, on the second subset of the plurality of samples.
    Type: Grant
    Filed: December 24, 2004
    Date of Patent: February 13, 2007
    Assignee: Rambus Inc.
    Inventors: Andrew Ho, Vladimir M. Stojanovic
  • Patent number: 7176722
    Abstract: A low-power, high-performance inverter circuit comprises first and second inverter circuit portions. The first portion comprises a first inverter, including a first pull-up element and a first pull-down element, for inverting an input signal, a first switching element connected between the first pull-down element and ground for switching the first inverter, and a first diode connected between the first pull-down element and ground in parallel with the first switching element. The second portion comprises a second inverter, including a second pull-up element and a second pull-down element, for inverting an input signal, a second switching element connected between the second pull-up element and a supply voltage terminal for switching the second inverter, and a second diode connected between the second pull-up element and the supply voltage terminal in parallel with the second switching element. An output of the first portion is connected to an input of the second portion.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: February 13, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Kye Park, Choon Sik Oh
  • Patent number: 7176723
    Abstract: In one embodiment, a voltage translator is configured to sense a change in a value of a supply voltage to the translator and responsively inhibit the translator from changing a state of the output of the translator.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: February 13, 2007
    Assignee: Semiconductor Components Industries LLC
    Inventor: Antonin Rozsypal
  • Patent number: 7176724
    Abstract: A very low voltage swing is used to achieve very high data rates (up to 4 Gbps double data rate) at very low power consumption. A differential signaling approach is used for noise rejection, and a constant current approach also is used to minimize switching noise.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: February 13, 2007
    Assignee: Northrop Grumman Corporation
    Inventor: Kenneth A. Delson
  • Patent number: 7176725
    Abstract: A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: February 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: James W. Dawson, Donald W. Plass, Kenneth J. Reyer
  • Patent number: 7176726
    Abstract: A loss-of-signal (LOS) detector includes a variable gain amplifier with an input receiving an input signal, a threshold comparator with a first input receiving a signal derived from an output of the variable gain amplifier, a second input receiving a reference level and an output providing a loss-of-signal indication signal. The variable gain amplifier has a gain control input receiving a gain control signal derived from the output of the threshold comparator and such that the gain of the variable gain amplifier is set to a lower value when the loss-of-signal indication signal is active, and set to a higher value when the loss-of-signal indication signal is not active. Accordingly, the LOS detector needs only one decision level for both of the LOS and NotLOS decisions, which is set in the linear range of the signal detector so that the hysteresis is reproduced precisely.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: February 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Andreas Bock
  • Patent number: 7176727
    Abstract: A synthesizer that has a phase detector 8 and a charge pump circuit 9 for injecting an electric charge, or pulling it out that corresponded to a frequency difference of an input, a low-pass filter 11 for converting this electric charge into a voltage, a voltage control oscillator (VCO) 13 for changing an output frequency for this input voltage, a divider 14 for dividing the frequency of the input, and a voltage holding circuit 10 for holding the input voltage for a plurality of output frequencies of the VCO. A holding voltage of the voltage holding circuit 10 is switched with a switch 12, and the frequency of an output clock signal 3 is switched.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: February 13, 2007
    Assignee: NEC Corporation
    Inventor: Hiroshi Kodama
  • Patent number: 7176728
    Abstract: A power driver circuit is provided including a low voltage source, a high voltage source, at least one input signal line, an output node, and circuitry adapted to connect the output node to the low voltage source when the input signal line is in a first state and to the high voltage source when said input signal line is in a second state.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: February 13, 2007
    Assignee: Saifun Semiconductors Ltd
    Inventor: Alexander Kushnarenko
  • Patent number: 7176729
    Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
  • Patent number: 7176730
    Abstract: The invention system adjusts a phase/frequency detecting device in a phase locked loop. The phase/frequency detecting device compares a target clock signal generated from the phase locked loop with a predetermined reference clock signal, and outputs a set of control signals to further control the target clock signal to synchronize with the reference clock signal. A reset module counts the set of control signals and outputs a set of reset signals when a predetermined reset condition is met. A switch module counts the set of reset signals and switches the phase/frequency detecting device between a normal mode and a glitch protection mode when a predetermined switch condition is met. When the phase/frequency detecting device is under the glitch protection mode, and the predetermined reset condition set by the reset module is met, the reset module outputs the set of reset signals and resets the phase/frequency detecting device.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: February 13, 2007
    Assignee: Mediatek Inc.
    Inventor: Chi-Ming Chang
  • Patent number: 7176731
    Abstract: The present invention provides for compensation of leakage charge in a PLL. A first plurality and second plurality of charge pumps has a source charge pump and a sink charge pump, and each charge pump has its own switch. A first node is coupled between at least one source charge pump and at least one sink charge pump. A second node coupled between at least one source charge pump and at least one sink charge pump. A PLL filter is coupled to the first node. A dummy filter is coupled to the second node. A first input of a differential mode sensor is coupled to the PLL filter. A second input of a differential mode sensor is coupled to the dummy filter. A first input of a common mode sensor is coupled to the dummy filter. A second input of a common mode sensor coupled to the PLL filter.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: February 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Franklin Manuel Baez, David William Boerstler, Eskinder Hailu, Kazuhiko Miki
  • Patent number: 7176732
    Abstract: A charge pump circuit and method for supplying power. The charge pump circuit includes a first circuit receiving at least one low voltage signal and generating an output voltage signal. The charge pump circuit also includes a second circuit receiving a clock signal and the output voltage signal. The second circuit sends a request signal based on a comparison of the output voltage signal with two reference voltage signals, where the two reference voltage signals are derived from two supply voltage signals having a substantially constant potential difference. The charge pump circuit further includes a high voltage generator receiving the request signal and sending the two supply voltage signals to the first circuit and the second circuit. The high voltage generator adjusts the voltage potentials of the two supply voltage signals such that the voltage potential of the output voltage signal falls between the voltage potentials of the two reference voltage signals.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: February 13, 2007
    Assignee: Interuniversitair Microelektronica Centrum (IMEC) vzw)
    Inventor: Manuel Innocent
  • Patent number: 7176733
    Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: February 13, 2007
    Assignee: Mosaid Technologies, Inc.
    Inventor: Dieter Haerle
  • Patent number: 7176734
    Abstract: A clock signal generation circuit includes a Delay Locked Loop (DLL) that, responsive to an input clock signal and first and second feedback clock signals, generates a plurality of phased clock signals time-shifted with respect to one another. The clock signal generation circuit further includes a phase mixer that receives the plurality of phased clock signals, that phase mixes first and second groups of the plurality of phased clock signals to generate the respective first and second feedback signals, and that phase mixes the first and second feedback signals to generate an output clock signal. The phased plurality of clock signals may be separated by substantially uniform delays, the first group of clock signals may include signals delayed even numbers of delays with respect to the input clock signal, and the second group of clock signals may include signals delayed odd numbers of delays with respect to the input clock signal.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kwang-il Park
  • Patent number: 7176735
    Abstract: In a wave-shaping circuit, a charging switching element in series with an inductor is switched, a capacitor is charged with a back electromotive force generated by the inductor, a discharging switching element in series with a discharge resistor is switched, and the charge in the capacitor is discharged. By controlling the timing at which the charging switching element and the discharging switching element are switched, the power supply voltage can be increased and it is possible to generate a charge voltage for which the slope of the envelope can be determined. As a result, an output voltage with a desired output voltage waveform can be obtained from the charge voltage. The wave-shaping circuit is a simple circuit that does not include a transformer is used to increase the voltage of a low-voltage power supply and to form an output voltage waveform from a DC waveform.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: February 13, 2007
    Assignee: SMK Corporation
    Inventor: Osamu Yoshikawa
  • Patent number: 7176736
    Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: February 13, 2007
    Assignee: Linear Technology Corporation
    Inventor: Karl Edwards
  • Patent number: 7176737
    Abstract: A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: February 13, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Michael P. Baker, Steven C. Meyers
  • Patent number: 7176738
    Abstract: A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset values(s), and combinations of such.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: February 13, 2007
    Assignee: Integrated Device Technology, Inc.
    Inventors: Frank Hwang, Howard Yang, Chuen-Der Lien, Jimmy Lee
  • Patent number: 7176739
    Abstract: A circuit comprising an active pull-up device coupled to a level shift circuit is coupled to a one-wire bus to allow communication devices coupled to the bus to better detect digital communication signals propagating through the bus. The level shift circuit provides a reference voltage signal that is typically above the circuit ground. Communication devices coupled to the bus are better able to detect digital communication signals propagating through the bus because such signals are raised above at least a portion of the noise signals on the bus.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: February 13, 2007
    Assignee: Lucent Technologies Inc.
    Inventors: James Michael Devine, Mark Elliot Kostbade, Stephen Thomas Spang
  • Patent number: 7176740
    Abstract: A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: February 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Suguru Tachibana, Tatsuo Kato
  • Patent number: 7176741
    Abstract: To a level shift basic circuit having a CMOS configuration and composed of four transistors M1 through M4, a control circuit for preventing feed-through current through the transistors is added. Transitions of complementary data inputs Vin1 and Vin2 are made in a period in which n-MOS transistors M7 and M8 for control are turned OFF by changing a control input VS1 to an L level (switch-off period). In this switch-off period, each source of the n-MOS transistors M1 and M2 is disconnected from VSS. In addition, in the switch-off period, a control input VS2 is changed to an L level, thereby turning ON p-MOS transistors M5 and M6 for control. In a period in which the control p-MOS transistors M5 and M6 are ON, data outputs Vout1 and Vout2 are both precharged to VDD (precharge period).
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomoya Ishikawa, Hirofumi Nakagawa
  • Patent number: 7176742
    Abstract: A bootstrapping circuit capable of sampling inputs beyond a supply voltage which includes a bootstrapped switch coupled between an input node and an output node, a first transistor having a first end coupled to a control node of the bootstrapped switch, a first capacitor having a first end coupled to a second end of the first transistor, a second transistor coupled between the first end of the first transistor and a supply node, and having a control node coupled to a first clock signal node, a third transistor coupled between the second end of the first transistor and the supply node, a charge pump having an output coupled to a control node of the third transistor, a level shifter having an output coupled to a second end of the first capacitor, a fourth transistor cross-coupled with, the first transistor, a fifth transistor having a second end coupled to the first end of the fourth transistor, and having a control node coupled to the output of the level shifter, and a sixth transistor coupled between the firs
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: February 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Devrim Y. Aksin, Mohammad A. Al-Shyoukh
  • Patent number: 7176743
    Abstract: A driver circuit that has a plurality of output elements that are switched on and off in staggered fashion by signals generated by first and second drive chains of a drive chain configuration. The first drive chain comprises “N” delay elements, each of which produces a time delay equal to tDELAY such that the total time delay produced by the first drive chain is equal to (N×tDELAY). The second drive chain comprises N+1 delay elements, “N” of which produce a time delay equal to tDELAY and one of which produces a time delay equal to ½(tDELAY). Therefore, the total time delay produced by the second drive chain is equal to ((N×tDELAY)+(½tDELAY)). The use of the delay element in the second drive that produces the time delay equal to ½(tDELAY) results in smooth transitions in the transition regions where the driver circuit output signal transitions from high to low and from low to high.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: February 13, 2007
    Assignee: Agere Systems Inc.
    Inventors: Robert H. Leonowich, Xiaohong Quan
  • Patent number: 7176744
    Abstract: A gate discharge resistor part is connected to the gate of an IGBT (Insulated Gate Bipolar Transistor). A timer circuit has its output connected to the input of the gate discharge resistor part and the input of a gate driving circuit. When an ON signal for driving the IGBT into an ON state stays input over a predetermined time period, the timer circuit outputs an H-level signal to the gate discharge resistor part and gate driving circuit. The gate driving circuit drives the IGBT into the OFF state based on the signal from the timer circuit. The gate discharge resistor part changes its resistance from a value given by a first resistor to a value given by a composite resistance of the first and second resistors.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: February 13, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shinsuke Goudo
  • Patent number: 7176745
    Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kiyoo Itoh, Hiroyuki Mizuno
  • Patent number: 7176746
    Abstract: A low power charge pump system having a plurality of charge pump cells. Each cell is a three transistor device that operates to transfer voltage from an input node to an output node of the cell when the input voltage is substantially greater than the output voltage and to block when the output voltage is substantially greater than the input voltage. Each cell has a pump capacitor is connected between a clock and its output, the odd-numbered cells having a first clock connected to their pump capacitors and the even-numbered cells having a second clock connected to their pump capacitors. During a first phase of either the first or second clock, the cell operates to transfer a voltage on its input node to its output node and during a second phase, the cell operates to boost its output voltage by a predetermined amount.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: February 13, 2007
    Assignee: PicoNetics, Inc.
    Inventors: Lei Wang, Jianbin Wu
  • Patent number: 7176747
    Abstract: A multi-level high voltage generator according to embodiments of the invention is capable of simultaneously generating high voltages of various levels by using one charge pump. The multi-level high voltage generator includes a charge pump unit, a voltage divider unit, and a pump control unit. The charge pump unit raises an input voltage applied at an input terminal to simultaneously output a number of high voltages having different levels. The voltage divider unit divides the voltages from the charge pump unit. The pump control unit operates according to an enable signal and generates pump control signals in response to a reference voltage, a control clock signal, and a divided voltage from the voltage divider unit. The charge pump unit generates the high voltages and is controlled by the pump control signals from the pump control unit.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: February 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Lee, Dae-Seok Byeon
  • Patent number: 7176748
    Abstract: A circuit for converting a direct current input voltage into an output voltage greater than the input voltage. The circuit includes a charge pump and a block for generating pulse signals of a predetermined frequency to be applied to a control input of the charge pump. The settling time, i.e. the time necessary for the output voltage to attain its operating value and to maintain it with a given precision, is reduced by providing the circuit with charge injection control via modulation of the duty cycle of the pulse signals as a function of the difference between the output voltage, or a predetermined fraction thereof, and a predetermined reference voltage and in such a manner as to reduce the settling time as the difference diminishes. The circuit includes a regulator that controls the charge pump based upon the predetermined reference voltage.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: February 13, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventors: Osama Khouri, Giancarlo Ragone
  • Patent number: 7176749
    Abstract: Ensuring sufficient bias current is provided to a portion of a circuit containing low voltage transistors operating with a high supply voltage. Such a sufficient bias current may be ensured by generating a primary bias current from a low supply voltage and a backup bias current from a high supply voltage, and providing the backup bias current as the bias current if the primary bias current is not present. The primary bias current may be provided as the bias current when the low supply voltage is available. Thus, the backup bias current is provided as bias current in case of undesirable supply sequencing.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: February 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Bhupendra Sharma, Sudheer Prasad, Sandeep K. Oswal
  • Patent number: 7176750
    Abstract: A fast power-on band-gap reference circuit includes a buffer, a first band-gap logic, and a second high drive band-gap logic. During power-on of the band-gap reference circuit, both the first band-gap logic and the second high drive band-gap logic are activated, in which the first band-gap logic charges an output of the first band-gap logic and the second high drive band-gap logic charges a capacitance associated with an output of the band-gap reference circuit. When the output of the first band-gap logic reaches a predetermined value, the second high drive band-gap logic is deactivated and the output of the first band-gap logic is couple to the output of the band-gap reference circuit through the buffer.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: February 13, 2007
    Assignee: Atmel Corporation
    Inventors: Giorgio Oddone, Stefano Sivero, Giorgio Bosisio, Andrea Bettini
  • Patent number: 7176751
    Abstract: A trimmable voltage reference uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Hari Giduturi, Kerry D. Tedrow
  • Patent number: 7176752
    Abstract: A plate voltage generation circuit comprises: first and second differential circuits (11a, 11b) supplied with a reference voltage (VREF) and an output voltage (VOUT), respectively; a push-pull output circuit (3), connected to the first and second differential circuits, for generating the output voltage; and first and second dead-band control circuits, connected to the first and second differential circuits, respectively, for changing the width of a dead band of the output voltage in accordance with a high level or a low level of dead-band control signals (Sa, Sb) externally supplied.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: February 13, 2007
    Assignees: Elpida Memory, Inc., Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.
    Inventors: Takeshi Hashimoto, Hiromitsu Kojima
  • Patent number: 7176753
    Abstract: A constant voltage outputting apparatus includes a differential amplifier circuit, an amplifier circuit, a current adjustment device and a stabilization circuit. The differential amplifier circuit performs a differential amplifying operation and outputs a differential amplified voltage. The amplifier circuit amplifies the differential amplified voltage output from the differential amplifier circuit. The current adjustment device adjusts a current characteristic of the amplifier circuit. The stabilization circuit stabilizes a state of the current adjustment device. A constant voltage outputting method is also described.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: February 13, 2007
    Assignee: Ricoh Company, Ltd.
    Inventors: Ippei Noda, Kohzoh Itoh
  • Patent number: 7176754
    Abstract: A control system for the characteristic parameters of an active filter includes: a system for the determination of the technological distribution of the components that provides the information related to said technological distribution of the components; an elaboration system for said information related to said technological distribution of the components; an active filter including at least two programmable passive circuital elements receiving said information related to said technological distribution of the components; said elaboration system, being aware of the topology for said active filter, comprises means for determining the value for said at least two programmable passive circuital elements; means for correcting the value for said at least two programmable passive circuital elements according to the value of the information related to said technological distribution of the components; means for determining the programming values for said at least two programmable passive circuital elements.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: February 13, 2007
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Andrea Baschirotto, Pietro Liguori, Vittorio Colonna, Gabriele Gandolfi
  • Patent number: 7176755
    Abstract: Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: February 13, 2007
    Assignee: Battelle Memorial Institute
    Inventor: Matthew S. Taubman
  • Patent number: 7176756
    Abstract: An inductor element containing circuit board of the present invention comprises a plurality of conductive layers, and a conductor having an inductor function (inductor conductor segment) in one or more of the conductive layers, wherein at least part of the inductor conductor segment is made thicker than other conductors disposed within the circuit board. The at least part of the inductor conductor segment extends through an insulating layer disposed between the conductive layers, or is embedded in the insulating layer, wherein the part of the inductor conductor segment has a thickness one-half or more the thickness of the insulating layer. A power amplifier module of the present invention comprises the multi-layer circuit board, a semiconductor amplifier fabricated in the multi-layer circuit board, and an impedance matching circuit coupled to the output of the semiconductor amplifier. The impedance matching circuit has a portion thereof formed of the inductor conductor segment.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: February 13, 2007
    Assignee: TDK Corporation
    Inventors: Toshiyuki Abe, Yoshihiro Suzuki, Masashi Katsumata
  • Patent number: 7176757
    Abstract: A multistage amplifying device for amplifying a desired signal comprise first to N-th amplifiers connected in cascade,wherein the k-th (k is 1 to N) amplifier includes a k-th amplification section; and a k-th feedback section which has a reactance component, changes a phase of a signal output from the k-th amplification section. When a phase difference between the desired signal output from the N-th amplifier and a third-order inter-modulation distortion(IM3) output from the (N?1)-th amplifier is referred to as a first phase, and a phase difference between the desired signal output from the N-th amplifier, and a combined IM3 obtained by combining a IM3 occurring in the N-th amplification section and a IM3 fed back from the N-th feedback section is referred to as a second phase, a difference between the first phase and the second phase is 120° or more and 180° or less.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshifumi Nakatani
  • Patent number: 7176758
    Abstract: A multi-stage output buffer is disclosed. The output buffer includes an emitter follower circuit coupled to a differential input that is configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof. An emitter coupled pair circuit is coupled to the output of the emitter follower circuit, and is configured to amplify the signal and further isolate an input circuit. The buffer further includes a base-grounded configuration transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer. The base-grounded transistor circuit reduces a load impedance at the output of the emitter coupled pair circuit, improves decoupling of the external load from an input circuit when coupled thereto, and increases the output power.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: February 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Hans-Martin Rein, Hao Li
  • Patent number: 7176759
    Abstract: A low noise differential amplifier has a pair of single ended common-gate or common-base circuits and cross coupling of an input of one of the pair to the gate or base of the other one of the pair. This cross-coupling puts the differential input voltage over the Gate-Source of the common-gate transistor (or Base-Emitter of the common base transistor). This means that the same input impedance and gain can be made with half the current compared to a basic common-gate topology. The cross-coupling means the noise generated by the positive side of the common-gate structure ends up partly on the negative output and vice versa, and so the Noise Figure can be less than 3 dB.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: February 13, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Dieter Joos, Marc Borremans