Abstract: A method and apparatus for enhancing the performance of residual prediction in a multi-layered video codec are provided. A residual prediction method includes calculating a first residual signal for a current layer block; calculating a second residual signal for a lower layer block corresponding to the current layer block; performing scaling by multiplying the second residual signal by a scaling factor; and calculating a difference between the first residual signal and the scaled second residual signal.

Abstract: An information processing device includes: a modified data generating unit for generating modified data obtained by modifying content configuration data; a fix-up table generating unit for generating a fix-up table in which transformation data serving as an object to be replaced with the modified data is registered; and a data recording unit for recording content including the modified data and the fix-up table in an information recording medium; wherein the modified data generating unit is configured so as to execute data modification processing with the configuration units of MPEG encoded data included in a TS packet making up content as data modification processing units.

Abstract: Provided is an image compression apparatus and method. The image compression apparatus compresses a captured image by performing discrete cosine transformation on image data of the captured image and includes a prediction unit, a quantization unit, and an encoding unit. The prediction unit generates a prediction value for predicting the size of a compressed image with respect to the captured image according to the amount of high-frequency components of a first direction of image data in a previous frame of the captured image and the amount of high-frequency components of a second direction of the image data in the previous frame. The quantization unit selects a predetermined quantization table according to the generated prediction value and quantizes the discrete cosine transformed image data using the selected quantization table. The encoding unit encodes the quantized image data.

Abstract: An image enhancement apparatus using motion estimation includes: a motion estimation unit estimating a degree of motion between an input image on which image enhancement is performed and a temporally successive image; and an enhancement unit applying the image enhancement to an area without motion in the input image while not applying the image enhancement to an area with motion in the input image on the basis of the motion degree. Accordingly, by performing image enhancement on an area without motion in an input image while not performing image enhancement on an area with motion in the input image, it is possible to prevent image noise from being generated in the area with motion.

Abstract: A hybrid intra-inter bi-predictive (or multi-predictive) coding mode allows both intraframe (intra) and interframe (inter) predictions to be combined together for hybrid-encoding a current macroblock or a subblock Bi-prediction may be used also in I-pictures, combining two intra predictions that use two different intra prediction directions. A video encoder processes data representing a two-dimensional video image which has been produced by a conventional commercially available video camera. The video encoder is adapted to select, for coding a current macroblock, between an intra encoding mode, an P-frame inter encoding mode, a B-frame bi-predictive inter mode, and a hybrid intra-inter bi-predictive encoding mode. A video decoder (800) receives and decodes a data stream that may contain a block/macroblock encoded in accordance with the hybrid intra-inter bi-predictive encoding mode.

Abstract: A motion vector search unit determines a unit area of a bidirectional prediction frame for each motion vector of a backward reference frame to pass through, and stores information on the unit area to be passed into a pass area number holding unit. A reference vector prediction unit consults the pass area number holding unit to acquire the motion vector of the backward reference frame that passes a target unit area of the bidirectional prediction frame from a motion vector holding unit, and determines a reference vector to be applied to this target unit area. The motion vector search unit applies the reference vector to the target unit area of the bidirectional prediction frame, determines a forward motion vector and a backward motion vector of the target unit area by linear prediction, and makes a motion compensated prediction on the target unit area bidirectionally to generate a predicted image.

Abstract: A method for encoding video signals subjects the signals to unbalanced multiple description coding. The unbalanced multiple description coding codes a video signal in a first high resolution packet and a second low resolution packet and represents, respectively a first high resolution description and a second low resolution description. The unbalanced multiple description coding step includes using different intra refresh periods for the first and second high resolution descriptions, with an intra refresh period for the second low resolution description shorter than the intra refresh period of the first high resolution description.

Abstract: Provided are a video prediction apparatus and method for a multi-format codec and a video encoding/decoding apparatus and method using the video prediction apparatus and method. The video prediction apparatus that generates a prediction block based on a motion vector and a reference frame according to a plurality of video compression formats includes an interpolation pre-processing unit and a common interpolation unit. The interpolation pre-processing unit receives video compression format information of a current block to be predicted, and extracts a block of a predetermined size to be used for interpolation from the reference frame and generates interpolation information using the motion vector. The common interpolation unit interpolates a pixel value of the extracted block or a previously interpolated pixel value in an interpolation direction according to the interpolation information to generate the prediction block.

Abstract: A motion vector estimation apparatus that can reduce an amount of calculation for video coding processing and thus achieve a higher bit rate and lower consumption power, while contributing to improvement in image quality and coding efficiency include: a reduced picture generation unit which generates a reduced current picture to be coded and a reduced reference picture; a region partition unit which partitions a reduced current picture to be coded into regions and generates reduced region images; a region motion vector estimation unit which estimates a region motion vector of a reduced region image; a confidence level calculation unit which calculates a confidence level of a region motion vector; and a block size narrowing-down unit which narrows down candidate block sizes so as to determine a block size to be used for coding a current block to be coded, based on a region motion vector and a confidence level of the region motion vector.

Abstract: A motion estimation method for enhancing a video compression speed, and a video encoder using the same are provided. The motion estimation method includes determining a global motion type of a previous frame from motion vectors of the previous frame, setting a search area for a specified motion block included in a current frame based on the global motion type, and searching for a motion vector within the set search area.

Abstract: A device for data compression includes a domain transformer unit, a classifying unit, a variable length encoder, a fixed length encoder and a memory unit. The domain transformer unit transforms time-domain data into frequency-domain data. The classifying unit determines an encoding type of the frequency-domain data based on occurrence probability of the frequency-domain data. The variable length encoder encodes first frequency-domain data that are determined to be encoded by variable length coding. The fixed length encoder encodes second frequency-domain data that are determined to be encoded by fixed length coding. The memory unit stores the encoded first and second frequency-domain data by relocating the encoded first and second frequency-domain data such that the encoded first frequency-domain data are placed adjacently and the encoded second frequency-domain data are placed adjacently. Therefore, the time for decoding the corresponding data may be reduced.

Abstract: A transpose buffer may store 8×8 and smaller sized blocks of video data. When the smaller sized blocks arrive, they can be reconfigured to fit within the available space within the buffer.

Abstract: An intraprediction encoding and decoding apparatus and method to improve compression efficiency are provided. A video encoding method includes dividing an input video of a predetermined size into at least two sub-planes, performing intraprediction encoding on at least one of the divided at least two sub-planes, and performing interprediction encoding on at least one of the remaining sub-planes by using the intraprediction encoded sub-plane as a reference sub-plane.

Abstract: A data stream encoder eliminates duplicate transmission units in a transmitted data stream in which the detected duplicate may not be the immediately preceding transmission unit. A data aggregator transmits a stream of data by identifying a frame interval, or timing interval, corresponding to the time to send a frame of data in the stream. Each of the frames includes a predetermined number of blocks. Configurations identify repetition patterns in the blocks of successive frames, thus looking backward a frame interval to identify a previous corresponding block in the preceding frame. The corresponding transmission block need not be the immediately preceding block or transmission unit. For certain types of data, successive frames exhibit the same or similar patterns in the blocks of data defining the frame. Therefore, the encoder identifies duplicate blocks in successive frames, and transmits only the blocks that differ from a counterpart block in the previous frame.

Abstract: A decoding arrangement for decoding pictures in an incoming video stream includes a noise generator for adding a dither signal containing random noise to the pictures after video decoding, to improve the subjective video quality. The noise generator adds noise to each pixel in an amount correlated to the luminance of at least a portion of the current picture.

Abstract: A method and apparatus for communicating compressed video information includes storing video information compressed based on a first compression method, such as a method with a high compression ratio, and transcoding the compressed video information to produce corresponding recompressed video information that is based on a second compression method, with a lower compression ratio such as standard JPEG compression or other suitable compression. The method and apparatus, if desired, may include sending the recompressed video information for a destination apparatus which may then suitably decompress the video information using a standard decompression technique. For example, storing the compressed image in a high compressed format, for example, in a piecewise basis may be done online while the camera, for example, is in use so that the image is properly captured and then, transcoding the compressed image to a different level of compression while the camera is offline.

Abstract: An image processing apparatus includes a plurality of decoders, each decoding a predetermined region of each frame forming coded stream and an output unit receiving pixel data obtained as a result of the decoding processing by the plurality of decoders and combining the pixel data into decoded image data to output it. One subject decoder supplies, among pixel data obtained as a result of the decoding processing by the subject decoder, pixel data necessary for a different decoder to the different decoder, and also obtains, among pixel data obtained as a result of the decoding processing by the different decoder, pixel data necessary for the subject decoder from the different decoder. The subject decoder performs the decoding processing by referring to the pixel data obtained as a result of the decoding processing by the subject decoder and the pixel data obtained from the different decoder.

Abstract: A plurality of bit streams are seamlessly spliced. Separate decoders decode each bit stream. A controller selects the decoded pictures according to a re-encoding range in the vicinity of a splicing point of the bit streams. Pictures presenting a reordering of the streams are excluded in the selection of the decoded pictures. An encoder re-encodes the pictures within the re-encoding range. When it is determined that crossover motion compensation exists between pictures of different streams, the controller changes the motion prediction direction of the problematic picture. The controller changes a motion prediction picture type of a picture which is improperly motion predicted with reference to another stream. A quantization characteristic or motion vectors for the new picture type are generated by the controller. The controller effects the encoding in accordance with a target amount of bits to prevent a breakdown of a buffer and a discontinuation of an amount of data occupancy thereof.

Abstract: A plurality of bit streams are seamlessly spliced. Separate decoders decode each bit stream. A controller selects the decoded pictures according to a re-encoding range in the vicinity of a splicing point of the bit streams. Pictures presenting a reordering of the streams are excluded in the selection of the decoded pictures. An encoder re-encodes the pictures within the re-encoding range. When it is determined that crossover motion compensation exists between pictures of different streams, the controller changes the motion prediction direction of the problematic picture. The controller changes a motion prediction picture type of a picture which is improperly motion predicted with reference to another stream. A quantization characteristic or motion vectors for the new picture type are generated by the controller. The controller effects the encoding in accordance with a target amount of bits to prevent a breakdown of a buffer and a discontinuation of an amount of data occupancy thereof.

Abstract: Self-clocked two-level differential signaling methods and apparatus assuring both clock synchronization and ease of recovery of transmitted data. In accordance with the method, the data is encoded differentially on a differential signal that changes polarity at the end of each bit time. This allows clock recovery at the receiver simply by detection of the polarity change. The data is encoded, bit by bit, as exceeding a predetermined magnitude for a bit of a given state and as not exceeding the predetermined magnitude for the opposite state. Consequently data recovery is by way of a simple signal magnitude detection during a bit time, such as by a detection of signal magnitude a predetermined time. The apparatus does not require a phase locked loop in the receiver, thereby saving power and time to obtain synchronization. The method is conducive to varying bit time or duration, thereby reducing the peaks in the EMI radiation.

Abstract: A line interface circuit with line side cancellation of a communication device is described herein. In one embodiment, a communication device includes a line interface circuit for interfacing a communication line. The line interface circuit includes a driver for driving multiple transmitting signals onto the communication line over multiple transmitting frequency bands. The line interface circuit further includes multiple transmitting filters each corresponding to one of the transmitting frequency bands. Other methods and apparatuses are also described.

Abstract: Methods and systems for communicating a signal through a multi carrier system session are disclosed. The carrier channel includes a plurality of subcarriers. A bit value for each subcarrier of the plurality of subcarriers is determined (202, 402) based on the signal to be communicated. The plurality of subcarriers is divided (204, 404) into a first set of subcarriers and a second set of subcarriers based on the bit value for each subcarrier of the plurality of subcarriers. The first set of subcarriers is turned off (206, 406). The second set of subcarriers is then modulated (208, 408).

Abstract: A method for generating a preamble of an Orthogonal Frequency Division Multiplexed (OFDM) data frame for a multiple input multiple output (MIMO) wireless communication includes determining at least one system condition preamble format parameter. When the system condition preamble format parameter satisfies a first preamble format parameter a preamble having a first preamble format is formed. When the system condition preamble format parameter satisfies a second preamble format parameter, a preamble having a second preamble format is formed. Further, when the system condition preamble format parameter satisfies a third preamble format parameter, a preamble having a third preamble format is formed. The first, second, and third preamble formats differ based upon their lengths, fields, and modulation formats of a high throughput signal field.

Abstract: Controllable delay circuitry is included in each channel of multi-channel, high-speed, serial transmitter and/or receiver circuitry to compensate for or to at least help compensate for possible skew (different signal propagation time) between the various channels. In systems employing CDR circuitry, the delay circuitry may be at least partly controlled by a signal derived from the CDR circuitry to make the amount of delay effected by the delay circuitry at least partly responsive to changes in data rate detected by the CDR circuitry.

Abstract: A single side band (SSB) modulator module using a carrier frequency includes: first and second Mach-Zender interferometers for modulating the carrier frequency and first and second signals into an SSB signal; and an arm, which is connected to both ends at which the first and second Mach-Zender interferometers are connected, splits the carrier frequency, and outputs a split portion to the first and second Mach-Zender interferometers.

Abstract: A reconfigurable receiver, a reconfigurable transmitter and a multimode receiver are disclosed, operating in accordance with a two-step channel selection. In the receiver, the first step provides for a coarse radio frequency (RF) channel selection, to downconvert a desired channel and an image channel of the desired channel to IF. The second step provides for a fine intermediate frequency (IF) channel selection to select either the desired channel or the image channel. In the transmitter, the first step provides for a fine channel selection and upconversion of a desired channel to either positive or negative IF. The second step is a coarse channel selection and upconversion of a desired channel to the RF. The receiver and transmitter can be used in a transceiver.

Abstract: An automatic gain control mechanism with high-frequency detection. During a predetermined period, the cumulative strength of the real part of a complex-valued input signal is compared with that of the imaginary part of the complex-valued input signal. The zero crossings in either the real part or imaginary part of the complex-valued input signal are selectively totaled contingent upon which part of the complex-valued signal possesses the larger cumulative strength. If the zero crossings total exceeds a predetermined threshold, the automatic gain control mechanism starts detecting a normal packet signal and activating gain control over the detected normal packet signal.

Abstract: A mechanism for frequency tracking and channel estimation in multi-carrier systems. First, two training symbols are pre-compensated for an effect of frequency offset. Then an average of the two pre-compensated symbols is calculated. Meanwhile, a correlation between the two pre-compensated second symbols is evaluated by performing a differential operation. By means of a tracking loop, a frequency tracking value is calculated from the correlation and a loop coefficient. After that, the average of the two pre-compensated symbols is further compensated with a fine frequency offset estimate derived from the frequency tracking value. Accordingly, a channel response is estimated by performing a Fourier transform on the compensated average.

Abstract: Provided are an apparatus and a method for compensating for an I/Q mismatch using a transmission signal in a wireless communication system. The apparatus includes a coupler, an FFT operator, and an I/Q mismatch estimator. The coupler couples the transmission signal and provides the coupled signal to a reception path, and the FFT operator performs FFT on the coupled transmission signal. The I/Q mismatch estimator estimates I/Q mismatch using a preamble of the FFT-performed transmission signal. The apparatus can compensate for I/Q mismatch in real-time. Since the FFT provided to a reception signal detection unit of a TDD OFDM receiver is used without the need for a separate algorithm for Fourier transform required during an I/Q mismatch estimation process of the conventional art, resources can be saved.

Abstract: There is provided an apparatus and method for isolating an in-phase component I and a quadrature component Q of a received IF signal and for filtering the received signal. The apparatus comprises a DDC for sampling the received signal at four times the frequency of the received signal, each sample having an order k and a filter for reducing noise outside a required bandwidth. The filter has n taps and comprises a first filter portion for receiving the samples where k is even and for outputting an in-phase component I of the received signal and a second filter portion for receiving the samples where k is odd and for outputting a quadrature component Q of the received signal. The first filter portion has x taps and the second filter portion has y taps and x+y=n.

Abstract: Pipelined digital processing circuitry for use with a particle size measurement system, such as that employed in automated hematology systems, measures the ‘center’ amplitude of a pulse produced by a particle or cell passing through a flow cell measurement aperture, such as the detection aperture of a Coulter Principle-based electronic particle analysis system. The circuitry of the invention processes successive pulse samples by means of a half-peak/half-width methodology that analyzes each pulse as its continuously sampled and temporarily stored in memory. Concurrent analysis of the data in memory during storage locates the pulse width at a prescribed percentage (e.g., 50%) of the peak amplitude of the pulse. This pulse width data is then processed to determine the pulse amplitude at the midpoint of the width of the pulse between its mid-peak values on rising edge and fall edge portions of the pulse.

Abstract: A method and apparatus for scaling demodulated symbols for fixed-point processing are disclosed. Received data are demodulated to generate symbols. The symbols are mapped to soft bits. A signal-to-interference ratio (SIR) is estimated on a current transmission. A scaling factor is then generated for retransmissions based on a ratio of the SIR of the current transmission to the SIR of the latest new transmission of the same process. The soft bits are scaled with the scaling factor and the scaled soft bits are decoded. The scaling allows for reduction of the retransmission buffer size.

Abstract: One embodiment is a system for processing a complex ambiguity function (CAF) comprising creating a CAF surface from incoming data and a model vector, wherein the CAF surface has at least one feature, processing for a peak value, establishing a sub-window about the peak, wherein the peak is within the sub-window, and flattening the peak.

Abstract: A circular Viterbi decoder is capable of improving a data decoding speed without being limited by a sampling speed of a sampling and holding circuit. An analog Viterbi decoder includes: a clock divider which generates a plurality of clock signals by dividing a clock frequency of an externally-input clock signal, a plurality of sampling and holding units which sample and hold input analog data according to the clock signals generated from the clock divider, and a multiplexer which sequentially and alternately outputs the analog data sampled and held by the sampling and holding units.

Abstract: A combined polarimetric and coherent processing receiver (2300) can include at least one antenna (730 and 740), at least one receiver front end (700 and 704), a multipath processor (702, 706, and 714), a polarimetric signal processor (708), and a coherent processor (712). The multipath processor can be a plurality of correlators (702 and 706) coupled to the receiver front end(s) and can process the desired signal arriving from multiple paths coupled to the receiver. The polarimetric signal processor which can include a plurality of adaptive polarimetric filters (710) can be coupled to the multipath processor and can polarimetrically filter signals that are distinguishable from the desired signal. The coherent processor can be coupled to the polarimetric signal processor and can coherently combine the polarimetric filtered signal. The coherent processor can include time varying complex coefficients (714) and a signal combiner (716).

Abstract: Provided is an AGC circuit which is hard to be influenced by the level of an input signal.

Abstract: A circuit for measuring an eye size generates first sampled data by sampling received data with recovered clock signals and generates second sampled data by sampling the received data with shifted clock signals, in which the recovered clock signals, having different phases, are recovered from the received data. The shifted clock signals are obtained by shifting each phase of at least one of recovered clock signals by respectively predetermined phases. The circuit generates error counts for calculating the eye size of the received data by comparing the first sampled data and the second sampled data and measures the eye size by obtaining a phase range where the error counts are equal to zero. Therefore, the circuit may measure the eye size without interference of frequency offsets and/or jitter of the received data.

Abstract: A method and apparatus are provided for automatic alignment of a notch filter in a receiver. The method comprises the steps of determining a frequency of an interfering signal, monitoring an energy in the interfering signal, tuning the notch filter based on an initial tune value, detecting an energy content in the radio signal after the tuning step, incrementally tuning the notch filter away from the initial tune value while monitoring the energy in the interfering signal, repeating the step of detecting and the step of incrementally tuning until the energy in the interfering signal is minimized, and storing a new tune value as the initial tune value. The notch filter is configured to filter the radio signal. The new tune value indicates a minimized energy in the interfering signal.

Abstract: A method for detecting occupation of an adjacent channel by a signal with the aid of a complex-valued bandpass signal having an information channel component and/or an adjacent channel component. In accordance with the invention, a) a real-valued bandpass signal is derived in that the complex-valued bandpass signal is filtered and the real component is produced from the filtered signal, b) the real-valued bandpass signal is transposed into a first baseband signal, c) the first baseband signal is filtered so that spectral components influenced by the information channel component are suppressed, and d) the first filtered signal is evaluated and a binary occupation signal is generated to indicate the occupation of the adjacent channel as a function of the evaluated first filtered signal. The invention further discloses a corresponding device for detecting occupation, as well as a transmitting/receiving device and an integrated circuit having such a device.

Abstract: A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.

Abstract: A data clock recovery system is provided. A phase detector is configured to sample an input data stream by way of a data clock and a second clock to generate a first signal indicating whether a data clock lags or leads a preferred phase of the data clock in relation to an input data stream. A phase controller is configured to process the first signal to shift a phase of the second clock toward a second preferred phase, and to shift a phase of the data clock toward the first preferred phase after the shifting of the phase of the second clock.

Abstract: An improved reception port for receiving packet data based on the IEEE 1394 standard. The reception port includes a synchronization FIFO memory for receiving reception data in accordance with a reception clock signal and synchronizing the reception data with an internal clock signal, a decoder for decoding the synchronized reception data, and a shaping FIFO memory for outputting the decoded reception data at a fixed timing.

Abstract: Disclosed is a clock and data recover circuit including N flip-flops (F/Fs) for sampling an input data signal using N-phase clocks, a phase comparison circuit for performing phase comparison based on outputs of the F/Fs, a filter or smoothing a result of the phase comparison and outputting an up/down signal, up/down counters, each for receiving an output of the filter and counting up or down a count value thereof, a phase shift circuit for adjustably controlling phases of the clocks for edge detection and the clocks for data sampling according to phase control signals from an up/down counter and an up/down counter, respectively, and an up/down control circuit for receiving a control signal for controlling maximum and minimum values of count values of the up/down counter, generating a signal for controlling counting up and down of the up/down counter based on the count value of the up/down counter, and supplying the generated signal to the up/down counter.

Abstract: A phase detector for detecting a phase difference between a first signal and a second signal is disclosed. The phase detector includes: a difference determining module, a phase leading/lagging determining module, and a phase determining module. The difference determining module is used for outputting a pulse having a period in which a logic level of the first signal is different from a logic level of the second signal. The phase leading/lagging determining module is used for outputting an detection signal to identify a phase leading/lagging relationship between the first signal and the second signal. The phase determining module is coupled to the difference determining module and the phase leading/lagging determining module for combining the pulse and the detection signal to output a result signal, wherein the result signal comprises difference and leading/lagging information between the first and the second signal.

Abstract: A frequency detecting circuit and method and a semiconductor apparatus including the frequency detecting circuit, in which the frequency detecting circuit includes an edge detecting circuit, a clock signal generating circuit, and a determination circuit. The edge detecting circuit detects an edge of an input clock signal. The clock signal generating circuit generates a selection clock signal, which is a periodic pulse signal, in response to the detected edge. The determination circuit generates a frequency detection signal based on the number of occurrences of the selection clock signal in a period of the clock signal. The semiconductor apparatus includes the above-described frequency detecting circuit and a processor resetting the semiconductor apparatus in response to the frequency detection signal. Since a frequency is detected every half period, that is every high/low level period, of the clock signal in a digital manner, the reliability and the accuracy of frequency detection is improved.

Abstract: The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and multiple phase detectors capable of determining the phase differences between the output signals and a reference clock. The PLL further includes a weighting device capable of weighting the phase differences and generating a control signal for the voltage controlled oscillator.

Abstract: A phase locked loop circuit and a phase locked loop control method in an optical disc reproducing system having a high ISI condition is capable of detecting a phase error and a frequency error of an input signal based on a pattern, such as a sync pattern, having a predetermined uniform distribution over an entire range.

Abstract: A bidirectional shift register includes a former stage multiplexer, a latter stage multiplexer, a former stage full-swing shift register, and a latter stage full-swing shift register, all of which have a plurality of registers all of the same type. The former and the latter stage multiplexers output signals according to a forward clock, a backward clock, a forward control signal, and a backward control signal. The former and the latter stage full-swing shift register store the signals output from the former and the latter stage full-swing shift registers respectively.

Abstract: A voice over Internet Protocol (VoIP) positioning center (VPC) is implemented in configuration with support from a text-to-voice module, emergency routing database, and VoIP switching points (VSPs) to allow a public safety access point (PSAP) or other emergency center to effectively communicate the nature of an emergency alert notification and the area of notification to the VoIP positioning center (VPC). The inventive VPC in turn determines which phones (including wireless and/or VoIP phones) are currently in the area for notification, and reliably and quickly issues the required warning to all affected wireless and VoIP phones.

Abstract: According to an embodiment on the present invention, a method for controlling a voice recorder is disclosed. The voice recorder is for recording a voice session between an origination device and a destination device. The method can be conveniently executed at a computing apparatus coupled to the origination device and to the voice recorder. The method comprises receiving at least one of a user identifier associated with a user of the origination device and a destination identifier associated with the destination device. The method further comprises generating a voice recording trigger using at least one of data associated with the user identifier and data associated with the destination identifier. The voice recording trigger is then transmitted to the voice recorder to enable the voice recorder to control recording of the voice session between the origination device and the destination device.