Abstract: A method and apparatus for testing and characterizing features formed on a substrate. In one embodiment, a test structure is provided that includes a test element having a first side and an opposing second side. A first set of one or more structures defining a first region having a first local density are disposed adjacent the first side of the test element. A second set of one or more structures defining a second region having a second local density are disposed adjacent the second side of the test element. A third set of one or more structures defining a third region having a first global density are disposed adjacent the first region. A fourth set of one or more structures defining a fourth region having a second global density are disposed adjacent the second region.

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

Abstract: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A channel material layer, a gate insulating layer and a second metal layer are formed over the substrate to cover the source/drain. The second metal layer, the gate insulating layer and the channel material layer are patterned to define a gate and a channel layer. A passivation layer is formed over the substrate to cover the gate. The passivation layer is patterned to expose a portion of the drain. A transparent conductive layer is formed over the substrate, and is electrically connected to the exposed drain. Thereafter, the transparent conductive layer is patterned to form a pixel electrode.

Abstract: Aspects of the invention can provide an electro-optical device that displays an image in good quality by an electro-optical device, such as a liquid crystal device, even in the proximity of edges of the image displayed. The electro-optical device can include a plurality of pixel electrodes, and wires and electronic elements that are used to drive the pixel electrodes, provided on a substrate. The plurality of pixel electrodes can be arranged in an image display area and a dummy area. The pixel electrodes disposed in the dummy area function as dummy pixel electrodes. Furthermore, on the substrate, dummy-pixel light-shielding films that cover at least part of opening regions of the dummy pixel electrodes are provided.

Abstract: A light-emitting device is provided. The device may include a thermally conductive region in contact with a wavelength-converting region (e.g., a phosphor region). The thermally conductive region may aid in the extraction of heat resulting from light absorption in the wavelength-converting region, which, if excessive, may impair device operation. The presence of a thermally conductive region can enable devices including wavelength-converting regions to operate even at high power levels (e.g., light generated by the light-generating region and/or by the light-emitting device having a total power greater than 0.5 Watts) for long operating lifetimes (e.g., greater than 2,000 hours).

Abstract: An optoelectronic module comprising at least one optical component placed on a support, said component comprising an active optical layer and at least one confinement layer which carries at least one electrical contact, wherein said module further comprises a thermal sensor comprising a temperature-dependent resistive material which extends over the confinement layer of the optical component, at the side of the electrical contact of said component.

Abstract: The present invention provides a submount that allows a semiconductor light-emitting element to be attached with a high bonding strength. A submount 3 is equipped with a substrate 3 and a solder layer 8 formed on a primary surface 4f of the substrate 4. The density of the solder layer 8 is at least 50% and no more than 99.9% of the theoretical density of the material used in the solder layer 8. The solder layer 8 contains at least one of the following list: gold-tin alloy; silver-tin alloy; and lead-tin alloy. The solder layer 8 before it is melted is formed on the substrate 4 and includes an Ag film 8b and an Sn film 8a formed on the Ag film 8b. The submount 3 further includes an Au film 6 formed between the substrate 4 and the solder layer 8.

Abstract: The optical semiconductor apparatus includes, on an n-GaAs substrate, a surface-emitting semiconductor laser device and a photodiode integrated on the periphery of the laser device with an isolation region interposed there between. The laser device is composed of an n-DBR mirror, an active region, and a p-DBR mirror and includes a columnar layered structure with its sidewall covered with an insulating film. The photodiode is formed on the substrate and has a circular layered structure wherein an i-GaAs layer and a p-GaAs layer surrounds the laser device with an isolating region interposed between the i-GaAs and p-GaAs layers and the laser device. The diameter of the photodiode is smaller than the diameter of the optical fiber core optically coupled with the optical semiconductor apparatus. Since the laser device and the photodiode are monolithically integrated, the devices do not require optical alignment, and thus, facilitate optical coupling with an optical fiber.

Abstract: A light emitting diode with high heat dissipation includes a substrate, a LED chip, a metal light reflection layer, a first lens, a holder, and a second lens. The substrate has an upper surface formed with a positive electrode and an opposite electrode, and a lower surface opposite to the upper surface. The LED chip is arranged on the upper surface of the substrate, and is electrically connected to the positive electrode and the opposite electrode by wires. The metal light reflection layer is located on the upper surface of the substrate for surrounding the LED chip, and reflecting the light emitted from the LED chip. The first lens is mounted on the metal light reflection layer for encapsulating the LED chip. The holder is mounted on the substrate to cover the first lens. And the second lens arranged on the holder.

Abstract: A radiation-emitting chip (2) with a radiation-transmissive window (5), which has a refractive index nF and has a main area (19), with a multilayer structure (9), which contains a radiation-active layer (10) and adjoins the main area (19) of the window (5), and with a radiation-transmissive medium surrounding the window (5) and having the refractive index n0, the window (5) having at least two boundary areas (6, 7), which form an angle ?, for which the relationship 90°??t<?<2?t where ?t=arc sin(n0/nF) is satisfied. A radiation-emitting component contains a chip (2) of this type.

Abstract: A light emitting device and electronic equipment having a long life at a low electric power consumption are provided. A hole transporting region composed of a hole transporting material, an electron transporting region composed of an electron transporting material, and a mixture region in which both the hole transporting material and the electron transporting material are mixed at a fixed ratio are formed within an organic compound film. Regions having a concentration gradient are formed between the mixture region and carrier transporting regions until the fixed ratio is achieved. In addition, by doping a light emitting material into the mixture region, functions of hole transportation, electron transportation, and light emission can be respectively expressed while all of the interfaces existing between layers of a conventional lamination structure are removed.

Abstract: In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are formed.

Abstract: A high-accuracy, threshold-voltage-settable, field-effect transistor and a semiconductor device including the field-effect transistor are provided. The field-effect transistor, having a channel layer through which carriers move between a source and a drain, includes a doped layer for adjusting the threshold voltage of the transistor by changing the carrier concentration in the channel layer. In particular, the doped layer is provided in a semiconductor substrate by implantation of impurities.

Abstract: A multilayer metal supply rings structure of an integrated circuit comprises at least two parallel perimetral metal rails defined in metal layers of different levels, geometrically superposed one to the other. Each rail is constituted by using definition juxtaposed modules, each module defining on a metal layer parallel segments, longitudinally separated by a separation cut, of each rail, superposed rails of said multilayer structure constituting one supply node being electrically interconnected through a plurality of interconnection vias through dielectric isolation layers between different metal levels. A feature of the multilayer metal supply rings structure is that the segments of each of said perimetral metal rails modularly defined on each metal level belong alternately to one and another supply node upon changing the metal level. A process of defining a multilayer metal supply rings structure is also disclosed.

Abstract: A rectifier device, based on a novel operation principle completely different from that of conventional molecular electronic devices, is made by coupling two or more molecules or molecule arrays (11) at certain joints. By making use of the phenomenon that transfer of an excited state or exciton from one molecule or molecule array to another molecule or molecule array coupled thereto progresses asymmetrically due to spatial asymmetry at the joint, a rectifying function related to the transfer of the excited state of exciton is obtained. Additionally, by controlling the rectification property in addition to the rectification function, an ion sensor device or a switching device is made. A resistor device may be inserted in the rectifier device.

Abstract: To arrange diffusion-inhibitory films 5a, 5b, and 5c for inhibiting the diffusion of a wiring material absent in a region on or above a light receiving unit 2, the diffusion-inhibitory films 5a, 5b, and 5c formed on a region above the light receiving unit 2 are selectively removed. Alternatively, the diffusion-inhibitory films are arranged only on top surfaces of wirings 4a, 4b, and 4c, and only a passivation film 12 and interlayer insulating films 3a, 3b, and 3c are arranged in the region on or above the light receiving unit 2. Thus, with less interface between different insulation films and less reflection of incident light in an incident region, the incident light 13 highly efficiently passes through these insulating films and comes into the light receiving unit 2. The light receiving unit 2 can thereby receive a sufficient quantity of the incident light 13.

Abstract: A device is provided having a first electrode, a second electrode, a first photoactive region having a characteristic absorption wavelength ?1 and a second photoactive region having a characteristic absorption wavelength ?2. The photoactive regions are disposed between the first and second electrodes, and further positioned on the same side of a reflective layer, such that the first photoactive region is closer to the reflective layer than the second photoactive region. The materials comprising the photoactive regions may be selected such that ?1 is at least about 10% different from ?2. The device may further comprise an exciton blocking layer disposed adjacent to and in direct contact with the organic acceptor material of each photoactive region, wherein the LUMO of each exciton blocking layer other than that closest to the cathode is not more than about 0.3 eV greater than the LUMO of the acceptor material.

Abstract: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current to generate spontaneous magnetization of a larger output current.

Abstract: A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

Abstract: A protection device and a method for manufacturing integrated circuit devices protect against plasma charge damage, and related charge damage during manufacture. The protection device comprises a dynamic threshold, NMOS/PMOS pair having their respective gate terminals coupled to the semiconductor bulk in which the channel regions are formed. With proper metal connection, the structure protects against plasma charge damage on the integrated circuit device during manufacture, and can also be operated to protect against abnormal voltages during operation of the circuit.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array region including a plurality of NAND cells, each NAND cell having a plurality of memory cell transistors, and which are arranged in series, and a plurality of select transistors. A trench-type isolation region is formed between columns in the array of the NAND columns. The trench-type isolation region is formed in self-alignment with end portions of the channel region and a floating gate of the memory cell transistor, formed in self-alignment with the end portion of a channel region of the select transistor, and has a recess formed in at least the upper surface between the floating gates of the memory cell transistors.

Abstract: A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The conductive spacers are patterned to form a plurality of floating gates. A plurality of buried doped regions is formed in the substrate under the bottom surface of the openings. An inter-gate dielectric layer is formed over the substrate. A plurality of control gates is formed over the substrate to fill the openings. The mask layer is removed to form a plurality of memory units. A plurality of source regions and drain regions are formed in the substrate beside the memory units.

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract: A method for fabricating a high-voltage MOS transistor. A first doping region with a first dosage is formed in a substrate. A gate structure is formed overlying the substrate and partially covers the first doping region. The substrate is ion implanted using the gate structure as a mask to simultaneously form a second doping region with a second dosage within the first doping region to serve as a drain region and form a third doping region with the second dosage in the substrate to serve as a source region. A channel region is formed in the substrate between the first and third doping regions when the high-voltage MOS transistor is turned on to pass current between the source and drain regions, where a resistance per unit length of the channel region is substantially equal to that of the first doping region. A high-voltage MOS transistor is also disclosed.

Abstract: An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.

Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

Abstract: A semiconductor apparatus where output and protection transistors are different in transistor structure, and where, even when breakdown in the output transistor occurs earlier than in the protection transistor, an ESD surge current does not concentrate in the output transistor inferior in ESD resistance. Formed in its output circuit, where the drain and source of a first-conductivity-type, e.g. NMOS, output transistor 11 are connected respectively to an output electrode and to ground, is an NMOS protection transistor 10 of which the drain and source are connected respectively to the drain and source of the NMOS output transistor 11 and of which the gate is directly connected to a second-conductivity-type layer, a P-well 22, under the gate electrode of the NMOS output transistor 11. By this means, an electrostatic surge does not concentrate in the NMOS output transistor 11.

Abstract: A semiconductor device in which a dielectric breakdown of a gate oxide in a MOS capacitor can be prevented and in which a circuit area can be reduced. The semiconductor device comprises an NMOS transistor a gate of which is connected to a terminal VDD on a high potential side and a PMOS transistor a gate of which is connected to a terminal GND on a low potential side, source/drain (S/D) regions of the NMOS transistor and source/drain (S/D) regions of the PMOS transistor being electrically connected.

Abstract: An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and the second-type FinFET are planar with each other. A first region of the BOX layer below the first FinFET fin is thicker above the substrate when compared to a second region of the BOX layer below the second FinFET fin. Also, the second FinFET fin is taller than the first FinFET fin. The height difference between the first fin and the second fin permits the first-type FinFET to have the same drive strength as the second-type FinFET.

Abstract: A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

Abstract: The invention relates to a method for the selective silicidation of contact areas that allow the production of highly integrated circuits, preferably in a SMOS or BiCMOS process. To this end, a metal oxide layer (14) that contains for example praseodymium oxide is deposited onto a prepared wafer (12). A silicon layer (16) and on top of said silicon layer a cover layer (18) is deposited onto the metal oxide layer (14), said cover layer being laterally structured. In a subsequent tempering step in an oxygen-free, reducing gas atmosphere the silicon layer (16) and the metal oxide layer (14) are converted to a metal silicide layer in lateral sections (20, 22) in which the cover layer (18) was previously removed.

Abstract: An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.

Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen

Abstract: An electromechanical microstructure including a first mechanical part formed in a first electrically conductive material, and which includes a zone deformable in an elastic manner having a thickness value and an exposed surface, and a first organic film having a thickness, present on all of the exposed surface of the deformable zone. The thickness of the first film is such that the elastic response of the deformable zone equipped with the first film does not change by more than 5% compared to the response of the bare deformable zone, or the thickness of the first film is less than ten times the thickness of the deformable zone.

Abstract: A memory element wherein a spin conduction layer having a sufficient spin coherence length and a uniform spin field can be obtained, and thereby practical use is attained and a memory device are provided. A spin conduction layer (paramagnetic layer) (24) is a fullerene thin film being from 0.5 nm to 5 ?m thick, for example. The fullerene has a hollow sized, for example, from 0.1 nm to 50 nm. A paramagnetic material is included in this hollow. A fermi vector of the fullerene thin film well laps over small number of spin band or plenty of spin band of a ferromagnetic fixed layer (23) and a ferromagnetic free layer (25). Further, spin orientations of the included paramagnetic material are random. Further, electron spin in the fullerene is in a quantized state in a pseudo zero dimensional space. Thereby, a spin coherence length becomes long in the fullerene thin film, and scatteration of spin-polarized conduction electrons goes away.

Abstract: An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

Abstract: Described are microlens designs to increase quantum efficiency and improve photonic performance of photosensitive integrated circuit device. A photosensitive integrated circuit made up of photodiodes, dielectric layers, metal contact holes, metal layers, and passivation stacks are formed on a semiconductor substrate. Microlenses are then formed over these encapsulating layers, the microlenses comprising non-planar surfaces, in particular a biconvex microlens formed above the photodiodes to direct, deliver, and focus incident light to the photodiodes for increased quantum efficiency and improved photonic performance. Color filters are then formed over the microlenses and the photodiodes so as to filter specific wavelengths of light.

Abstract: An optical semiconductor device package includes a disc-shaped stem, metallic leads in rod form penetrating the stem in the direction of the thickness to protrude from a main surface of the stem, and a mount extending vertically from the main surface of the stem, with a plane part of the mount facing the leads. A dielectric substrate is mounted on the plane part, and an optical semiconductor chip is mounted thereon. Two impedance-adjusting dielectric substrates which are rectangular in plan view are provided extending in parallel with the leads, to cover the plane part facing the leads.

Abstract: A method for encoding information that is encoded in spatial variations of the intensity of light (24) of a first wave-length into light of a second wavelength, the method comprising: generating a first density distribution of electrons homologous with the spatial variations in intensity of the first wavelength light; generating a second additional electron density homologous with the first electron density distribution; trapping electrons from the first and second electron density distributions in a trapping region (34) to generate an electric field homologous with the density distributions in a material (36) that modulates a characteristic of light (22) that passes therethrough responsive to an electric field (46) therein; and transmitting the second wavelength light (22) through the modulating material (36) thereby modulating the second wavelength light in response to the electric field and encoding it with the information.

Abstract: A MOS or CMOS sensor with a multi-layer photodiode layer covering an array of active pixel circuits. The multi-layer photodiode layer of each pixel is fabricated as continuous layers of charge generating material on top of the MOS and/or CMOS pixel circuits so that extremely small pixels are possible with almost 100 percent packing factors. The sensor includes special features to minimize or eliminate pixel to pixel crosstalk. A micro-lens array with a micro-lens positioned above each pixel directs light illuminating the pixel toward the central portion of the pixel and away from its edges. Also, preferably carbon is added to doped amorphous silicon N or P bottom layer of the multi-layer photodiode layer to increase the electrical resistivity in the bottom layer to further discourage crosstalk. In preferred embodiments each of the pixels define a tiny surface area equal to or larger than about 3.24 square microns and smaller than or equal to about 25 square microns.

Abstract: A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.

Abstract: A drain diffusion layer 11b includes a low impurity concentration region 5a and a high impurity concentration region 5b, and the low impurity concentration region 5a is located on the channel region side. An impurity layer 7 having an opposite conductivity type to the drain diffusion layer 11b is formed in the channel region, at a position away from the low impurity concentration region 5a by a distance T. Alternatively, the low impurity concentration region 5a and the impurity layer 7 are located so as to contact each other. Still alternatively, a border impurity layer is provided between the low impurity concentration region 5a and the impurity layer 7. Thus, a semiconductor device including a high voltage transistor capable of suppressing the reduction of the electric current driving capability and performing stable driving, and a method for fabricating the same, can be provided.

Abstract: A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.

Abstract: The object is the present invention is to provide a semiconductor device including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active in which the transistor is formed). By such composition, stress growing in the active due to the shallow trench isolation is equalized among the transistors and thereby the characteristics of the transistors can be equalized.

Abstract: The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film covering an inner surface of the isolation trench; forming a first silicon oxide film burying the isolation trench; etching and removing the first silicon oxide film in an upper region of the isolation trench; etching and removing the exposed second silicon nitride film; chemical-mechanical-polishing the second silicon oxide film; and etching and removing the exposed first silicon nitride film.

Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Abstract: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.

Abstract: A metal layer is formed directly on a nitride-based compound semiconductor base layer over a substrate body. The metal layer includes at least one metal exhibiting an atomic interaction, with assistance of a heat treatment, to atoms constituting the base layer to promote removal of constitutional atoms from the base layer, whereby pores penetrating the metal layer are formed, while many voids are formed in the nitride-based compound semiconductor base layer. An epitaxial growth of a nitride-based compound semiconductor crystal is made with an initial transient epitaxial growth, which fills the voids, and a subsequent main epitaxial growth over the porous metal layer.

Abstract: An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater.