Patents Issued in March 27, 2007
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Patent number: 7196501Abstract: A linear regulator having an input node receiving an unregulated voltage, an output node providing a regulated voltage, a voltage regulator, a bias circuit, and a current control device. The voltage regulator has an input terminal, a reference terminal, and an output terminal which forms the output node of the linear regulator circuit. The bias circuit has a first terminal coupled to the output terminal of the voltage regulator and a second terminal. The current control device has a first current electrode which forms the input node of the linear regulator circuit, a second current electrode coupled to the input of the voltage regulator, and a control electrode coupled to the second terminal of the bias circuit. The bias circuit develops a voltage sufficient to drive the control terminal of the current control device and to operate the voltage regulator.Type: GrantFiled: November 8, 2005Date of Patent: March 27, 2007Assignee: Intersil Americas Inc.Inventor: Richard A. Dunipace
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Patent number: 7196502Abstract: A switching regulator has a soft start circuit having a current source, a capacitor, and a MOS transistor connected between the current source and the capacitor for undergoing controlled operations between ON/OFF states to control a time period required for soft start of the switching regulator.Type: GrantFiled: November 29, 2004Date of Patent: March 27, 2007Assignee: Seiko Instruments Inc.Inventors: Masakazu Sugiura, Yoshikazu Kurusu
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Patent number: 7196503Abstract: A current averaging circuit for averaging a piecewise linear switching current waveform of a PWM power converter including first, second and third sample and hold circuits and a sample averaging circuit. The first sample and hold circuit samples a short duration of the current waveform for each PWM cycle and provides corresponding short samples. The second sample and hold circuit samples a long duration of each PWM cycle and provides corresponding long samples. The sample averaging circuit is coupled to the first and second sample and hold circuits, averages corresponding ones of the short and long samples and provides corresponding average values. The third sample and hold circuit samples each average value and provides a current average signal. The waveform may include ramp-on-a-step voltage pulses representing switching current. The current average signal is updated after each current pulse.Type: GrantFiled: March 23, 2005Date of Patent: March 27, 2007Assignee: Intersil Americas, Inc.Inventors: Grady M. Wood, Fred F. Greenfeld
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Patent number: 7196504Abstract: A constant-voltage circuit includes a first transistor, a first control circuit, and a second control circuit having a second transistor and a differential amplifier. The first transistor controls an output current according to a first control signal output by the first control circuit such that an output voltage is substantially equal to a predetermined voltage. The second control circuit has a response property faster than the first control circuit to a variation of the output voltage, and causes the first transistor to increase the output current for a predetermined time period, regardless of the first control signal, when the output voltage varied to an extent greater than a predetermined output voltage variation value. The second transistor controls an operation of the first transistor according to a second control signal output by the differential amplifier such that a voltage at an inverting input terminal is substantially equal to the bias voltage.Type: GrantFiled: January 17, 2006Date of Patent: March 27, 2007Assignee: Ricoh Company, Ltd.Inventor: Kohzoh Itoh
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Patent number: 7196505Abstract: An apparatus and method for regulating voltage levels. The apparatus includes a first transistor and a second transistor coupled to the first transistor. The first transistor is configured to receive a reference voltage, and the second transistor is configured to receive a feedback voltage and generate a first voltage. The first voltage is associated with a difference between the reference voltage and the feedback voltage. Additionally, the apparatus includes a third transistor coupled to the second transistor and configured to receive the first voltage from the second transistor and generate an output voltage in response to at least the first voltage. Moreover, the apparatus includes a fourth transistor coupled to the third transistor and configured to receive the output voltage from the third transistor and generate the feedback voltage, and a first current generation system coupled to the fourth transistor through at least a node.Type: GrantFiled: February 17, 2005Date of Patent: March 27, 2007Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Wenzhe Luo, Paul Ouyang
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Patent number: 7196506Abstract: Described herein is a surface-mounted integrated current sensor for use in a printed circuit having a track along which there flows, in use, the electric current to be measured. The current sensor comprises a package having a bottom face facing, in use, the printed circuit, and on which there is set an electrically conductive bottom piece, which, in use, makes contact with the track of the printed circuit in such a way as to be traversed by the current to be measured. The current sensor moreover comprises a sensor element, for example a Hall-effect one, designed to generate a voltage proportional to the electric current that flows through the bottom piece.Type: GrantFiled: February 14, 2006Date of Patent: March 27, 2007Assignee: C.R.F. Societa Consortile per AzioniInventors: Giuseppe Catona, Riccardo Groppo, Alberto Manzone
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Patent number: 7196507Abstract: An apparatus for testing substrates reduces the area required and the costs which arise with the testing of substrates, in particular semiconductor wafers, during the production process. The apparatus includes testing arrangements comprising a chuck, a chuck drive, control electronics, probe or probe board holding means with a handling system, a substrate magazine station and an alignment station. The testing arrangements include at least two testing arrangements, both of which are all jointly operatively connected to the handling system, the substrate magazine station and the alignment station.Type: GrantFiled: August 27, 2004Date of Patent: March 27, 2007Assignee: SUSS MicroTec Testsystems (GmbH)Inventors: Stefan Schneidewind, Claus Dietrich, Frank-Michael Werner, Don Feuerstein, Mike Lancaster, Denis Place
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Patent number: 7196508Abstract: A handler for testing semiconductor devices is disclosed which is capable of simplifying the process carried out in an exchanging station, namely, the process of loading/unloading semiconductor devices in/from test trays, and greatly increasing the number of simultaneously testable semiconductor devices.Type: GrantFiled: August 4, 2005Date of Patent: March 27, 2007Assignee: Mirae CorporationInventors: Chul Ho Ham, Ho Keun Song, Young Geun Park, Woo Young Lim, Jae Bong Seo
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Patent number: 7196509Abstract: A color contour of an object is displayed from information that is obtained using an array of thermopile sensors. A color contour of an object is generated by pre-establishing a relationship between IR radiation power and color, measuring the power of incident IR radiation emanating from different locations on the object, mapping the measured IR radiation powers to colors, and generating color contour information that can be displayed on a color display. The color contour information represents the temperature of an object at different locations.Type: GrantFiled: September 23, 2004Date of Patent: March 27, 2007Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.Inventor: Kong Leong Teng
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Patent number: 7196510Abstract: The invention provides an induction type displacement detector capable of achieving an improved resolution and high precision. The induction type displacement detector comprises a scale, and a sensor head movable along a measurement axis. A plurality of flux coupling windings are arranged on the scale along the measurement axis. A receiving winding is arranged on the sensor head, including receiving loops arrayed along the measurement axis.Type: GrantFiled: October 12, 2005Date of Patent: March 27, 2007Assignee: Mitutoyo CorporationInventor: Osamu Kawatoko
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Patent number: 7196511Abstract: A magnetic position detecting apparatus of the present invention includes a first magnetic resistance circuit and a second magnetic resistance circuit each having multiple magnetic resistance elements arranged to be opposite to a magnetized surface, wherein the first and the second magnetic resistance circuits are arranged in such a way that the resistance elements of the first and the second magnetic resistance circuits are connected to one another in series and arranged in a comblike shape to be parallel to one another along a current path of each magnetic resistance element, the magnetic resistance elements of the second magnetic resistance circuit are placed between the magnetic resistance elements of the first magnetic resistance circuit.Type: GrantFiled: April 22, 2005Date of Patent: March 27, 2007Assignee: Shicoh Engineering Co., Ltd.Inventors: Manabu Shiraki, Junichi Tada
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Patent number: 7196512Abstract: The magnetic head tester of the present invention drives a medium for rotation to float a slider from the medium so as to test a magnetic head for its characteristics, and the tester includes a holder removably holding the slider opposed to the surface of the medium, and suspension means provided in the holder which has the same function as a suspension supporting the slider in a real apparatus. With this tester, tests can be executed by exchanging the slider alone, and it is unnecessary to discard the suspension even when the magnetic head is judged to be defective, thus the loss of production costs for the suspension and processing costs for assembling the slider in the suspension can be avoided.Type: GrantFiled: November 26, 2003Date of Patent: March 27, 2007Assignee: Fujitsu LimitedInventors: Norio Kainuma, Hidehiko Kira, Kenji Kobae, Hiroshi Kobayashi, Katsutoshi Hirasawa, Takatoyo Yamakami, Masumi Katayama, Shinji Hiraoka
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Patent number: 7196513Abstract: A testing method for a magnetic hard disk or a magnetic head in a test system includes a moving step in which the magnetic head, which moves to fly closely over the magnetic disk, moves to a predetermined radial position corresponding to the position data of the magnetic disk which rotates at a predetermined constant speed; a reading step in which imbedded position data is read out for each sector of the magnetic disk is by the magnetic head; and a reading/writing step in which a predetermined signal is written in or read out from a data area of the sector by the magnetic head when the position data is one of equal to a predetermined value and within a predetermined range.Type: GrantFiled: July 31, 2006Date of Patent: March 27, 2007Assignee: International Manufacturing and Engineering Services Co., Ltd.Inventor: John Perez
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Patent number: 7196514Abstract: A magnetic field sensor relies on variations in permeability of magnetic material to detect an external field. An exemplary magnetic field sensor includes a lengthwise extending sensing element, and a coil wound about the sensing element. The sensing element may be formed as a number of geometrically and magnetically similar or identical conductive cores that are ferromagnetic, driven by an AC magnetic field. The multiple conductive cores are connected in parallel. An external magnetic field changes the magnetic characteristics of the sensing element and induces a change in electric potential of the induction coil. The sensor output is proportional to the number of conductive cores.Type: GrantFiled: October 20, 2004Date of Patent: March 27, 2007Assignee: National University of SingaporeInventor: Xiaoping Li
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Patent number: 7196515Abstract: The Hall switch arrangement comprises a plurality of Hall switch elements connected in series with a first Hall switch element, wherein the first Hall switch element is formed to provide a first output signal, which has information about a switching state of the first Hall switch element and with a second Hall switch element, wherein the second Hall switch element is formed to receive the first output signal of the first Hall switch element and to provide a further output signal having information about the switching state of the first Hall switch element and further information about the switching state of the second Hall switch element.Type: GrantFiled: May 19, 2005Date of Patent: March 27, 2007Assignee: Infineon Technologies AGInventor: Werner Roessler
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Patent number: 7196516Abstract: NMR spin echo signals are corrected for axial motion of the borehole logging tool. An additional correction may be applied to correct for incomplete polarization of nuclear spins due to an insufficient wait time between pulse sequences.Type: GrantFiled: August 16, 2004Date of Patent: March 27, 2007Assignee: Baker Hughes IncorporatedInventors: Martin Blanz, Holger Thern, Thomas Kruspe
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Patent number: 7196517Abstract: A method for evaluating formation fluids includes measuring a nuclear magnetic resonance property related to a total volume of the formation fluids, measuring a dielectric property related to an electromagnetic wave travel time, measuring a bulk density, and solving a set of linear response equations representing a reservoir fluid model to determine fractional fluid volumes from the nuclear magnetic resonance property, the dielectric property, and the bulk density.Type: GrantFiled: March 30, 2006Date of Patent: March 27, 2007Assignee: Schlumberger Technology CorporationInventor: Robert Freedman
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Patent number: 7196518Abstract: A magnetic resonance imaging method for fully automatically forming a water/fat separated image by calculation after acquiring data on images of different echo times, wherein the unwrapping of a phase map showing the distribution of the phase rotation due to the inhomogeneous static magnetic field is repeated so as to determine the distribution of the inhomogeneous static magnetic field by using an index used for judging whether or not the unwrapping is properly being performed, and wherein during the formation of a water/fat separated image with correction of the static magnetic field, the unwrapping is automatically and properly performed in correcting the static magnetic field, and the water/fat images are automatically discriminated.Type: GrantFiled: August 13, 2001Date of Patent: March 27, 2007Assignee: Hitachi Medical CorporationInventors: Yumiko Yatsui, Tetsuhiko Takahashi
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Patent number: 7196519Abstract: Apparatus and method for magnetic resonance imaging. In an aspect, the present invention is an apparatus for magnetic resonance imaging that includes a short bore magnet that is oriented such that, when energized, a static magnetic field is created in a substantially vertical direction. In another aspect, the present invention is a method for performing magnetic resonance imaging using a short bore magnet that is oriented such that, when energized, a static magnetic field is created in a substantially vertical direction.Type: GrantFiled: November 30, 2004Date of Patent: March 27, 2007Assignee: Fonar CorporationInventor: Raymond V. Damadian
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Patent number: 7196520Abstract: An apparatus and method for shimming a magnetic field of a magnet in a volume of interest includes a nonmagnetic holder configured with an array of fluid containing pockets; and a solidified ferromagnetic fluid in each pocket of the array of fluid containing pockets, wherein the solidified ferromagnetic fluid is fabricated from a ferromagnetic fluid, a diluting liquid, a hardener, and an accelerator agent. The ferromagnetic fluid includes a carrier liquid, ferromagnetic particles, and a surfactant.Type: GrantFiled: October 22, 2004Date of Patent: March 27, 2007Assignee: General Electric CompanyInventors: Weijun Shen, Minfeng Xu, Bu-Xin Xu
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Patent number: 7196521Abstract: A material having a permanent external diametrical electric field is included within an NMR MAS spinner. Such materials include ferroelectret porous films, in which the electric polarization arises from opposite mono-polar charges on separated surfaces within a structured material containing voids. Rotation of electrically polarized material produces a time-dependent electric field, modulated at the rotational frequency, so that a simple antenna achieves high sensitivity and phase stability in spin rate detection. The electrically polarized material is also of sufficiently high resistivity that modulation of the external NMR polarizing magnetic field B0 is negligible.Type: GrantFiled: March 15, 2006Date of Patent: March 27, 2007Assignee: Doty Scientific, Inc.Inventor: F David Doty
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Patent number: 7196522Abstract: A power circuit of a coil, includes two power or transmission line segments that are each connected to one of two ends of this coil, the line segments forming with the coil an oscillating circuit exhibiting a determined resonance frequency. The circuit has two line segments each including at least two conductors, of which one is connected to coil, and between them exhibit identical structures and identical lengths of connected conductors, whereby this common length is essentially a multiple of half of the resonance wavelength of the oscillating circuit. The conductors which are connected to coil at one of their ends are connected to one another at their other end by an adjustable symmetrical tuning component that completes this oscillating circuit, which with symmetrical structure is powered by a primary power circuit.Type: GrantFiled: June 20, 2005Date of Patent: March 27, 2007Assignee: Bruker Biospin SA (Societe Anonyme)Inventors: Michel Weiss, Laurent Martinache, Olivier Gonella
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Patent number: 7196523Abstract: A circuit for monitoring charge/discharge of a battery is disclosed. The circuit may comprise first and second terminal capacitors disposed for first and second terminals of a current detection resistor connected to a battery. The first and second terminal capacitors may develop an integrated voltage responsive to the charge/discharge current obtained from the individual terminals. The circuit may also include at least one comparator for comparing the individual integrated voltages developed by the first and second terminal capacitors with a reference voltage, the comparator having respective outputs which change when the individual integrated voltages reach the reference voltage. A terminal-by-terminal output change count difference output unit may count the number of times the output of the comparator changes and may output the difference between the number of times of change corresponding to the first terminal and the number of times of change corresponding to the second terminal.Type: GrantFiled: April 23, 2004Date of Patent: March 27, 2007Assignee: Sanyo Electric Co., LtdInventor: Susumu Yamada
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Patent number: 7196524Abstract: For simplified supply of potentiometric sensors with a reference electrolyte, a sensor plug head for connecting to a cable connection piece of a potentiometric sensor is provided. The sensor plug head including, besides the usual electric connections, a supply connection for connecting to a reference container of the potentiometric sensor. The supply connection includes, preferably, an electrolyte line and the reference container an opening, with the electrolyte line being connectable to the opening, in order to supply the reference container with electrolyte.Type: GrantFiled: November 26, 2003Date of Patent: March 27, 2007Assignee: Endress + Hauser Conducta Gesellschaft fur Mess-u. Regeltechnik mbH + Co. KGInventors: Detlev Wittmer, Wolfgang Babel
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Patent number: 7196525Abstract: Systems and methods of generating ions at atmospheric pressure are presented. These systems and methods include spatially dependent analysis of a sample using an effusive ionization source. Systems and methods of isolating samples at atmospheric pressure are presented. These systems and methods include using a barrier to prevent metastables or electrons from an effusive ion source from reaching a sample unless the sample is in an analysis position. Systems and methods of using metastables in collisionally induced dissociation are presented.Type: GrantFiled: May 6, 2006Date of Patent: March 27, 2007Inventors: O. David Sparkman, Steven M. Colby
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Patent number: 7196526Abstract: A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.Type: GrantFiled: August 18, 2005Date of Patent: March 27, 2007Assignee: The Regents of the University of Colorado, A Body CorporateInventors: Michael Vincent, Dragan Maksimovic
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Patent number: 7196527Abstract: A position transducer for a rotary member such as the rotor of a motor has a rotating encoder disc and flat, disc-shaped elements interacting with the encoder disc to produce position dependent signals. The encoder disc has at least one active element such as metal surfaces configured so that signals from one of several portions or sectors of the encoder system are not transferred to another portion or sector, thus permitting the position transducer to be split into several position detectors that can operate independently of each other without having signals from one position detector affecting the other position detectors. The position detectors can cover individual circular sectors or concentric rings and e.g. be based on sensing the capacitive coupling between transmitter and sensor electrodes located on opposite sides of the encoder disc.Type: GrantFiled: February 17, 2005Date of Patent: March 27, 2007Assignee: Stridsberg Innovation ABInventor: Lennart Stridsberg
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Patent number: 7196528Abstract: An electrostatic capacitance detection device including an electrostatic capacitance detection element arranged in a matrix form; a row line arranged in each row for selecting a relevant electrostatic capacitance detection element arranged in a relevant row; an output line arranged in each column for outputting a signal from a relevant electrostatic capacitance detection element arranged in a relevant column, wherein each electrostatic capacitance detection element is provided with a row selection element that controls the outputting of the signal of the relevant electrostatic capacitance detection element to the relevant output line based on the signal from the relevant row, and the signal from the relevant electrostatic capacitance detection element, which is caused to be in a selection state based on the signal from the relevant row line, is outputted to the output line arranged in the relevant electrostatic capacitance detection element.Type: GrantFiled: August 30, 2005Date of Patent: March 27, 2007Assignee: Seiko Epson CorporationInventor: Hiroaki Ebihara
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Patent number: 7196529Abstract: A system or method of analyzing a conductive member for the presence an anomaly. A test source signal is applied to a first test location on the elongate conductive member remote from the corrosion to cause the test source signal to travel along the pipe through the anomaly. At least one test return signal caused by the test source signal traveling through the anomaly is detected. The at least one test return signal for characteristics associated with the anomaly. Optionally, a perturbation may be applied to the elongate conductive member to place the conductive member in a perturbed state in which the electromagnetic characteristics of the conductive member at the anomaly are altered. The test source signal is applied to the first test location when the conductive member is in the perturbed stated.Type: GrantFiled: November 25, 2005Date of Patent: March 27, 2007Assignee: Profile Technologies, Inc.Inventors: Gale Burnett, Charles A. Frost
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Patent number: 7196530Abstract: A contactor used for testing a semiconductor device is provided. The semiconductor device testing contactor is electrically connected to electrodes of a semiconductor device to be tested. Such a contactor includes a wiring board and a first reinforcing member for reinforcing the wiring board. The contactor has a flexible base film and device connecting pads to be electrically connected to the electrodes of the semiconductor device. The first reinforcing member is disposed on the surface opposite to the semiconductor device connecting surface of the wiring board. The wiring board and the first reinforcing member are collectively bonded.Type: GrantFiled: September 26, 2003Date of Patent: March 27, 2007Assignee: Fujitsu LimitedInventors: Makoto Haseyama, Shigeyuki Maruyama
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Patent number: 7196531Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.Type: GrantFiled: March 4, 2005Date of Patent: March 27, 2007Assignee: FormFactor, Inc.Inventors: Gary W. Grube, Igor Y. Khandros, Benjamin N. Eldridge, Gaetan L. Mathieu, Poya Lotfizadeh, Jim Chih-Chiang Tseng
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Patent number: 7196532Abstract: An embodiment may comprise a test probe to measure electrical properties of a semiconductor package having ball-shaped terminals. The probe may include a signal tip and a ground tip. The signal tip may have a spherical lower surface allowing good contact with a ball-shaped signal terminal. The ground tip may be extended from a lower end of a ground barrel that encloses the signal tip. The ground tip may move independent of the signal tip by means of a barrel stopper and a spring. Thus, the probe can be used regardless of the size of and the distance between the package terminals.Type: GrantFiled: June 6, 2005Date of Patent: March 27, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Sun-Won Kang
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Patent number: 7196533Abstract: A control system and method of a semiconductor inspection system are disclosed, wherein the inspection can be conducted without reducing the reliability of measurement even in the case where the supply voltage drops. The control system has a controller, a power supply for a power on-off circuit constituting a switching regulator designed to maintain the output voltage against a supply voltage drop, and a supply voltage drop detector. In the case where a supply voltage drop is detected during the measurement, the measurement is automatically suspended, and after restoring the supply voltage, the measurement is automatically restarted.Type: GrantFiled: February 23, 2005Date of Patent: March 27, 2007Assignee: Hitachi High-Technologies CorporationInventors: Kouichi Yamamoto, Shinobu Otsuka
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Patent number: 7196534Abstract: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator 20 which obtains clocks input from a DUT 1 by a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolator 20 which obtains output data input from the DUT 1 by a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selector 30 which switches the time-sequential level data obtained by the time interpolators 20 and selectively outputs level data indicating rising and/or falling edges of the level data.Type: GrantFiled: December 18, 2003Date of Patent: March 27, 2007Assignee: Advantest Corp.Inventor: Hideyuki Oshima
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Patent number: 7196535Abstract: A method includes setting a first target temperature for an object that is in contact with a thermal medium, repeatedly receiving input that is indicative of a current temperature of the thermal medium, repeatedly estimating the temperature of the object based on the input, repeatedly setting a second target temperature for the thermal medium based on the estimated temperature of the object, and controlling the temperature of the thermal medium based on the second target temperature which has been set. Other embodiments are described and claimed.Type: GrantFiled: April 26, 2004Date of Patent: March 27, 2007Assignee: Intel CorporationInventor: C. Walter Fenk
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Patent number: 7196536Abstract: Methods and apparatus for non-contact electrical probes are described. In accordance with the invention, non-contact electrical probes use negative or positive corona discharge. Non-contact electrical probes are suited for testing of OLED flat panel displays.Type: GrantFiled: August 2, 2004Date of Patent: March 27, 2007Assignee: Agilent Technologies, Inc.Inventors: Michael J. Nystrom, Gloria E. Hofler
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Patent number: 7196537Abstract: An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.Type: GrantFiled: March 30, 2005Date of Patent: March 27, 2007Assignee: Infineon Technologies AGInventors: Aurel von Campenhausen, Joerg Vollrath, Ralf Schneider, Marcin Gnat
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Patent number: 7196539Abstract: An input signal is transmitted from a first device to a second device. At the second device the input signal method is received, and an output signal is generated in response to the input signal. The output signal is sensed, and the input signal is dynamically terminated in response to sensing the output data. In some embodiments, the receiving, generating and dynamically terminating occur within a single integrated circuit. In some embodiments, the method includes detecting a signal voltage level of the input signal and causing a termination voltage level to change from a first voltage level to a second voltage level in response to the signal voltage level.Type: GrantFiled: March 12, 2004Date of Patent: March 27, 2007Assignee: Rambus Inc.Inventors: Suresh Rajan, Scott Best
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Patent number: 7196540Abstract: A semiconductor device is easy for high accuracy impedance matching against differences in impedance of a transmission line and a package wire. A semiconductor chip having external output buffers and a packaging circuit are included. Each external output buffer has a first output portion whose internal impedance is adjusted commonly with other external output buffers in accordance with impedance control data and a second output portion whose internal impedance is adjusted independently of other external output buffers. Both of the first and second output portions are connected in parallel to a common output terminal. Common adjustment by the first output portion can cope with impedance of the transmission line and individual adjustment by the second output portion can cope with a difference of package wires.Type: GrantFiled: November 9, 2004Date of Patent: March 27, 2007Assignee: Renesas Technology Corp.Inventor: Hiroki Ueno
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Patent number: 7196541Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain.Type: GrantFiled: February 12, 2004Date of Patent: March 27, 2007Assignee: Koninklijke Philips Electronics N.V.Inventor: Katarzyna Nowak-Leijten
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Techniques for providing increased flexibility to input/output banks with respect to supply voltages
Patent number: 7196542Abstract: Techniques are provided for increasing flexibility to I/O banks with respect to supply voltages. Multiple supply voltages can be provided to a bank of I/O pins. Separate I/O pins residing in an I/O bank are driven by buffers that are coupled to different supply voltages. Dedicated I/O pins are driven by buffers with pre-selected supply voltages. The dedicated I/O pins can be grouped together into the same I/O bank providing greater flexibility to drive signals on I/O pins in other I/O banks at different voltages. Also, a dual mode input buffer can drive an input signal to a voltage determined by one of two possible supply voltage levels. In addition, power on reset circuits for an I/O bank can monitor the voltage of two or more supply voltages.Type: GrantFiled: October 28, 2004Date of Patent: March 27, 2007Assignee: Altera CorporationInventors: Andy Lee, Toan Nguyen, Stephanie Tran, Cameron McClintock, Brian Johnson -
Patent number: 7196543Abstract: A programmable input structure for a programmable logic circuit provides the capability of “fanning out” a selected signal to two or more input terminals of the programmable logic circuit, thereby increasing the routability of the logic block input signals. A logic block for an integrated circuit includes a programmable logic circuit and input multiplexers programmably selecting an input signal to provide to the programmable logic circuit. Also included in the integrated circuit are fan multiplexers that do not drive the programmable logic circuit directly. Instead, the fan multiplexers drive two or more of the input multiplexers that can, optionally, drive other input multiplexers in the same logic block, providing additional selection options among potential input signals. In some embodiments, the fan multiplexers are driven by global and/or regional clock signals. Thus, existing clock distribution structures can be used to provide high fanout input signals to the programmable logic circuit.Type: GrantFiled: June 14, 2005Date of Patent: March 27, 2007Assignee: Xilinx, Inc.Inventors: Steven P. Young, Trevor J. Bauer
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Patent number: 7196544Abstract: A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.Type: GrantFiled: March 30, 2006Date of Patent: March 27, 2007Assignee: Micron Technology, Inc.Inventor: Daniel R. Loughmiller
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Patent number: 7196545Abstract: A high frequency latch comprising a latch and a plurality of buffers coupled to peak load circuitry produces a peak response at a desired frequency of operation as well as isolating each high frequency latch output of a plurality of outputs to substantially reduce the effects of a kickback signal coupled into the latch output. The peaked load circuitry comprises selectable resistive elements and selectable capacitive elements coupled as a high pass filter to change the bias on a saturation region MOSFET configured as an active load. The high pass filter produces positive feedback on the saturation region MOSFET to increase the bias at high frequencies thereby producing an increased response at a desired operating frequency.Type: GrantFiled: March 29, 2004Date of Patent: March 27, 2007Assignee: Xilinx, Inc.Inventors: Eric D. Groen, Charles W. Boecker, William C. Black
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Patent number: 7196546Abstract: According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.Type: GrantFiled: December 30, 2003Date of Patent: March 27, 2007Assignee: Intel CorporationInventors: Mark A. Anders, Peter Caputa, Ram Krishnamurthy
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Patent number: 7196547Abstract: A level shifter has a voltage converting circuit converting an input signal provided by a first power supply into an output signal provided by a second power supply, and a reset circuit outputting a reset signal when the first power supply is turned off. The voltage converting circuit has: first and second FETs which are cross-coupled; a first trigger FET connected to the second FET and triggering it in response to the input signal; a second trigger FET connected to the second FET in parallel with the first trigger FET; a third trigger FET connected to the first FET and triggering it in response to an inversion signal of the input signal; and a fourth trigger FET connected to the first FET in parallel with the third trigger FET. Any of the second and the fourth trigger FETs triggers corresponding one of the second FET and the first FET in response to the reset signal.Type: GrantFiled: June 2, 2005Date of Patent: March 27, 2007Assignee: NEC Electronics CorporationInventor: Yukio Kozawa
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Patent number: 7196548Abstract: A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.Type: GrantFiled: August 25, 2004Date of Patent: March 27, 2007Assignee: Intel CorporationInventors: Mark A. Anders, Atul Maheshwari, Ram Krishnamurthy
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Patent number: 7196549Abstract: In one embodiment, a differential transistor pair of an ECL differential amplifier is formed on two different semiconductor die.Type: GrantFiled: December 13, 2004Date of Patent: March 27, 2007Assignee: Semiconductor Components Industries, L.L.C.Inventor: Ira E. Baskett
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Patent number: 7196550Abstract: A circuit for driving a pair of input signals to form driven output signals while reducing the amount of skew between the driven output signals. In one embodiment, a driver circuit includes a first set of drivers connected in series and receiving the first input signal to produce a first output signal; a second set of drivers connected in series and receiving the second input signal to produce a second output signal; a first transmission gate connecting an input of one of the drivers from the first set of drivers to an output of one of the drivers of the second set of inverters; and a second transmission gate connecting an input of one of the drivers from the second set of drivers to an output of one of the drivers of the first set of drivers. Each transmission gate may be provided with a control for enabling or disabling the transmission gate, thereby permitting the selective application of the de-skew function of the circuit and providing for reduced power consumption when the de-skew function is disabled.Type: GrantFiled: June 23, 2004Date of Patent: March 27, 2007Assignee: Cypress Semiconductor CorporationInventor: Robert M. Reinschmidt
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Patent number: 7196551Abstract: Systems and methods provide current mode logic buffers and interface circuits. As an example, in accordance with an embodiment of the present invention, a CML buffer is disclosed that receives and/or provides multiple signal pairs having different common mode voltages to operate over a wider common mode voltage range.Type: GrantFiled: May 28, 2004Date of Patent: March 27, 2007Assignee: Lattice Semiconductor CorporationInventor: Kochung Lee