Abstract: A semiconductor light-emitting device has a semiconductor substrate, an n-type cladding layer, an active layer, a p-type cladding layer, a p-type buffer layer, a p-type contact layer, and a current spreading layer. A part or all of the p-type buffer layer has a low Mg concentration buffer layer with a Mg concentration of 3.0×1017/cm3 or less and a film thickness of 50 nm or more.

Abstract: An Organic Light Emitting Display (OLED) includes: a lower substrate having at least one thin film transistor arranged thereon in a active region and a power supply lower stripe arranged thereon in a non-emissive region; an upper substrate corresponding to the lower substrate and having a power supply upper stripe arranged thereon in the non-emissive region; and a conductive spacer arranged between the upper stripe and the lower stripe in the non-emissive region to electrically connect the upper stripe to the lower stripe.

Abstract: A semiconductor device includes a light-emitting layer of a first conductivity type, a second conductivity type or non-doped type, a first contact layer of the second conductivity type disposed on the light-emitting layer and supplied with a voltage via a predetermined contact, a second contact layer of the second conductivity type disposed below the light-emitting layer and supplied with a voltage via a predetermined contact, a first etching stopper layer of the first or second conductivity type disposed below the light-emitting layer and above the second contact layer, and a third contact layer of the first conductivity type disposed below the second contact layer and supplied with a voltage via a predetermined contact.

Abstract: A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25?{N1/(N1+N2)}×100?75.

Abstract: The present invention relates to a semiconductor device; in particular, an object of the invention is to provide a semiconductor device in which a main current flows in a direction of thickness of the semiconductor substrate and which offers satisfactory performance and breakdown voltage and also satisfactory mechanical strength of the semiconductor substrate, and which needs no inconvenient control of the exposure system etc. during photolithography process.

Abstract: The present invention provides a field effect transistor having a double recess structure, which minimizes an influence exerted on a channel region depending upon the surface state of an outer recess section. In the field effect transistor having such a double recess structure, an ohmic contact layer at the surface of the outer recess section is made thick to deplete the ohmic contact layer completely.

Abstract: Methods for forming a SiC BJT having a low base resistance and minimal emitter width are provided. The methods incorporate a plated shadow metal layer overhanging the emitter mesa. The mushroom-shaped shadow metal layer can then act as either a deposition shadow mask or an ion implantation mask in subsequent steps for forming base contacts. In this way, base contacts can be formed with a variable and controllable distance from the emitter mesa defined by the lateral extent of overhang of the shadow metal layer. The same shadow masking effect can also be used to form self-aligned emitter and base wiring metals for reduction of resistance. Plating of the emitter contact layer allows avoiding subsequent photolithography steps on the top of emitter mesa; thus emitter mesa width could be minimized.

Abstract: Final sections of the word lines are arranged in a staggered fashion to fan out and have larger lateral extensions than the word lines. Interspaces are filled with a dielectric material, and a mask is applied that partially covers the final sections and leaves contact areas in regions adjacent to the final sections and to the interspaces open. This mask is used to remove the dielectric material between the word line stacks. A second word line layer is applied and planarized to form second word lines between the first word lines, which have contact areas arranged in a staggered fashion to fan out like the final sections of the first word lines.

Abstract: Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.

Abstract: Example embodiments relate to an image sensor and a fabrication method thereof. An image sensor may include a semiconductor substrate. A charge transfer structure may be formed on the semiconductor substrate. The charge transfer structure may include a gate insulating film that may be formed on a channel region in the semiconductor substrate between a photoelectric conversion region and charge detection region, and a transfer gate electrode that may be formed on the gate insulating film that may have a region doped with a first conductivity type impurity-doped region and a second conductivity type impurity-doped region which may be adjacent to each other.

Abstract: An image sensor includes a substrate having an active pixel sensor region defined therein, a plurality of first conductivity type photodiodes formed in the active pixel sensor region and a first conductivity-type first deep well formed in the active pixel sensor region in a location which does not include the plurality of the first conductivity-type photodiodes. Moreover, the first deep well is electrically connected to a positive voltage.

Abstract: A gas-sensitive field effect transistor reads signals generated by the principle of measuring work functions, for the detection of chlorine (Cl) with a gas-sensitive layer of gold.

Abstract: Proposed is a III-V-semiconductor-containing epitaxial substrate comprising at least one layer of porous III-V semiconductor material, together with a corresponding production method. Also specified is a component, particularly an LED, produced on the proposed epitaxial substrate, and a corresponding production method.

Abstract: A semiconductor capacitor that includes a plurality of overlapping conductive layers and a field-effect transistor. The plurality of conductive layers include a first and second conductive layers that are spaced apart to creating a capacitance between the plurality of layers. In the semiconductor capacitor, the FET has a source, a drain and a gate. When the FET is in conduction mode, a capacitance is created between the gate and the conductive path in the semiconductor substrate between the source and the drain. The semiconductor capacitor's total capacitance is increased by coupling the drain and the source to the first conductive layer and coupling the gate to the second conductive layer.

Abstract: A semiconductor device with a fin structure according to one embodiment of the present invention includes: a fin of a predetermined height formed on an insulating layer of a substrate; a gate electrode formed on both sides of the fin through a gate insulating film; and a source/drain region formed in the fin on both sides of the gate electrode by implanting impurities into the fin; wherein a concentration of the impurities forming the source/drain region in a vicinity of an interface between the fin and the insulating layer in the fin is lower than a concentration of the impurities in a vicinity of the interface between the fin and the insulating layer in the insulating layer.

Abstract: To arrange diffusion-inhibitory films 5a, 5b, and 5c for inhibiting the diffusion of a wiring material absent in a region on or above a light receiving unit 2, the diffusion-inhibitory films 5a, 5b, and 5c formed on a region above the light receiving unit 2 are selectively removed. Alternatively, the diffusion-inhibitory films are arranged only on top surfaces of wirings 4a, 4b, and 4c, and only a passivation film 12 and interlayer insulating films 3a, 3b, and 3c are arranged in the region on or above the light receiving unit 2. Thus, with less interface between different insulation films and less reflection of incident light in an incident region, the incident light 13 highly efficiently passes through these insulating films and comes into the light receiving unit 2. The light receiving unit 2 can thereby receive a sufficient quantity of the incident light 13.

Abstract: On the front side of an n-type semiconductor substrate 5, p-type regions 7 are two-dimensionally arranged in an array. A high-concentration n-type region 9 and a p-type region 11 are disposed between the p-type regions 7 adjacent each other. The high-concentration n-type region 9 is formed by diffusing an n-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 as seen from the front side. The p-type region 11 is formed by diffusing a p-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 and high-concentration n-type region 9 as seen from the front side. Formed on the front side of the n-type semiconductor substrate 5 are an electrode 15 electrically connected to the p-type region 7 and an electrode 19 electrically connected to the high-concentration n-type region 9 and the p-type region 11.

Abstract: The present invention provides techniques to fabricate high dielectric MIM storage cell capacitors. In one embodiment, this is accomplished by forming a silicon contact is then formed to electrically connect the formed bottom electrode layer in the container with the at least one associated transistor device. A titanium nitride barrier layer is then formed over the silicon contact. An oxygen barrier layer including platinum stuffed with silicon oxide is then formed over the titanium nitride layer and below the bottom electrode layer. A bottom electrode layer is then formed using platinum over interior surfaces of a container formed relative to at lest one associated transistor device on a silicon substrate. Further, a high dielectric insulator layer is formed over the bottom electrode layer. A top electrode layer is then formed over the high dielectric insulator layer.

Abstract: A light emitting diode (LED) is disclosed. The LED includes a substrate, a patterned semiconductor layer, two contact pads, a dielectric layer and a fluorescence thin film. Wherein, the patterned semiconductor layer is disposed on the substrate and suitable for emitting a first light, while the contact pads are disposed on the patterned semiconductor layer. The dielectric layer covers the patterned semiconductor layer and exposes a portion of the contact pads. In addition, the fluorescence thin film is disposed on the dielectric layer and emits a second light with a wavelength different from the first light after irradiated by the first light. Moreover, a LED package with the above-described LED is provided as well.

Abstract: A phase change memory device and a method of forming the same are provided. The phase change memory device includes a conducting electrode in a dielectric layer, a bottom electrode over the conducting electrode, a phase change layer over the bottom electrode, and a top electrode over the phase change layer. The phase change memory device may further include a heat sink layer between the phase change layer and the top electrode. The resistivities of the bottom electrode and the top electrode are preferably greater than the resistivity of the phase change material in the crystalline state.

Abstract: In accordance with the invention, there are methods for making and there is an integrated circuit comprising a semiconductor substrate comprising device elements and a metallization layer interconnecting the device elements and having an uppermost layer. The integrated circuit can also include a protective overcoat formed over the metallization layer, the protective overcoat having a plurality of patterned regions that expose portions of the metallization layer, a first conductive layer formed on the protective overcoat, and a dielectric layer formed over the first conductive layer. The integrated circuit can further include a second conductive layer formed over the dielectric layer and a plurality of sidewall spacers contacting end portions of the first conductive layer.

Abstract: The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.

Abstract: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Abstract: In a non-volatile semiconductor memory device typically of a MONOS type storing data by trapping charge in a multilayer film composed of a plurality of insulating films, which includes: source and drain regions of a second conductivity type disposed apart from each other in a semiconductor substrate of a first conductivity type; and a multilayer film composed of a plurality of insulating films and disposed on top of a channel region between the source and drain regions, a heavily doped region higher in impurity concentration than the semiconductor substrate is provided in part of the channel region to be in contact with only one of the source and drain regions, and in an uppermost top oxide film of the multilayer film on the channel region, only a portion overlapping with the heavily doped region in a plane view is smaller in thickness than the other portion, whereby a stepped portion is formed.

Abstract: A flash memory structure comprises a semiconductor substrate having a V-groove, a first doped region positioned in the semiconductor substrate, two second doped regions positioned in the semiconductor substrate and at two sides of the V-groove, a dielectric stack having trapping sites interposed therein positioned on the V-groove, and a conductive layer positioned on the surface of the dielectric stack above the V-groove. A method for forming the V-groove comprises steps of forming a mask layer on the surface of the semiconductor substrate, forming an opening in the mask layer, etching a portion of the semiconductor substrate below the opening to form the V-groove, and removing the mask layer. The semiconductor substrate can be a (100)-oriented silicon substrate, and the V-groove has inclined surface planes with (111) orientation.

Abstract: A nonvolatile semiconductor memory has a memory cell structure with a doped semiconductor substrate, a gate electrode, a channel area disposed in the substrate below the gate electrode, a pair of variable resistance areas disposed on opposite sides of the channel area in the substrate, charge storage bodies formed above the variable resistance areas and on the sides of the gate electrode, and highly doped source and drain areas formed on opposite sides of the variable resistance areas in the substrate. The variable resistance areas are doped at a carrier concentration of 5×1017 cm?3 or less to ensure an adequate current difference between the programmed and erased states of the memory cell. The doping of the variable resistance areas differs from the lightly doped drain doping in peripheral circuit areas.

Abstract: A capacitor includes a lower electrode, a first dielectric film composed of lead zirconate titanate niobate formed above the lower electrode, a second dielectric film composed of lead zirconate titanate or lead zirconate titanate niobate with a Nb composition smaller than a Nb composition of the lead zirconate titanate niobate composing the first dielectric film, and an upper electrode formed above the second dielectric film.

Abstract: A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

Abstract: A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through a first insulator, an isolation formed between the plurality of first conductor layers, a silicon oxide film formed on the first conductor layer, a high-dielectric-constant insulator formed on the silicon oxide film and the isolation and being diffused silicon and oxygen at least in a surface thereof contacting with the silicon oxide film, and a second conductor film formed above the high-dielectric-constant insulator.

Abstract: A flash memory structure comprises a silicon substrate having at least one concave structure, two doped regions positioned in the semiconductor substrate and at two sides of the concave structure, at least one carrier trapping region positioned in the concave structure, and a conductive layer positioned above the concave structure. The concave structure comprises two grooves having a U-shaped or V-shaped profile. The grooves have an inclined plane with (111) orientation and a bottom plane with (100) orientation of the silicon substrate. The carrier trapping region comprises a dielectric stack positioned in the concave structure, wherein the dielectric stack comprises a first oxide layer positioned on the surface of the silicon substrate, a nitride block positioned on the surface of the first oxide layer and in the concave structure, and a second oxide layer covering the first oxide layer and the nitride block.

Abstract: In a circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device, the circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region; bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction; channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another; gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars; buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region; local interconnection lines contacting side surfaces of the gate

Abstract: This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source contact opening opened on top of an area extended over the body region and the source region through a protective insulation layer wherein the area further has a cobalt-silicide layer disposed near a top surface of the substrate. The MOSFET cell further includes a Ti/TiN conductive layer covering the area interfacing with the cobalt-silicide layer over the source contact opening. The MOSFET cell further includes a source contact metal layer formed on top of the Ti/TiN conductive layer ready to form source-bonding wires thereon.

Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

Abstract: The self-aligned Schottky-barrier clamped trench DMOS transistor structure of the present invention comprises a Schottky-barrier diode being formed in a middle semiconductor portion of a self-aligned source region. The self-aligned source region comprises a lightly-doped epitaxial semiconductor layer, a moderately-doped base diffusion ring being formed in a surface portion of the lightly-doped epitaxial semiconductor layer surrounded by a trench gate region, a heavily-doped source diffusion ring being formed in a side surface portion of the moderately-doped base diffusion ring, and a self-aligned source contact being formed on a semiconductor surface of the self-aligned source region surrounded by a sidewall dielectric spacer. The trench gate region comprises a self-aligned conductive gate layer being formed over a gate dielectric layer lined over a trenched semiconductor surface in a shallow trench with or without a thicker isolation dielectric layer being formed on a bottom surface of the shallow trench.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.

Abstract: A MOSFET comprising an epitaxial layer of a semiconductor substrate of a first conductivity type, the MOSFET comprises a polysilicon gate, a source region of the first conductivity type and a body region of a second conductivity type, the polysilicon gate comprises a first layer of polysilicon and a second layer of polysilicon sandwiching a layer of polysilicon etch stop substances.

Abstract: A thin-film transistor includes a substrate having a substantially outwardly protruding support structure formed thereon such that a portion adjacent to the structure is exposed. The support structure has opposed sidewalls sloped at an angle relative to the substrate surface. A stack is established over the portion and over a portion of an adjacent opposed sidewall. The stack includes an insulating layer. A channel material is established on at least a portion of the stack, thus forming a channel having a length substantially determined by a thickness of the insulating layer in relation to the adjacent opposed sidewall angle. A gate dielectric is established on at least a portion of the channel material and a gate electrode is established on at least a portion of the gate dielectric.

Abstract: According to the present invention, there is provided a semiconductor memory device having: a semiconductor layer of a first conductivity type formed above a semiconductor substrate via an embedded insulation film, a gate electrode formed above the semiconductor layer via a gate insulation film, a floating body region of a first conductivity type formed under the gate electrode in the semiconductor layer of a first conductivity type, which functions as a collector region of a first conductivity type, a source region of a second conductivity type and a drain region of a second conductivity type formed on both sides of the floating body region in the semiconductor layer, the drain region functioning as a base region of a second conductivity type, an emitter region of a first conductivity type formed in the semiconductor layer, adjacent to the side opposite to the side of the floating body region in the drain region, and silicide formed at least on the surface portion of the source region.

Abstract: An SOI semi-conductor element has field electrodes and/or field zones which are arranged between a first and a second semi-conductor zone. Electric coupling is possible between the field electrodes and the field zones.

Abstract: A CMOS inverter cell having a small horizontal length which is reduced by substituting metal lines for supplying data signals to gates with a connection pattern which is mounted in one end of a supply voltage area of the CMOS inverter cell and is made of the same material as the gate. Data is supplied to the gates through at least one side of the CMOS inverter cell. A single gate pattern or a plurality of different gate patterns may be used.

Abstract: A thin film transistor and a method of fabricating the same capable of reducing stress of a substrate caused by a metal layer of the drain and source electrodes, the thin film transistor including a substrate; a semiconductor layer disposed on the substrate and including source, drain and channel regions; a gate insulating layer disposed on the substrate including the semiconductor layer; a gate electrode disposed on the gate insulating layer to correspond to the channel region of the semiconductor layer; an interlayer insulating layer disposed on the substrate including the gate electrode, and having contact holes connected with the source and drain regions of the semiconductor layer; and source and drain electrodes connected with the source and drain regions through the contact holes, wherein the source and drain electrodes include a first metal layer, a second metal layer, and a metal oxide layer interposed between the first metal layer and the second metal layer.

Abstract: The present invention provides a method, an apparatus, and a computer program product for measuring the temperature of a microprocessor through the use of ESD circuitry. The present invention uses diodes and an I/O pad within ESD circuits to determine the temperature at the location of the ESD circuitry. First, a current measuring device connects to a diode. A user or a computer program disables the protected component or circuitry, and subsequently applies a predetermined voltage to the I/O pad. This creates a reverse saturation current through the diode, which is measured by the current measuring device. From this current the user or a computer program determines the temperature of the microprocessor at the diode through the use of a graphical representation of diode reverse saturation current and corresponding temperature.

Abstract: An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Abstract: There is provided a semiconductor device wherein at least the largest width of a source/drain region is larger than the width of a semiconductor region and the source/drain region has a slope having a width continuously increasing from the uppermost side to the substrate side, and a silicide film is formed in the surface of the slope.

Abstract: Realizing that rather than protect electronic circuitry, electrostatic discharge networks when hit by cosmic rays and charged particles, can actually cause the electronic circuitry in satellites and other space applications to fail, the inventor created an ESD network having a redundant voltage clamping element in series with a first voltage clamping element between two voltage pads. The ESD network may be connected to a power voltage pad or a signal voltage pad either directly or through a dummy voltage pad. The voltage clamping elements may further comprise an array of unit cells wherein the array is electrically equivalent to single large transistors currently used in ESD networks. By creating an ESD network as an array of unit cells, benefits greater than those obtained by using a single transistor as a clamping or a trigger element are realized—such as increased ballast resistance and less overall damage to the circuitry resulting from cosmic rays and particles.

Abstract: A semiconductor device includes: a first field-effect transistor including a first gate electrode; and a second field-effect transistor including a second gate electrode. The first and second gate electrodes are fully silicided with metal and have different gate lengths. A trench is formed in an upper portion of the first gate electrode such that a rim portion of the first gate electrode is high and a middle portion of the first gate electrode in a gate length direction is low. The trench has a width depending on the gate length of the first gate electrode.

Abstract: A field effect semiconductor component has a bipolar transistor structure in a semiconductor body consisting of a lightly doped upper area of a first conductivity type as base region and of a lower heavily doped area as emitter region with a complementary conductivity type. Between the base region and the emitter region, a horizontal pn junction forms. The emitter region is in resistive contact with a large-area emitter electrode on the rear of the semiconductor component. On the top of the semiconductor component, a first insulated gate electrode and a second insulated gate electrode are arranged adjacently in the area close to the surface. A vertical pn junction region insulated from the upper area is arranged in such a manner that a collector region and the base region of the bipolar transistor structure can be controlled via the insulated gate electrodes (G1 and G2) arranged electrically separately.

Abstract: A semiconductor device comprises a semiconductor substrate having an N-type base region, a collector region, a P-type base region, an emitter region, a collector-shorting region, a buffer region, and a P-type semiconductor region, and a gate bus line disposed on the P-type semiconductor region through an insulating film. The collector-shorting region is formed at a region in the collector region opposite to the gate bus line. Accordingly, it is possible to secure the area of the collector region which is opposite to a gate electrode. The collector-shorting region discharges carriers well.

Abstract: A semiconductor structure having a recessed active region and a method for forming the same are provided. The semiconductor structure comprises a first and a second isolation structure having an active region therebetween. The first and second isolation structures have sidewalls with a tilt angle of substantially less than 90 degrees. The active region is recessed. By recessing the active region, the channel width is increased and device drive current is improved.