Abstract: A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gate and a gate dielectric layer disposed between the gate and the substrate. The spacer is disposed on the sidewall of the gate structure. The source/drain region is disposed in the substrate on two sides of the spacer. The barrier layer is disposed around the source/drain region. The source/drain region and the barrier layer are fabricated using an identical material. However, the doping concentration of the source/drain region is larger than the doping concentration of the barrier layer.

Abstract: A metal-oxide-semiconductor transistor device is disclosed, in which, a silicon nitride spacer has been formed but is removed after an ion implantation process to form a source/drain region and a salicide process to form a metal silicide layer on the surface of the source/drain region and the gate electrode are performed. The metal silicide layer comprises silicon, nickel and at least one metal selected from a group consisting of iridium, iron, cobalt, platinum, palladium, molybdenum, and tantalum; therefore, when the silicon nitride spacer is removed by etching, the metal silicide layer is not damaged.

Abstract: A semiconductor device includes a semiconductor layer formed partially on a semiconductor substrate by epitaxial growth, an embedded oxide film embedded between the semiconductor substrate and the semiconductor layer, first and second gate electrodes disposed on sidewalls of the semiconductor layer, a source layer formed in the semiconductor layer and disposed in the first gate electrode, and a drain layer formed in the semiconductor layer and disposed in the second gate electrode, wherein the sidewalls of the semiconductor layer are film-forming surfaces of the epitaxial gowth.

Abstract: The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

Abstract: An integrated circuit is provided, and in the integrated circuit, a microlens array is formed with a silicon nitride film which provides an interlayer insulation film for Al wiring, so that any stress migration in the Al wiring and any deformation of lens shape can be prevented. A silicon nitride film is formed on a semiconductor substrate as an interlayer insulation film between a first-layer wiring and a second-layer wiring. The silicon nitride film includes, in an image pickup section, a lens array having a plurality of convex lenses which are formed with a surface of the silicon nitride film. A silicon dioxide film is grown on the silicon nitride film. Then, a second Al film is formed on the silicon dioxide film. The Al film is etched in an unnecessary portion such as the surfaces of the lens array, to form wiring.

Abstract: A semiconductor device having a vertical gate and method of manufacturing the same are disclosed. An example semiconductor device includes a pair of first source/drain regions formed apart from each other by a predetermined distance on a silicon substrate, a first silicon epitaxial layer formed on the pair of first source/drain regions, a vertical gate insulation layer formed at both sidewalls of the first silicon epitaxial layer, and a second silicon epitaxial layers formed on the first silicon epitaxial layer and on the gate insulation layer. The example device includes a pair of second source/drain regions formed in the second silicon epitaxial layer formed on the first silicon epitaxial layer, at positions above the pair of first source/drain regions, and a plurality of vertical gates respectively connected to the second silicon epitaxial layer formed on the gate insulation layer and to the pair of second source/drain regions.

Abstract: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.

Abstract: A SONOS gate structure has an oxide structure on a substrate having gate pattern thereon. The oxide structure has a relatively thinner oxide portion on the substrate for keeping good program/erase efficiency, and a relatively thicker oxide portion on sidewalls of the gate pattern for inhibiting gate disturb. Trapping dielectric spacers are on formed the oxide structure laterally adjacent to said sidewalls of said gate pattern respectively.

Abstract: The present invention provides a film hole forming apparatus (400), which includes a chemical etching system (410) and a driving system (420). The driving system comprising a transmission belt, which pass through the chemical etching system. A material of the transmission belt being teflon, teflon-containing material, poly (vinylidene finoride), metal, or metal-sandwiched composite. The present invention also provides a method for forming film holes, which includes the following steps: providing a flexible printed circuit board to be etched, with copper holes pre-formed thereat and the copper holes expose base film (310) at corresponding positions; and transporting the flexible printed circuit boards into a chemical etching system by a transmission belt to form film holes in the base film.

Abstract: An acceleration sensor includes a semiconductor substrate, a first layer formed on the substrate, a first aperture within the first layer, and a beam coupled at a first end to the substrate and suspended above the first layer for a portion of the length thereof. The beam includes a first boss coupled to a lower surface thereof and suspended within the first aperture, and a second boss coupled to an upper surface of the second end of the beam. A second layer is positioned on the first layer over the beam and includes a second aperture within which the second boss is suspended by the beam. Contact surfaces are positioned within the apertures such that acceleration of the substrate exceeding a selected threshold in either direction along a selected axis will cause the beam to flex counter to the direction of acceleration and make contact through one of the bosses with one of the contact surfaces.

Abstract: Provided is an optical element including: a substrate; at least one at least partially ordered orientation facility connected to at least a portion of the substrate; and an at least partial coating connected to at least a portion of the at least partially ordered orientation facility. The at least partial coating includes at least one at least partially ordered anisotropic material. At least one photochromic-dichroic compound is at least partially aligned with at least a portion of the at least partially ordered anisotropic material.

Abstract: An image pickup device comprises: a flexible substrate; a photosensitive layer formed above the flexible substrate and sandwiched between a pixel electrode layer and an opposite electrode layer; a signal reading section, formed on the flexible substrate, that reads a photoelectric charge generated as a result of incidence of light into the photosensitive layer; and a flexibility increasing section that splits the photosensitive layer between pixels in a predetermined position, the flexibility increasing section extending in a direction perpendicular to a surface of the flexible substrate.

Abstract: Radiation hardening, detection and protection design methods are disclosed. An example write drive circuit is disclosed having radiation hardened analog circuitry. A passive transistor is provided to generate a radiation photo-current to offset any net radiation photo-current of the operational circuitry. Using this technique, a radiation hardened reference-mirror control circuit provides a switched write current for setting the logical state of MRAM bits during a radiation event, for instance. A radiation detector and radiation hardened logic gates are further provided for inhibiting the write current when a radiation level is above a predetermined level.

Abstract: Pt/n?GaN Schottky barrier diodes are disclosed that are particularly suited to serve as ultra-violet sensors operating at wavelengths below 200 nm. The Pt/n?GaN Schottky barrier diodes have very large active areas, up to 1 cm2, which exhibit extremely low leakage current at low reverse biases. Very large area Pt/n?GaN Schottky diodes of sizes 0.25 cm2 and 1 cm2 have been fabricated from n?/n+GaN epitaxial layers grown by vapor phase epitaxy on single crystal c-plane sapphire, which showed leakage currents of 14 pA and 2.7 nA, respectively for the 0.25cm2 and 1 cm2 diodes both configured at a 0.5V reverse bias.

Abstract: A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench.

Abstract: In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P+-type source region (8), an N-type body region (4) and an N+-body contact diffusion region (10) are surrounded by a P+-type drain region (9) and a P-type drift region (5). A gate electrode (7) is formed to overlap the end portion of the N-type body region (4). The end portion of the N-type body region (4) has a portion in which the gate electrode (7) and the P+-type source region (8) are not adjacent to each other.

Abstract: A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls in a semiconductor substrate having first and second opposing surfaces. An inductor is formed on the first surface of the semiconductor substrate and a hole is formed through the second surface of the substrate to expose the substrate between the first and second lateral etch stop walls. The substrate is isotropically etched between the first and second lateral etch stop walls through the etch hole to create a cavity within the semiconductor substrate. A sealing layer is formed over the etch hole to seal the cavity.

Abstract: A capacitor of a semiconductor device and a method of fabricating a capacitor in a semiconductor device are disclosed. The capacitor may include a bottom electrode formed on a semiconductor substrate, an insulation layer having different regions having different thicknesses, and a top electrode over a region of the insulation layer that has a relatively great thickness.

Abstract: A semiconductor device includes a semiconductor substrate having a diffusion layer. An insulating film is formed on the semiconductor substrate, a fuse section of fuses is formed on the insulating film. An interlayer insulating film is formed on the fuse section and the insulating film, and an antenna section is formed on the interlayer insulating film in correspondence to the fuse section.

Abstract: A first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and a second capacitor is formed on the substrate and connected to a second differential node of the differential circuit. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate.

Abstract: Devices, systems, and methods for providing an on-chip, temperature-stable resistance network for generating a precision current or precision resistance are disclosed. The resistance network includes a first resistance material having a linear, negative temperature coefficient of resistance and a second resistance material having a linear, positive temperature resistance. The first and second resistance materials are arrayed in segments proximate to a local, pulsed thermal gradient and are combined or mixed, i.e., trimmed, to provide a zero or near zero thermal coefficient.

Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.

Abstract: Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer. An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Feature sizes are determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated.

Abstract: One aspect of this disclosure relates to a memory device, comprising at least one gettering region, a memory array, a plurality of word lines and bit lines, and control circuitry. The gettering region is formed in a semiconductor substrate. The gettering region includes a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate. The memory array is formed in the crystalline semiconductor region, and includes a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells. Each word line is connected to a row of memory cells, and each bit line is connected to a column of memory cells. The control circuitry includes word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations.

Abstract: An attachment system. The attachment system includes a first structure and a second structure. The first structure has a surface and a recess in the surface. The second structure is molded into the recess and extends above the surface. The second structure adheres to the first structure at a boundary of the recess.

Abstract: The functional structural element includes: a substrate member which has a surface made of directionally solidified silicon; and a functional structural body which is made of a functional material and is formed on the surface of the substrate member.

Abstract: An integrated circuit package system is provided including an integrated circuit package system including an integrated circuit and a lead frame. The lead frame has a multi-surface die attach pad and the integrated circuit is mounted to the multi-surface die attach pad.

Abstract: A system may include a conductive plane defining a non-conductive antipad area and a second non-conductive area extending from the antipad area in at least a first direction, a dielectric plane coupled to the conductive plane, a conductive via passing through the dielectric plane and the antipad area, a conductive pad connected to an end of the conductive via, and a conductive trace coupled to the dielectric plane and connected to the conductive pad, the conductive trace extending from the conductive pad in the first direction.

Abstract: A wafer level method for metallizing source, gate and drain contact areas of a semiconductor die includes the steps of (a) plating Ni onto the source, gate and drain contact areas of the semiconductor die, and (b) plating Au onto the source, gate and drain contact areas of the semiconductor die after completing step (a). A semiconductor package having plate interconnections between leadframe leads and the metalized passivation areas is also disclosed.

Abstract: Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.

Abstract: A wiring substrate to which a semiconductor element 10 is connected, is a wiring substrate 20 comprised of a glass substrate with through-hole groups 20d, each group consisting of a plurality of through holes 20c extending from input surface 20a to output surface 20b and formed in a predetermined array, and conductive members 21 formed on respective inner walls of the through holes 20c in each through-hole group 20d so as to establish electrical continuity between input surface 20a and output surface 20b. A bump electrode 12 of semiconductor element 10 connected to the input surface 20a corresponds to each through-hole group 20d, conductive member 21, and conductive part 22 formed in a region covering the through-hole group 20d, and is connected so that a portion of the bump electrode 12 enters into an interior of each of the through holes 20c.

Abstract: In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.

Abstract: A semiconductor device (5) for radio frequency applications has a semiconductor chip (1) with an integrated circuit accommodated in a radio frequency package. Inside bumps (2) comprise inside contacts between the semiconductor chip (1) and a redistribution substrate (3). The inside bumps (2) have a metallic or plastic core (6) and a coating layer (7) of a noble metal.

Abstract: A state recognition tag is configured to include a tag main body, and a tag fragment separable from the tag main body, and each of the tag main body and the tag fragment is provided with an information holding unit storing therein information to be transmitted, a separation-state recognizing unit which recognizes a separation state between the tag main body and the tag fragment, a control unit which exercises transmission control for transmitting the information from the information holding unit based on the separation state, and an electric power supplying unit which supplies electric power to the information holding unit, the separation-state recognizing unit, and the control unit. Regardless of whether the tag main body and the tag fragment are connected to each other or separated from each other, both the tag main body and the tag fragment can function as tags as needed.

Abstract: A chip package for a computer system includes a substrate having a first region and a second region on a first surface, at least one die coupled to the first region on the first surface of the substrate and a main logic board coupled to the second region on the first surface of the substrate. By coupling the die and the main logic board on the first surface of the substrate, an overall thickness of the chip package is reduced.

Abstract: A semiconductor package according to the present invention includes a substrate; first and second semiconductor chips mounted on a first surface of the substrate; and a heat-radiation sheet. The heat-radiation sheet includes a heat-transferable conductive layer and first and second insulating layers formed on top and bottom surfaces of the heat-transferable conductive layer, respectively. The heat-radiation sheet includes a first portion arranged between the first semiconductor chip and the second semiconductor chip; and a second portion extending at least a side of the first portion. The second portion is connected to the substrate. The second insulating layer of the second portion is formed to expose a part of the heat-transferable conductive layer.

Abstract: A semiconductor device is disclosed wherein first wiring lines in a first row extend respectively from first connecting portions toward one side of a semiconductor chip, while second wiring lines extend respectively from second connecting portions toward the side opposite to the one side of the semiconductor chip. The reduction in size of the semiconductor device can be attained.

Abstract: The present invention provides a semiconductor device in which the warp of a board is suppressed without the need for provision of a solder resist on opposite surfaces of the board and semiconductor element connection characteristics are improved by reducing stress exerted on a connection portion, and increases flexibility in assembly process.

Abstract: Electronic devices, such as those having a flexible substrate and printed material on the flexible substrate. In one embodiment, the printed material and substrate are part of an electronic device having at least three terminals, wherein the electronic device has a charge carrier mobility of at least 10 cm2/V-s. Multi-terminal devices can have a substrate including a doped semiconductor layer and at least two doped regions formed upon the substrate. The doped regions can be doped oppositely from the semiconductor layer and exhibit a charge carrier mobility of greater than 10 cm2/V-s. Methods for making the same are also disclosed.

Abstract: A MEMS module package using a sealing cap having heat releasing capability is disclosed, which comprises a lower substrate, a MEMS element mounted on the lower substrate, a driver integrated circuit mounted on the lower substrate adjacently to the MEMS element which operates the MEMS element, and a sealing cap positioned in contact with the lower substrate which has a MEMS-element protrusion portion in physical contact with the MEMS element and has one or more grooves for housing the MEMS element and the driver integrated circuit. The MEMS module package using a sealing cap having heat releasing capability and a manufacturing method thereof according to an aspect of the present invention utilize an effective heat releasing structure to release the heat generated in each element.

Abstract: A shielding device is provided for reducing EMI for a PCB. The shielding device includes a plurality of conductive grounded portions arranged on the PCB, an insulating mask, and an auxiliary grounded layer. A plurality of through holes is defined in the insulating mask corresponding to the grounded portions. The auxiliary grounded layer provides a conductive surface. The grounded portions contact the conductive surface via the through holes.

Abstract: A semiconductor device includes: first to fourth vertical type semiconductor elements having first and second electrodes; a metallic lead; a resin mold; a circuit board; an electric circuit on the circuit board; and an electronic chip on the circuit board. The electronic chip drives and controls each semiconductor element through the electric circuit. The first to fourth semiconductor elements are arranged to be a stack construction in the resin mold. The first to fourth semiconductor elements provide a H-bridge circuit. Each of the first and second electrodes in each semiconductor element is directly connected to the metallic lead so that heat generated in the semiconductor element is radiated through the metallic lead.

Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.

Abstract: An ultra-thin wafer system providing thinning a wafer on a protective tape to an ultra-thin thickness and forming electrical interconnects on the thinned wafer on a support plate.

Abstract: Disclosed is an electronic device comprising a substrate, a bump formed on a substrate surface and composed of a first metal material, a junction film for connection with an electrical connecting portion of another device which is formed on the top face of the bump and composed of a second metal material, the melting point of which second metal material itself is lower than the melting point of an alloy thereof with the first metal material, and a diffusion-preventing film which is so arranged between the top face of the bump and the junction film as to cover at least a part of the top face of the bump and composed of a third metal material whose diffusion coefficient in the first metal material is lower than that of the second metal material.

Abstract: A semiconductor element with conductive bumps and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor element having a plurality of bond pads formed on an active surface thereof, wherein each of the bond pads has a predetermined bonding area; applying a passivation layer on the active surface, with a plurality of openings formed for exposing the predetermined bonding areas; applying a buffer layer on the passivation layer to cover the predetermined bonding areas; allowing the buffer layer with a plurality of openings to be formed for exposing a portion of the predetermined bonding areas; forming a under bump metallurgy (UBM) layer on the bond pads, allowing the predetermined bonding areas to be completely covered by the UBM layer; and implanting conductive bumps on the UBM layer. The buffer layer advantageously absorbs stresses exerted to the conductive bumps, thereby preventing the conducting bumps from cracking.

Abstract: In the peripheral part of a semiconductor chip, third electrode pads for wire bonding and plate wiring and first electrode pads dedicated to wire bonding are provided. On the other hand, second electrode pads dedicated to plate wiring are provided on an inner part away from the edge of the semiconductor chip. Further, the first and second electrode pads are connected via metal bypass layers, respectively. In the case of wire bonding, the first and third electrode pads are used and the third electrode pads are encapsulated with an insulating layer. Further, in the case of plate wiring, the second and third electrode pads are used and the first electrode pads are covered with an insulating layer. This realizes a semiconductor chip which has great versatility and which can be used in semiconductor packages of various types.

Abstract: The invention prevents a pad electrode for external connection of a semiconductor device from being damaged. An electronic circuit, a first pad electrode connected to the electronic circuit, and a second pad electrode connected to the first pad electrode are formed on a semiconductor substrate. A first protection film is formed, covering the first pad electrode and having an opening on the second pad electrode only. A wiring layer is further formed, being connected to the back surface of the first pad electrode through a via hole penetrating the semiconductor substrate and extending from the via hole onto the back surface of the semiconductor substrate.

Abstract: A flexible insulating base, a plurality of conductor wirings aligned on the flexible insulating base, and bump electrodes provided respectively in end portions of the plurality of conductor wirings in a region where a semiconductor chip is to be placed are provided. The semiconductor chip is mounted on the conductor wirings by bonding electrode pads formed on the semiconductor chip to the bump electrodes. An auxiliary conductor wiring formed similarly to the conductor wirings is provided on the insulating base, and an auxiliary bump electrode formed similarly to the bump electrodes is provided on the auxiliary conductor wiring, so that the electrode pads formed on the semiconductor chip can be registered with respect to the bump electrodes on the conductor wirings by positioning the semiconductor chip with reference to the auxiliary bump electrode.

Abstract: A method for forming a metal carbide layer begins with providing a substrate, an organometallic precursor material, at least one doping agent such as nitrogen, and a plasma such as a hydrogen plasma. The substrate is placed within a reaction chamber; and heated. A process cycle is then performed, where the process cycle includes pulsing the organometallic precursor material into the reaction chamber, pulsing the doping agent into the reaction chamber, and pulsing the plasma into the reaction chamber, such that the organometallic precursor material, the doping agent, and the plasma react at the surface of the substrate to form a metal carbide layer. The process cycles can be repeated and varied to form a graded metal carbide layer.