Abstract: The sizes of crystal masses are made to be a uniform in a crystalline silicon film obtained by a thermal crystallization method in which a metal element is used. An amorphous silicon film to be crystallized is doped with a metal element that accelerates crystallization, and then irradiated with laser light (with an energy which is not large enough to melt the film and which is large enough to allow the metal element to diffuse in the solid silicon film) from the back side of a light-transmissive substrate. Thereafter, heat treatment is performed to obtain a crystalline silicon film. Thus crystal masses in the crystalline silicon film can have a uniform size and the problem of fluctuation between TFTs can be solved.

Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).

Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

Abstract: Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided.

Abstract: A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

Abstract: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

Abstract: Disclosed is a method of manufacturing a flash memory device. In a flash memory device using a SA-STI scheme, a trench for isolation is buried with oxide. A field oxide film is then formed by means of a polishing process. Next, field oxide films of a cell region and a low-voltage transistor region are selectively etched by a given thickness. As EFH values of the cell region, the low-voltage transistor region and the high-voltage transistor region become same or similar, it is possible to secure stability of a subsequent process.

Abstract: There are provided a method of fabricating a flash memory device and a flash memory device fabricated thereby. The method of fabricating a flash memory device includes forming an isolation layer defining an active region in a semiconductor substrate, wherein the isolation layer is formed to have a protrusion being higher than a top surface of the active region, and to provide a groove in the active region. A conductive layer pattern is formed in the groove. A buffer layer is formed on the semiconductor substrate having the conductive layer pattern. Then, an oxidation barrier layer pattern having a line shape opening across the active region is formed on the buffer layer. The buffer layer and an upper portion of the conductive layer pattern, which are exposed by the opening, are selectively oxidized to form a mask oxide layer at a cross region of the opening and the active region, and simultaneously to form a buffer oxide layer on the isolation layer adjacent to the mask oxide layer.

Abstract: When memory cells of EEPROM and a capacitor element are formed on a same semiconductor substrate, the number of processes is prevented from increasing and a manufacturing cost is reduced. Furthermore, reliability of the capacitor element is improved, and characteristics of the memory cells, a MOS transistor, and so on are prevented from changing. A pair of left and right memory cells is formed in a memory cell formation region of a P-type silicon substrate, being symmetrical to each other with respect to a source region, and a capacitor element formed of a lower electrode, a capacitor insulation film, and an upper electrode is formed in a capacitor element formation region of the same P-type silicon substrate. The lower electrode of the capacitor element is formed by patterning a polysilicon film provided for forming control gates of the pair of memory cells.

Abstract: A process for forming an electronic device can include forming a first trench within a substrate, wherein the trench includes a wall and a bottom and extends from a primary surface of the substrate. The process can also include forming discontinuous storage elements and forming a first gate electrode within the trench such that, a first discontinuous storage element of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The process can further include removing the discontinuous storage elements that overlie the primary surface of the substrate. The process can still further include forming a second gate electrode that overlies the first gate electrode and the primary surface of the substrate.

Abstract: The present invention relates to a method of forming an interlayer dielectric film in a semiconductor device. More particularly, the present invention selectively forms an insulating film spacer only at a region where a plug is formed between metal lines and removes the insulating film spacer at a region where the plug is not formed to lower the aspect ratio between the metal lines, in a process of burying an insulating material between the metal lines to electrically insulate them. Therefore, the present invention can easily bury the insulating material even between the metal lines having a narrow gap without voids.

Abstract: The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengths. Short-channel effects are prevented by the use of highly localized halo implant regions formed in the device channel. Highly localized halo implant regions are formed by a tilt pre-amorphization implant and a laser thermal anneal of the halo implant region.

Abstract: Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

Abstract: A method of fabricating a gate electrode of a semiconductor device is disclosed. A disclosed method comprises growing a silicon epitaxial layer on a silicon substrate; making at least one trench through the epitaxial layer and filling the trench with a first oxide layer; etching the first oxide layer to form reverse spacers in the trench; depositing a second oxide layer and a polysilicon layer over the silicon substrate including the trench and the reverse spacers and forming a gate; implanting ions in the silicon substrate at both sides of the gate to form pocket-well and LDD areas; depositing a nitride layer over the silicon substrate including the gate and etching the nitride layer to form spacers; implanting ions using the spacers and the gate as a mask to make a source/drain region; and forming a silicide layer on the top of the gate electrode and the silicon epitaxial layer positioned on the source/drain region.

Abstract: A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers.

Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Abstract: Semiconductor structures and methods for fabricating semiconductor structures are provided. The method comprises forming a first insulating layer having a substantially planar surface overlying a first conductive layer of an interconnect stack. A thin film resistor is formed overlying the first insulating layer and a second insulating layer is deposited overlying the first insulating layer and the resistor. A portion of the second insulating layer is removed to form a substantially planar surface. The second insulating layer is anisotropically etched to form a first via to the first conductive layer and a fill material comprising tungsten is deposited within the first via. The second insulating layer is wet etched to form a second via to the thin film resistor and a second conductive layer is deposited overlying the second insulating layer and within the second via.

Abstract: Semiconductor devices having a capacitor and methods of manufacturing the same are disclosed.

Abstract: A dielectric wiring structure and method of manufacture therefor. The wiring structure includes air dielectric formed in a hemisphere. The wiring structure also includes, in embodiments, a method of simultaneously forming a MEMS structure with a transistor circuit using substantially the same steps. The MEMS structure of this embodiment includes freestanding electrodes which are not fixed to the substrate.

Abstract: According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.

Abstract: A method including forming a first mask material layer on a semiconductor substrate in order to mask a cell region and to not mask a peripheral circuit region. The method further includes forming a second mask material layer on an entire surface of the substrate in the cell region and peripheral circuit region, simultaneously forming a trench having a first depth in the cell region and a trench having a second depth in the peripheral circuit region, where the second depth is greater than the first depth. The method also includes filling an insulation layer into an entire surface of the substrate including trenches, planarizing the insulation material layer and the second mask material layer to a degree that the first mask material layer is exposed, and respectively forming an STI isolation layer in both the cell region and the peripheral circuit region by removing the first and second mask material layer.

Abstract: A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. Another method includes forming a high density plasma proximate a substrate; flowing gases into the plasma, at least some of the gases forming silicon dioxide; depositing the silicon dioxide formed from the gases over the substrate; and while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. As an alternative, the method may include not cooling the substrate with a coolant gas while depositing the silicon dioxide.

Abstract: A pre-process before cutting a wafer is described. The wafer includes a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the corner regions of the dies. Removing the material layer at the corner regions before cutting the wafer is able to preserve the integrity of the corner regions of the cut dies.

Abstract: Numerous embodiments of a method and apparatus for laser annealing are disclosed. In one embodiment, a method of laser annealing includes performing one or more annealing processes on one or more portions of a semiconductor device, where one or more annealing processes performed on one or more portions of the semiconductor device are varied based at least in part on the particular portion of the semiconductor device being annealed, and/or on one or more desirable characteristics of the particular portion of the semiconductor device being annealed.

Abstract: A method for manufacturing a semiconductor device in which lower cost can be realized, a wiring with favorable coverage can be formed in a contact hole having a large aspect ratio, wiring capacitance can be reduced and a multilayer wiring can be formed, can be provided.

Abstract: Embodiments of the present invention are directed to methods for fabricating microscale-to-nanoscale interfaces. In numerous embodiments of the present invention, hybrid microscale/nanoscale crossbar multiplexers/demultiplexers provide for selection and control of individual nanowires through a set of microscale signal lines. In order to overcome the difficulty of aligning nanowires with submicroscale and microscale signal lines, at least a portion of the interconnections between nanowires and sub-microscale or microscale signal lines are randomly generated by one of various connection-fabrication methods. Addresses for individual nanowires, or groups of nanowires, can be discovered by testing the microscale-to-nanoscale interfaces.

Abstract: A process is provided for the selective metallization of 3D structures, particularly for the selective gold-plating of 3D contact structures on wafers, such as contact bumps, which are electrically connected to a bond pad on the wafer via a three-dimensional, mechanically flexible structure in the form of a redistribution layer, for subsequent electrical connection to a carrier element, e.g., a printed circuit board. The process is intended to considerably simplify the process sequence. The metallization of the previously prepared 3D structures on the wafer is carried out electrochemically, under current or potential control, by the structures being partially immersed in an electrolyte with a fixed surface. The electrolyte can be covered with a membrane which is permeable to the corresponding ions, or alternatively a gel electrolyte may be used.

Abstract: In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring films formed protrusively above tops of the first insulating film among the grooves, plural barrier films formed on bottoms of the wiring films and up to a position on sides of the wiring films higher than the tops of the first insulating film; first cap films comprising metal films formed on tops of the wiring films, and a second cap film formed on at least respective sides of the first cap films and the barrier films.

Abstract: The present invention provides methods of forming cobalt layers on a structure comprising forming a preliminary cobalt layer on a semiconductor substrate by introducing an organic metal precursor onto the semiconductor substrate and treating a surface of the preliminary cobalt layer under an atmosphere of a hydrogen-containing gas to remove impurities contained in the preliminary cobalt layer. Compositions of cobalt layers are also provided. Further provided are semiconductor devices comprising cobalt layers provided herein.

Abstract: Methods of depositing a tantalum-nitride (TaN) diffusion barrier region on low-k materials. The methods include forming a protective layer on the low-k material substrate by performing plasma-enhanced atomic layer deposition (PE-ALD) from tantalum-based precursor and a nitrogen plasma in a chamber. The protective layer has a nitrogen content greater than its tantalum content. A substantially stoichiometric tantalum-nitride layer is then formed by performing PE-ALD from the tantalum-based precursor and a plasma including hydrogen and nitrogen. The invention also includes the tantalum-nitride diffusion barrier region so formed. In one embodiment, the metal precursor includes tantalum penta-chloride (TaCl5). The invention generates a sharp interface between low-k materials and liner materials.

Abstract: Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate including depositing a metal nitride barrier layer on at least a portion of a substrate surface by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a nitrogen containing compound and depositing a metal barrier layer on at least a portion of the metal nitride barrier layer by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a reductant. A soak process may be performed on the substrate surface before deposition of the metal nitride barrier layer and/or metal barrier layer.

Abstract: Methods for depositing a ruthenium metal layer on a dielectric substrate are provided. The methods involve, for instance, exposing the dielectric substrate to an amine-containing compound, followed by exposing the substrate to a ruthenium precursor and an optional co-reactant such that the amine-containing compound facilitates the nucleation on the dielectric surface.

Abstract: A method of stacking dice in an electronic circuit includes controlling a size of a hole made in a connection pad on each die of said dice to selectively provide an electrical connection to a particular die in the stack. Additionally, a method of stacking dice in an electronic circuit includes forming holes in each of the dice, and providing electrical connection material selectively at some of the holes to provide for selective electrical connections among the dice. A stack of dice in an electronic circuit includes a number of dice stacked on top of each other, each die in the stack having one or more holes therein, conductive material extending through the holes and making electrical connection between one or more of the dice in the stack and the electronic circuit.

Abstract: In bit line cladding structure formation, stability and margin of the process are secured and further shrinking is achieved, and the magnetic memory device is improved in speed, reliability and yield. Method for manufacturing a magnetic memory device, comprising the steps of: forming a word line; forming a magnetoresistance effect memory element comprising a tunnel insulating layer disposed between a ferromagnetic material and being electrically insulated from the word line; forming an insulating film for covering the memory element; and forming a bit line so that it is buried in the insulating film wherein the bit line is electrically connected to the memory element and spatially crosses the word line through the memory element disposed therebetween, wherein the method has steps of removing the insulating film on the bit line side to expose the bit line and forming a soft magnetic material layer selectively only on the bit line surface.

Abstract: Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate. The seed layer is deposited to a thickness of less than 15 nanometers (nm). A photolithography technique is used to define a number of via holes above the seed layer. In one embodiment, using a photolithography technique includes forming a patterned photoresist layer to define the number of via holes above the seed layer. A layer of copper is deposited over the seed layer using electroless plating filling the number of via holes to a top surface of the patterned photoresist layer.

Abstract: Nitrogen doped titanium oxide coatings on a hot glass substrate are prepared by providing a uniform vaporized reactant mixture containing a titanium compound, a nitrogen compound and an oxygen-containing compound, and delivering the reactant mixture to the surface of a ribbon of hot glass, where the compounds react to form a nitrogen doped titanium oxide coating. The nitrogen doped titanium oxide coatings deposited in accordance with the invention demonstrate an increase in visible light absorption.

Abstract: A method for subjecting target substrates to a heat process under a vacuum pressure includes a transfer step, heating-up and pressure-reducing step, and heat-processing step. The transfer step is arranged to transfer into a reaction chamber a holder that supports the substrates at intervals. The heating-up and pressure-reducing step following the transfer step is arranged to heat up the reaction chamber to a process temperature, and exhaust the reaction chamber to a process pressure. During the heating-up and pressure-reducing step, the reaction chamber is set at the process pressure after being set at the process temperature, to form a state where the reaction chamber has the process temperature under a pressure higher than the process pressure. The heat-processing step following the heating-up and pressure-reducing step is arranged to subject the substrates to the heat process at the process temperature and process pressure.

Abstract: Methods of forming MOS transistors include forming lightly and heavily doped source/drain regions adjacent to one another in a substrate and a gate electrode with a sidewall spacer thereon. A salicide process is performed on a surface of the heavily doped source/drain region to provide a first suicide layer self-aligned to the sidewall spacer. At least a portion of the sidewall spacer is removed to expose a portion of the lightly doped source/drain region adjacent to the first silicide layer. A salicide process in performed on the exposed portion of the lightly doped source/drain region to provide a second silicide layer adjacent to the first suicide layer. Related devices are also disclosed.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

Abstract: A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

Abstract: A method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the wafer has a barrier layer over the wafer and a dielectric layer over the barrier layer. The dielectric layer is etched. The barrier layer is opened. The wafer is removed from the etch chamber. A waferless automatic cleaning of the etch chamber without the wafer is provided. The waferless automatic cleaning comprises providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.

Abstract: After an SiC film (4), an SiO2 film (5) and a silicon nitride film (6) are formed sequentially on an organic low dielectric constant film (3), by performing O2 plasma processing to a surface of the silicon nitride film (6), an oxide layer (7) is formed on the surface of the silicon nitride film (6). Then, a wiring trench pattern is formed on the silicon nitride film (6) and the oxide layer (7), and a resin layer (10) on which a via hole pattern is formed is formed. Subsequently, a portion of the oxide layer (7) exposed from the resin layer (10) is removed along with unnecessary particles.

Abstract: A method for fabricating a field effect transistor, in which, after the etching of the gate electrode, the removal of the etching mask is omitted since the etching mask serves as a gate dielectric. The etching mask or the dielectric has a self-assembled monolayer of an organic compound.

Abstract: A structure including at least one layer of germanium formed on a surface of a ceramic substrate is provided. The layer of germanium has a thickness of not larger than 10 microns and includes grains having grain size of at least 0.05 mm. A structure including at least one layer of germanium formed on a surface of a ceramic substrate and having at least one capping layer formed on a surface of the layer of germanium is also provided. In addition, a method of forming a thin film germanium structure is provided including forming at least one layer of germanium on a surface of a ceramic substrate, then forming at least one capping layer on a surface of the layer of germanium, followed by heating and then cooling the layer of germanium.

Abstract: The present invention provides a process for forming a silica-based coating film, characterized by heating a reaction mixture comprising a silicon compound (A) represented by Si (OR)4 and/or a silicon compound (B) represented by R1nSi (OR2)4?n (wherein n is an integer of from 1 to 3), an alcohol (C) represented by R3CH2OH and oxalic acid (D) in specific ratios, at a temperature of from 50 to 180° C. in the absence of water, to form a solution of a polysiloxane having a number average molecular weight, as calculated as polystyrene, of from 2,000 to 15,000, applying a coating fluid containing such a solution on a substrate surface, and thermally curing a coating film obtained by such coating, at a temperature of from 80 to 600° C., and such a coating film having a film thickness of from 0.5 to 5 ?m, a coating fluid to be used for such a coating film, and a process for producing such a coating fluid.

Abstract: A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substrate in a region not covered with the barrier layer by introducing pure dry oxygen, and performing a wet oxidation process to form a second field oxide adjacent the first field oxide by introducing hydrogen and oxygen. The method of the present invention can improve the quality and electrical property of the semiconductor device, increase the yield, and reduce the cost.

Abstract: The present invention relates to a method of forming an insulating film in a semiconductor device. After a mixed gas of alkyl silane gas and N2O gas is supplied into the deposition equipment, a radio frequency power including a short pulse wave for causing incomplete reaction upon a gas phase reaction is applied to generate nano particle. The nano particle is then reacted to oxygen radical to form the insulating film including a plurality of nano voids. A low-dielectric insulating film that can be applied to the nano technology even in the existing LECVD equipment is formed.

Abstract: Methods of filling gaps on semiconductor substrates with dielectric film are described. The methods reduce or eliminate sidewall deposition and top-hat formation. The methods also reduce or eliminate the need for etch steps during dielectric film deposition. The methods include treating a semiconductor substrate with a hydrogen plasma before depositing dielectric film on the substrate. In some embodiments, the hydrogen treatment is used is conjunction with a high rate deposition process.