Abstract: A resistive memory cell random access memory device and method for fabrication.

Abstract: Ferromagnetic materials for use with spin memory and logic devices include a geometry and composition adapted to increase spin injection efficiency and/or reduce fringe fields. The ferromagnetic materials can be oriented to implement a variable spin resistance. The ferromagnetic layers are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the “on” state the device has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic layers. An external magnetic field can change the magnetization state of the device by orienting the magnetization of the ferromagnetic layers to be parallel or antiparallel, thus changing the resistance of the device to a current of spin polarized electrons.

Abstract: A semiconductor memory device includes memory cells, a memory cell array, word lines, latch circuits, first row decoders, second row decoders, first isolating transistors, and second isolating transistors. The memory cell includes a memory cell transistor having a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects in common the control gates of the memory cell transistors in a same row. The first row decoder applies a positive voltage to the word lines in a write operation and in an erase operation. The second row decoder applies a negative voltage to the word lines in a write operation and in an erase operation. The first isolating transistor switches between the first row decoder and the word line. The second isolating transistor switches between the second row decoder and the word line.

Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

Abstract: The programming method of the present invention minimizes program disturb in a non-volatile memory device by initially programming a lower page of a memory block. The upper page of the memory block is then programmed.

Abstract: This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a plurality of gate structures for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate and electrically isolated therefrom; a plurality of wordlines, each of the gate structures being connected to one of the wordlines and a group of the gate structures being connected to a common wordline; and a plurality of active regions, each of the active regions being individually connectable to at least one of the gate structures.

Abstract: The invention considers a non-volatile semiconductor memory device comprising a first and second floating gate transistor, which are coupled in series. Each floating gate transistor comprises a floating gate. Programming means coupled to the first and second floating gate transistor are operable to place a selected electrical charge in one of the floating gates and less than the selected electrical charge in the other floating gate to represent either a first or second binary value.

Abstract: Provided is directed to a NAND flash memory device and a method of programming the same, which can improve integration of the device by removing a common source line connecting with a source line coupled to a plurality of cell blocks, control a voltage applied to a source line by each cell block, and rise a precharge level in a channel area by applying a pumping voltage to the source line relatively having low capacitance instead of a bitline having a large capacitance, and as a result of those, the NAND flash memory device can reduce disturbance, use a lower voltage than a power supply voltage on the bitline, which leads to reduce a current consumption.

Abstract: The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly reduces and overall system performance increases. Architectural features include the ability to selectively transfer individual data sectors of a page between on-chip registers and the ability to realign data sectors within a register.

Abstract: In a nonvolatile semiconductor memory device, the increase of the capacity of a nonvolatile semiconductor memory inevitably causes the power supply circuits including the charge pump circuits at the periphery to increase. In view of the above situation, the object of the present invention is to provide a technology of allowing a nonvolatile semiconductor memory to increase the capacity without increasing the power supply circuits which are the peripheral circuits of the nonvolatile semiconductor memory.

Abstract: The present invention relates to a structure for directly burning a program into a motherboard comprising a burning plate having a series connected first transistor set, a resistor, a comparator and a series connected second transistor set mounted thereon, wherein the first transistor set, the resistor, and comparator are series connected, two input terminals of the first transistor set and an output terminal of the comparator are electrically connected to a burner, an output terminal of the first transistor set is coupled to a serial data pin of a memory on the motherboard, an input terminal of the second transistor set is electrically connected to the burner, and an output terminal of the second transistor set is coupled to a serial clock pin of the memory for directly burning the program into the memory and checking the program burned therein.

Abstract: A non-volatile memory in which a plurality of memory cells connected to a same word line are entirely written with data. Source lines SL separated from each other in column units is arranged on each memory cell of a memory cell array. When writing data, one of either a first or a second source voltage is applied to each source line in accordance with data that is to be written. After a first control voltage of negative voltage is applied, a second control voltage of high voltage is applied to the word line with the voltage of each source line SL in a maintained state. Therefore, each memory cell is erased or programmed in accordance with the voltage applied to the respective source line.

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract: A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.

Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.

Abstract: A flash memory device, such as a NAND flash, having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells, the voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block.

Abstract: A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the robustness of the design when used in a TMR mode of operation. Various addressing schemes are provided, which allow dual use of the configuration data lines as selection signals using one addressing scheme, while allowing for dual use of the configuration address lines as selection signals using the second addressing scheme.

Abstract: There is provided a data output device for stably operating in a high frequency circumstance. The data output device includes a selection unit for receiving a second address information signal to directly output or inversely output the received signal as a third address information signal in response to a first address information signal; a pipe output control unit for generating a plurality of pipe output control signals; a plurality of pipe latch units for storing a global data in response to a pipe input control signal and aligning the stored data in response to the first to the third address information signals, thereby outputting the aligned data synchronized by the pipe output control signals; and a data driving unit for outputting the aligned data as an external data in response to a first and a second DLL output clock.

Abstract: Disclosed is a non-volatile ferroelectric memory device having differential data, the device including: a plurality of cell array block groups having a hierarchy bit line structure and storing differential data; a common data bus being shared by a plurality of the cell array block groups, and transferring sensing voltages induced by the differential data; a column selection control unit selectively applying to the common data bus the induced sensing voltages of two main bit lines of the cell array block group according to the differential data; and a sense amp unit receiving the sensing voltages through the common data bus, comparing two sensing voltages induced by the differential data, and sensing the cell data. Therefore, the non-volatile ferroelectric memory device of the invention is capable of sensing a cell data more stably, independent of external factors and the state of a cell, by simultaneously sensing the stored data (differential data) in two unit cells and detecting the cell data.

Abstract: A column selection signal generator of a semiconductor memory device is configured to maintain a predetermined pulse width of a column selection signal regardless of change in process and external conditions by selectively using a self-generated pulse signal and a pulse signal generated by an external clock signal. The column selection signal generator includes a command combination unit, a pulse generating unit, a comparison unit and a selection unit.

Abstract: Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.

Abstract: A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines.

Abstract: A column decoder in a semiconductor memory device in which address setting cannot be performed but only a serial access can be performed. The column decoder is constructed by: a redundant fuse for generating a redundant fuse signal; a column decoding circuit for decoding a column address; a column decoding switching circuit for switching an output destination of a decoding result of the column decoding circuit by the redundant fuse signal; and a column driver for driving an output signal of the column decoding switching circuit and generating it to normal column lines and a redundant column line. The column decoding circuit continuously makes the redundant column line operative after the operation of the normal column lines.

Abstract: An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as rows or columns, in parallel. Memory is dynamically reprogrammed in order to remap unused spare memory elements for failed memory elements when errors are detected. Unused spare memory elements are remapped utilizing a circuit that overrides unblown fuses or antifuses.

Abstract: Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met which does not allow time for precharging a second word line.

Abstract: A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier input in response to a column enable signal. A multiplexer output conditioner discharges the sense amplifier input and a bitline conditioner precharges and readjusts the selected bitline to a precharge threshold. A sense amplifier produces a data output that is based on the sense amplifier input.

Abstract: A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

Abstract: A method and circuitry for boosting a driven signal along a circuit line so as to reduce RC delays is disclosed. In one embodiment, the circuitry includes a line amplifier positioned at a distance from the circuitry that drives signals onto the line, for example, across a memory array. The line amplifier detects the driven signal on the line at early stages, and even before the signal reaches its full potential, the amplifier amplifies that signal and drives it back to the line to help boost the detected signal. In a preferred embodiment, the amplifier comprises a differential amplifier capable of boosting one of two input signal lines. In an alternative embodiment, the amplifier output may additionally input to a feedback loop, which loop ultimately drives a pull-up transistor to boost the detected signal and passes it back to the line to even further assist the differential amplifier in boosting.

Abstract: A memory device conducts a stable data access operation by removing glitch component in an internal clock outputted after a completion of self-refresh. This memory device includes a memory core region, a clock enable sensor for sensing an enable of a clock enable signal corresponding to a termination of a self-refresh operation to provide a sensing signal, a clock buffer for buffering a clock signal from the outside as an internal clock signal in response to the sensing signal and providing the internal clock signal to the memory core region, and a self-refresh control circuit for preventing a glitch component in the internal clock signal firstly outputted by the clock buffer in response to the sensing signal from transferring to the memory core region.

Abstract: Techniques for reducing leakage power in the transistors of integrated circuits are provided. Suppressing sub-threshold leakage techniques can be applied to memory cells that drive the gates of the transistors, memory cells that drive the sources of the transistors, and level shifters that drive the gates of the transistors. In these techniques, an appropriate gate to source voltage (VGS) can be applied to a transistor in its off state. Of importance, this VGS can under-drive the transistor, which significantly reduces the sub-threshold leakage of that transistor. These techniques fail to affect a transistor in its on state, thereby ensuring that high speed performance of the integrated circuit can be maintained.

Abstract: A system and method of providing a voltage to a non-volatile memory. The system includes an output pin to provide an output voltage to a non-volatile memory and includes a memory to store a table. The table includes a plurality of operating voltage levels. The system further includes a voltage mode module to apply a first voltage at a first of the plurality of operating voltage levels at the output pin prior to a read operation on the non-volatile memory. The voltage mode module applies a second voltage at a second of the plurality of voltage levels at the output pin in response to a read operation that returns a failure condition.

Abstract: A semiconductor memory device includes: a plurality of memory cells arranged in a matrix; a memory cell array divided into a plurality of blocks; a plurality of read amplifiers, each of which is coupled correspondingly to each of the blocks; and a plurality of latch circuits, each group of which is coupled correspondingly to each of the read amplifiers and includes two or more latch circuits coupled to one another in parallel, wherein, in order to read a plurality of data consecutively from the memory cell array, the data are firstly read from one desired memory cell for each block; the read data are secondly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits included in a group of latch circuits corresponding to the same read amplifier; the data are thirdly read from another desired memory cell, which is different from the memory cell from which the data are formerly read, for each block; the read data are fourthly inputted and latched, via the read amp

Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

Abstract: A method and apparatus for producing an amplitude value for use in controlling illumination of a pixel on a display, in response to a sampled sonar signal produced by an element of a sonar array. A pixel time associated with the pixel is found, the pixel time representing a time required for sound to travel a distance represented by the pixel, according to a range of distance to be viewed on the display. A sample point of the sampled sonar signal is then found, the sample point having a sample time nearest the pixel time. A delay value associated with the pixel is then found, the delay value including an array element delay value. A representation of a synthesized waveform is then produced, in response to the sonar signal, the representation comprising a plurality of sample points coinciding in time with the sample points of the sonar signal.

Abstract: Described herein is sonar localization apparatus which comprises a plurality of acoustic transducers (6) arranged to define at least two end fire arrays (2, 4) each of which produces a sonar beam (10, 12) suitable for the detection of objects in the near field.

Abstract: Disclosed is a method for automatically detecting and selecting a time correction protocol and a time base, from among many possible protocols, in a master/slave clock system. A “self-teaching” feature is also disclosed, which includes a table stored at the slave clock containing data representative of characteristics, such as the relative frequency and spacing, of each one of numerous different time correction pulses that can be received by the slave clock from the master clock. Then, at a time of time correction, the slave clock selects the protocol most likely being used by the master clock, based on historical data. The time displayed by the slave clock is the then updated to match the time displayed by the master clock.

Abstract: There is provided a mixing recorder which enables the user to readily produce music using overdubbing and/or other recording techniques while suppressing degradation of sound quality to the minimum and enables the user to easily find out his/her desired mixing result from a large number of mixing results obtained in the process of mixing. An audio signal is input, and a source file is read out from a memory card and an audio signal is reproduced based on the source file. The input audio signal and the reproduced audio signal are mixed into a mixed signal, which is then stored as a new source file in the memory card. The source file stored in advance in the memory card is backed up before the new source file is stored in the memory card, and in the back-up, the source file is automatically backed up by generating a file given a new name associated with a name of a source file to be backed up and having the same contents as the contents of the source file.

Abstract: An accessor moveably disposed within a data storage and retrieval system, where that accessor includes an information input/output device and a power supply connector disposed on a gripper mechanism such that the information input/output device and the power supply connector can be releaseably coupled/connected to an information input/output port and a power port, respectively, disposed on a hard disk drive unit disposed in a storage slot within the data storage and retrieval system. A data storage and retrieval system which includes one or more of Applicants' accessors, one or more hard disk disposed in one or more hard disk drive units each of which includes an information input/output port in communication with that hard disk, and an information transfer station in communication with a host computer, wherein that information transfer station can communicate with Applicants' accessor(s).

Abstract: A method is for simultaneously operating the tray of an optical disk system and the front panel of the computer cabinet wherein the optical disk system is housed. In the method, the tray of the optical disk system is ejected immediately after the front panel of the computer case is completely opened when a tray operation instruction is issued and the front panel is currently at a close state. Additionally, the tray is retracted into the optical disk system before the front panel of the computer case is closed when a tray operation instruction is issued again and the front panel is currently at an open state so that the optical disk system may been closed inside a computer cabinet of the computer including HI-FI stereo. In the embodiment, the tray operation instruction is delivered via an output pin of the computer including HI-FI stereo and one of the reserved output pin of the optical disk system.

Abstract: A focus jump technique enables focus control on recording layers of a disc in such a manner that its effect is not absorbed by disturbance or a variation in the movement speed of an objective lens. The technique involves monitoring level of a focus error signal and rejecting noise from the error signal. A speed sensor detects movement speed of an objective lens; and a speed control circuit generates a voltage for controlling the objective lens, based on the detected movement speed. Movement speed of the objective lens is detected during focus jump, a corresponding lens drive signal is generated, and an end position is determined from behavior of the error signal immediately before the end of the jump. A focus control is pulled, from a focus point corresponding to one recording layer, into a focus point corresponding to another recording layer forcibly in a stable manner.

Abstract: A method and device are provided for adjusting a focus bias of an objective lens of an optical pickup for an optical disc using a level of a tracking error signal. The level of the tracking error signal outputted when the optical disc is rotated and driven is detected for a predetermined period of time. An operation of adjusting the focus bias of the objective lens is carried out on the basis of the detected level of the tracking error signal. A focus bias adjustment value is set as an optimum focus bias value at a time when the detected level of the tracking error signal is maximized. In accordance with the method, a period of time for adjusting the focus bias is very short, on the order of “0” to several hundred milliseconds, in comparison with periods of time for adjusting the focus bias in conventional methods, such that the focus bias can be quickly adjusted.

Abstract: An apparatus for scanning a track on a record carrier has a head (22) and front end circuitry (31) for scanning the track and generating scanning signals. A detection unit (32) detects anomalies in the scanning signal, for example for adjusting a tracking servo. The detection unit (32) calculates a mean value of the scanning signal and compares the mean value to a threshold for providing an anomaly detection signal (33). Further a classification unit (34) provides an indication of the type of defect for determining a suitable responsive or corrective action.

Abstract: In the tilt correction method, information about inclination of an object lens relative to an information recording medium is acquired. A direct current signal Sdc for correcting the inclination is produced based on the information. An alternating current signal Sac having a prescribed signal characteristic is superposed onto the direct current signal Sdc to produce a driving signal Sout. The driving signal Sout is supplied to a driving mechanism to correct the inclination of the object lens against friction.

Abstract: A data demodulation process rate is varied according to a reproduction state, thereby reducing power consumption while maintaining a reading performance in a favorable state. A channel rate process data demodulation device performs a data demodulation process by employing channel bit frequency. Further, a half rate process data demodulation device performs a data demodulation process by employing frequency half as high as the channel bit frequency. These devices demodulate digital data from an optical recording medium. A process rate switching device switches a process rate at data demodulation, whereby demodulation is performed by switching between the data demodulation devices according to a quality of a reproduction signal, so as to reproduce the digital data recorded on the optical recording medium.

Abstract: In an optical recording/reproducing apparatus of the present invention, a semiconductor laser driver supplies a selected one of a plurality of drive currents, including at least a first-level drive current and a second-level drive current, to a semiconductor laser to control the emission of a laser beam by the laser. A current driver selectively outputs one of a plurality of increment currents to the laser driver in response to control signals, the plurality of increment currents including a first increment current supplied to the laser driver during an automatic power control process and a second increment current supplied to the laser driver during a special power setting process.

Abstract: A data assurance method controls an optical head according to the difference between the device temperature and the temperature of inserted removable optical storage media. A rate of temperature change c is calculated from the output of a temperature sensor which detects the device temperature, and then the temperature of the media is estimated. A transition is made to special processing, and a return is made from special processing in a state with a temperature difference to normal processing depending on the rate of temperature change. Consequently a return to normal processing can be made safely and quickly.

Abstract: An apparatus of detecting defects on an optical recording medium includes a defect signal generating circuit for generating a corresponding defect signal according to a surface defect of the optical recording medium, a first synchronous signal generator for generating a first synchronous signal, a defect signal locating circuit, a delay signal generating circuit, and an OR gate. The defect signal includes at least one pulse, whose width corresponds to the physical width of a surface defect. The delay signal generating circuit generates a delay signal corresponding to each pulse when the spacing between two adjacent pulses is smaller than a preset value. An OR operation is performed to the delay signal and the defect signal to obtain a defect extension signal. The first synchronous signal and a second synchronous signal for separating data recording sectors of the optical recording medium are employed to detect widths and addresses of surface defects.

Abstract: An information recording medium is provided, which comprises a plurality of recording layers and a first disc information area for storing parameters relating to access to the plurality of recording layers and formats relating to the plurality of recording layer. The first disc information area is provided in a first recording layer that is one of the plurality of recording layers.

Abstract: A method and device for searching a recording medium are provided. The recording medium has a management information area of which location information is overlapped with that of a program area. The method for determining an area on a recording medium having an overlapped time range between two areas reads a time address from a current position on the recording medium, obtains additional information from the recording medium or from a recording medium driving unit, if the read time address belongs to the overlapped range, and determines, based on the obtained additional information, to which one the areas the current position belongs. Therefore, it prevents wrong track jumps that are caused from time-overlapped areas on a capacity-expanded recording medium.

Abstract: A method and apparatus to dynamically adjust the amplitude of a signal comprising information read from an information storage medium. The method first forms (N) digital signals comprising information read from an information storage medium. The method provides a first signal comprising information read an information storage medium, wherein that first signal is one of the (N) digital signals. The method provides a first gain level, and calculates a first gain adjusted signal comprising the multiplication product of the first signal and the first gain level. To dynamically adjust that gain level, Applicants' method determines a gain error. Using that gain error, Applicants' method then calculates a second gain level by multiplying the gain error times a multiplier coefficient, and adding that multiplication product to the first gain level.