Abstract: An electronic test system load board electromagnetic shield is presented. The load board electromagnetic shield may have a DUT docking plate having a periphery rim on a first side with an aperture extending through the docking plate that has a waveguide chimney through which a DUT may be inserted into a socket or contactor on the load board.

Abstract: An adjusting device for a chip adapter. The adjusting device comprises a main body having a plurality of adjusting holes into which testing pins of the adapter are inserted and a slider disposed on the main body and sliding perpendicular to the top surface thereof for easy removal the chip adapter without mis-alignment of testing pins.

Abstract: Wafer test equipment includes a probe station having a wafer chuck for supporting a wafer, a test head disposed on the probe station, a manipulator for moving the test head to and from an upper surface of the probe station, and an alignment monitoring member for monitoring an alignment of the test head docked to the probe station.

Abstract: An assembly that includes a target component mounted for rotation about an axis, a sensor mounted adjacent the inner member and directed toward the inner member to measure the rotational speed of the target component and an outer component interposed between the sensor and the target component. Low magnetic permeability of the outer component is assured by appropriate selection of the material, maintaining the concentration of martensite in the outer component below a reference concentration as indicated by certain reference indices such as the Instability Function, and/or by maintaining the temperature at which a stamping operation is performed on the inner member above a pre-determined temperature.

Abstract: A plurality of Hall ICs 34A, 34B are disposed around a magnetic rod 32 that is movable along a central axis. The Hall ICs are disposed in different positions in terms of both a straight line distance coordinate in the direction of the central axis and a rotational angle coordinate around the central axis. The amount of displacement of the magnetic rod 32 is calculated based on the average of output signals from the Hall ICs. Errors in the output signals due to a shift and tilt of the magnetic rod are detected and calibration of the measurement method is carried out.

Abstract: A rotation angle detecting device includes magnetic field forming members such as a permanent magnet and a yoke, a plurality of magnetic sensors disposed in the magnetic field to rotate relative to the magnetic field forming members to provide output signals that are 90 degrees in phase different from each other, a judgment level calculating circuit that provides a judgment level based on the output signals and judging circuit that judges the output signals normal if the judgment level is within a prescribed range and not normal if the judgment level is out of the prescribed range.

Abstract: A pressure vessel penetration sidewall adjacent a tube installed in the penetration by a clearance fit is inspected by passing an eddy current probe having a pair of circumferential coils through the tube. Eddy currents are induced in the pressure vessel as the probe passes through the penetration tube and degradation of the pressure vessel adjacent the clearance is determined based upon the eddy currents induced in the pressure vessel by the probe.

Abstract: A apparatus for pipeline integrity monitoring comprising a magnetically permeable backing bar and at least three magnets comprising a relatively medium-strength magnet positioned at one end of the backing bar, a relatively low-strength magnet positioned at the other end of the backing bar, and a relative high-strength magnet positioned between the medium-strength and the low-strength magnet. The at least three magnets are adapted and positioned to induce a plurality of resultant fields within the pipeline wall comprising a first resultant field suitable for detecting a reduced metal-related anomaly and a second resultant field suitable for detecting a mechanically worked-related anomaly. Preferably, the first resultant field has a strength greater than 120 Oersted and the second resultant field has a strength between 40 and 80 Oersted.

Abstract: A method of manufacturing a thin film magnetic sensor comprising: forming a projection on a surface of an insulating substrate formed of an insulating nonmagnetic material by removing an unnecessary portion of the insulating substrate from a surface region thereof or by depositing a thin film formed of an insulating nonmagnetic material on the surface of the insulating substrate; forming a pair of thin film yokes positioned to face each other with the projection interposed therebetween and completely electrically separated from each other, the thin film yokes being formed by depositing a thin film formed of a soft magnetic material on the surface of the insulating substrate having the projection formed thereon, followed by partially removing the thin film formed of the soft magnetic material until at least a tip surface of the projection is exposed to the outside; and depositing a GMR film having an electrical resistivity higher than that of the soft magnetic material on the tip surface of the projection and

Abstract: Nuclear magnetic resonance (NMR) signals are detected in microtesla fields. Prepolarization in millitesla fields is followed by detection with an untuned dc superconducting quantum interference device (SQUID) magnetometer. Because the sensitivity of the SQUID is frequency independent, both signal-to-noise ratio (SNR) and spectral resolution are enhanced by detecting the NMR signal in extremely low magnetic fields, where the NMR lines become very narrow even for grossly inhomogeneous measurement fields. MRI in ultralow magnetic field is based on the NMR at ultralow fields. Gradient magnetic fields are applied, and images are constructed from the detected NMR signals.

Abstract: An apparatus for exciting and detecting NQR in a substance containing quadrupole nuclei responsive to the NQR phenomenon. The apparatus includes a coil 15 for irradiating an item that may contain a substance with RF waves to excite NQR in quadrupole nuclei within the substance and for receiving an NQR signal emitted in response thereto. A transmitter unit 10 is provided for producing and transmitting an RF pulse to the probe to create said RF waves. A receiver unit 11 is provided to receive and treat a received signal from said probe for subsequent processing and detection of a said NQR signal therein. A sensing means is included in the apparatus for sensing an extraneous parameter that may influence the detection of the NQR signal from the item to be scanned.

Abstract: A magnetic resonance imaging apparatus of the invention comprises a static magnetic field generation unit which generates a static magnetic field in a gantry, a gradient magnetic field generation unit which applies a gradient magnetic field to a object in the static magnetic field, a radio frequency coil which receives a magnetic resonance signal from the object to which the gradient magnetic field is applied, a contour detection unit which detects a contour of the object, a coil movement unit which moves the radio frequency coil on the basis of the detected contour while the radio frequency coil is placed near and far relative to the object, and an image generation unit which generates a magnetic resonance image on the basis of the received magnetic resonance signal.

Abstract: An apparatus for producing a corrected reconstructed image from magnetic resonance imaging data acquired by a magnetic resonance imaging scanner (10) includes a reconstruction processor (44) that reconstructs a corrected reconstructed image from acquired magnetic resonance imaging data. A parameters calculation processor (52) determines at least one characteristic of the imaging subject. A correction pattern adjustment processor (54) selects a correction pattern from a family of stored correction patterns based on the at least one characteristic. An image correction processor (56) corrects the uncorrected reconstructed image using the selected correction pattern to produce the corrected reconstructed image.

Abstract: A magnetic resonance imaging apparatus includes: a sensitivity map database that stores sensitivity map data of a multi-coil including plural coils necessary for parallel imaging unfolding processing; a data slicing unit that slices partial data from three-dimensional volume data collected for the respective coils by parallel imaging, respectively; an intermediate image reconstructing unit that executes reconstruction processing for the partial data to thereby reconstruct intermediate images for the respective coils; and a reference image generating unit that slices sensitivity map data corresponding to the intermediate images from the sensitivity map database as sensitivity map data for unfolding processing, executes the parallel imaging unfolding processing for the intermediate images using the sensitivity map data for unfolding processing, and generates reference images.

Abstract: In a method for generation of magnetic resonance exposures and a control device for a magnetic resonance tomography apparatus, a number of coils are available in the apparatus, the coils being are positioned at various locations relative to the examination subject. Initially a radio-frequency signal is emitted and a spatially-resolved signal intensity distribution is measured with at least one or some of the available coils. An automatic determination of a three-dimensional exposure profile of the appertaining coils is made based on the received signals. A selection of one or more of the appertaining coils for a subsequent magnetic resonance measurement is made on the basis of the determined exposure profiles of the coils as well as the measurement region to be acquired in the magnetic resonance measurement.

Abstract: A method and a system for acquiring diffusion magnetic resonance images with compensation of the effects of eddy currents induced by the diffusion weighting (DW) gradient pulses. Prescan data are first acquired using the same DW sequence to be used for imaging. The prescan data are used to obtain eddy current parameters that model the effects of DW-induced eddy currents under the exact conditions under which DW images are to be acquired. The DW imaging sequence is then slightly modified according to the eddy current parameters and used to acquire DW image data with the effects of DW-induced eddy currents compensated.

Abstract: This invention concerns a new embodiment of the instrument to measure nuclear polarization described in U.S. Pat. No. 6,356,080. The coil, that couples the nuclear polarized substance to the electronics, has been designed not to pick up ambient electromagnetic noise. The output from the low level oscillator is passed through a Schmidt trigger to reduce noise. A local oscillator beats with the output of the low level oscillator to provide an audible output. The instrument is automated, using a microprocessor with a customized downloaded program, to control the operation of the instrument and to output the results of measurement to a liquid crystal display and, if desired, to an external computer. This computer is not necessary and the instrument can act as a stand alone.

Abstract: A combined magnetic resonance (MR) imaging and positron emission tomography (PET) system is provided. In one embodiment, a system is provided comprising a radiofrequency (RF) antenna and an RF screen spaced apart from one another to create an RF field reflux zone. The RF screen comprises a plurality of openings, and a plurality of a scintillator crystals are positioned in the plurality of openings in the RF screen such that at least a portion of the plurality of scintillator crystals are positioned in the RF field reflux zone. Other embodiments are provided, and each of the embodiments described herein can be used alone or in combination with one another.

Abstract: In a magnetic resonance system and an operating method therefor, a B1 field distribution of a radio-frequency antenna is measured in at least one part of a examination volume of the magnetic resonance system, and then the RF pulses emitted by the radio-frequency antenna are optimized, based on the determined B1 field distribution, for homogenization in a specific volume. An effective volume within the examination volume is determined beforehand for each applied RF pulse and, based on the determined B1 field distribution, the appertaining RF pulse is individually adjusted such that the B1 field is homogenized within the effective volume of the RF pulse.

Abstract: In a shimming method for an irregular object to be examined by magnetic resonant equipment magnetic field parameters are measured at measurement points located on the surface of an irregular object to be examined. Based on the measured magnetic field parameters, the positions and number of shims for adjusting magnetic field homogeneity are calculated when a passive shimming is to be performed, or the current value in a shimming coil are calculated when an active shimming is to be performed, or at the same time both the positions and number of shims and current value in the shimming coil are calculated when active shimming and passive shimming are to be performed at the same time. Shimming is then performed according to the calculated results. These above steps are repeated until achieving required magnetic field homogeneity.

Abstract: An NMR apparatus which includes an NMR probe coil of a superconductor made of magnesium 2-boride formed on the surface of a substrate made of a flexible organic polymer material.

Abstract: Tracking a boring tool is performed within an underground region using a locating signal. The boring tool is moved through the ground during a series of distance movements such that potential movement of the boring tool during any one of the distance movements is less than a maximum movement value. A current positional relationship is determined for a current one of the distance movements based on: a last-determined positional relationship established for an immediately preceding one of the distance movements, certain orientation parameters, the maximum movement value and the determined signal strength of the locating signal in the current positional relationship. Target coordinates are accepted and a target position, based on the target coordinates, is included as part of the current positional relationship. The position of the target is unconstrained with respect to system geometry. Steering command features are provided along with steering warnings.

Abstract: An improved hand held starting/charging system tester. According to one aspect of the present invention, the portable handheld tester includes a connector to which various test cables can be removably connected to the tester. Detection circuitry within the tester determines which of several types of test cable is connected to the tester before testing. According to another aspect of the present invention, the portable handheld tester includes an improved user interface that permits a user to review test data from previously performed tests and further permits a user to either skip a previously performed test (thereby retaining the previously collected data for that test) or re-do the test (thereby collecting new data for that test). According to yet another aspect of the present invention, the portable handheld tester that performs a more complete set of tests of the starting/charging system.

Abstract: A method for monitoring the condition of a battery of a marine propulsion system provides the measuring of a voltage characteristic of the battery, comparing the voltage characteristic to a preselected threshold value, and evaluating the condition of the battery as a function of the relative magnitudes of the voltage characteristic and the threshold value. The voltage characteristic of the battery is measured subsequent to a connection event when a connection relationship between the battery and an electrical load is changed. The electrical load is typically a starter motor which is connected in torque transmitting relation with an internal combustion engine. The voltage characteristic is preferably measured at its minimum value during the inrush current episode immediately prior to cranking the internal combustion engine shaft to start the engine.

Abstract: A method for testing an electronic assembly (10) is provided. A portion (22) of the electronic assembly is electrically isolated from a remainder (24) of the electronic assembly. Power is provided to the electronic assembly such that a reduced amount of current flows only through the portion of the electronic assembly. The reduced amount of current is determined. A combined amount of current flowing through both the portion and the remainder of the electronic assembly when power is provided to both the portion and the remainder of the electronic assembly is calculated based on the reduced amount of current.

Abstract: Various component parts of a driver circuit for drive sources such as electric motors and clutches, such as relays and FETs as well as the drive sources can be tested by selectively energizing the relays and evaluating the voltage levels of the selected points by using the first and second test voltage detection circuits. This testing process is typically executed before the power up of the drive circuit. The test current is so small that the drive sources would not be inadvertently activated and various components would not be damaged even when there is any faulty component in the driver circuit. When any faulty component is detected in the testing process, the driver circuit may be prevented from being powered up so that any undesired operation of the drive sources or permanent damage to various components owing to such a faulty component may be avoided.

Abstract: An apparatus selectively generates a disturbance in a three-phase supply voltage provided to a load. The apparatus includes input connections for receiving a first phase voltage, a second phase voltage and a third phase voltage of the three-phase supply voltage. The apparatus includes a voltage disturbance generator for selectively adjusting the amplitudes of the first, second and third phase voltages according to a first test method, a second test method or a third test method. Output connections are provided for connecting to the load to provide the load the first, second and third phase voltages as altered according to the first, second or third test method. In the first test method, a phase-to-phase voltage disturbance is introduced between the first and second phase voltages by altering the amplitude of the first phase voltage against the second phase voltage.

Abstract: The present invention is a detection device, system and method for detecting an external electromagnetic event such as lightning or a high intensity radiated field. In an exemplary embodiment, the detection device includes a free space capacitive sensor and a protected amplifier circuit coupled with the free space capacitive sensor. The free space capacitive sensor and the protected amplifier circuit are configured to respond to a voltage waveform produced by an external electromagnetic event. The free space capacitive sensor serves as a single input capable of detecting the external electromagnetic event and the coupling of the free space capacitive sensor to the protected amplifier circuit allows subsystems in communication with the sensor and amplifier circuit to generate a coordinated response to the detected external electromagnetic event.

Abstract: One type of capacitive sensing apparatus has a sensing element that includes a first portion and a second portion adjacent opposite edges of a sensing region. Signals from the first and second portions are combined. Another type of apparatus includes: a first sensing element including first and second portions; a second sensing element including third and fourth portions; and a third sensing element including fifth and sixth portions. The first, third and fifth portions form a first pattern, and the second, fourth and sixth portions form a second pattern. The patterns are bilaterally symmetrical about a median of a sensing region. In another type of apparatus, an electrical conductor coupled to a first sensing element passes through a gap in a second sensing element. An electrical conductor coupled to the second sensing element is dimensioned such that a capacitive coupling to the second sensing element is compensated for the gap.

Abstract: A method and apparatus for determining a voltage, such as a bias voltage, supplied by an integrated circuit. A nominal terminating resistor is connected across a first and a second input/output pads from which the voltage is supplied. The voltage is measured across third and fourth pads connected, respectively, to the first and second pads. In an alternative embodiment the functionality of the third and the fourth pads is multiplexed between chip operational circuitry unrelated to the voltage to be measured and a connection to the first and second pads for measuring the voltage.

Abstract: An apparatus for measuring a sample with a circuit pattern including at least a porous low-permittivity hydrogensilsesquioxane material or a material structurally or compositionally similar to the porous low-permittivity hydrogensilsesquioxane. The apparatus includes an electron beam optics unit which enables scanning of a primary electron beam onto the sample, a detector which detects a secondary electron or a reflected electron, an image processing unit which measures a desired portion of the sample irradiated with the primary electron beam based on an output signal of the detector, and a control unit which controls the irradiation energy and density of the primary electron beam onto the sample.

Abstract: An electronic device is moved into a first position such that terminals of the electronic device are adjacent probes for making electrical contact with the terminals. The electronic device is then moved horizontally or diagonally such that the terminals contact the probes. Test data are then communicated to and from the electronic device through the probes.

Abstract: A probe apparatus includes a nest element operable to precisely locate a chip having a plurality of exposed interconnects on a face of the chip to permit conductive connection to the chip through the interconnects. The nest element includes a pocket dimensioned to locate the chip within a tolerance of less than a width of one of the interconnects, and tapered walls extending upwardly and outwardly from the pocket, the tapered walls adapted to guide the chip into the pocket. One or more piezoelectric elements can be attached to or provided within to the nest element to impart vibration to the nest element, causing the chip to be “fluidized” such that the chip is guided into the pocket under the force of gravity or other externally applied force.

Abstract: A system, apparatus and method for controlling temperature of an integrated circuit in a chip tester is disclosed. Embodiments include supplying a chilled fluid to a cold plate at a first flowrate, where the first flowrate is associated with a first valve setting based on at least a desired temperature setpoint and an applied power. Embodiments may determine a change in applied power and modify the chilled fluid flowrate in response to a change in testing conditions to a second flowrate associated with a second valve setting associated with at least the desired temperature setpoint and the changed testing conditions. This feed forward loop may be supplemented by a feedback loop that includes modifying the energy supplied to a cold plate heater in response to a comparison of a current temperature and the temperature setpoint. The valve may be a proportional control valve or the like.

Abstract: A probe card for production testing of semiconductor imaging die includes a stiffener supported on a bottom side of the probe card. The top of the stiffener is substantially flush with a top surface of the probe card. A light passage through the stiffener features non-reflective surfaces. Surfaces surrounding the light passage are arranged to avoid casting any shadows on the imaging die being tested. The arrangement provides a low profile probe card. A source of light used to illuminate the imaging die through the light passage can be placed close to the imaging device under test, providing few false negatives and more consistent results from wafer to wafer.

Abstract: An inspection probe comprises resilient probe pins having electric contacts disposed in positions corresponding to electrodes of an external terminal of a semiconductor device, a base substrate including pitch-expansion wiring layers of the probe pins, and a backup substrate, the base substrate, and a flexible substrate, wherein at least one precious metal layer is disposed at the tip of the probe pins on the side having the electric contact for contacting the electrodes of the semiconductor device to be inspected, at least one metal layer is disposed on the probe pins and the pitch-expansion wiring layers, the precious metal layer and the metal layer are composed of the same material or composed of different materials, and a roughness pattern comprising fine marks is provided on the surfaces of the probe pins on the side having the electric contacts for contacting the electrodes of the semiconductor device to be inspected.

Abstract: Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: Methods and apparatus for testing programmable integrated circuits are provided. Programmable integrated circuits include programmable elements that are loaded with configuration data to program programmable logic to perform a custom logic function. The programmable integrated circuits receive test configuration data from a tester to program the programmable logic into a test configuration. After the programmable integrated circuit has been placed into the test configuration by loading the test configuration data, test vectors are applied to the programmable integrated circuit to evaluate its performance. Test configuration data loading circuits are used in the programmable integrated circuits to control how the test configuration data is loaded into the programmable elements. When the adjustable circuits are placed in a low bandwidth configuration, relatively few input lines are used to load the test configuration data.

Abstract: An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

Abstract: To provide a transmission circuit which can adequately perform a fast data transmission even to a receiving circuit of a host controller or a device controller with a low sensitivity. A transmission circuit transmitting a signal through first and second signal lines that form a differential pair and includes a first terminating resistor terminating the first signal line, a second terminating resistor terminating the second signal line and a terminating resistance control circuit generating a control signal for controlling terminating resistance values of the first terminating resistor and the second terminating resistor. A first resistor takes a first resistance value if a first control signal is active, a nth resistor takes a nth resistance value if a nth control signal is active, the first-nth resistors are coupled, one end of the coupled first-nth resistors is coupled to a reference potential and the other end is coupled to the first signal line or the second signal line.

Abstract: Method and apparatus for dynamic configuration of function block logic of an integrated circuit is described. The integrated circuit includes a reconfiguration port coupled to a controller. The controller is coupled to an array of memory cell. A portion of the array of memory cells is coupled for read/write communication with the controller, and another portion of the array of memory cells is not coupled for read/write communication with the controller. The portion of the array of memory cells is configurable at an operational frequency of the integrated circuit for dynamic reconfiguration of the function block logic of the integrated circuit.

Abstract: A circuit and a method for operating the circuit are disclosed. A first step of the method generally comprises generating a plurality of first intermediate signals in two parallel first operations each responsive to a respective half of a plurality of input signals. A second step involves generating a plurality of result signals in a plurality of first logical operations each responsive to at most two of the first intermediate signals. A third step includes generating a first output signal as a particular one of the result signals, wherein a first delay from the first intermediate signals to the first output signal is at most through one logical gate. A fourth step of the method generally comprises generating a second output signal for a second threshold function in a logical OR operation of the result signals except for the particular one result signal.

Abstract: Efficient implementations of arithmetic functions in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate both an exclusive OR (XOR) function of first and second input signals and a second function. In some embodiments, the second function is simply the second input signal to the XOR function. In other embodiments, the second function is a different function optionally independent of the first and second input signals. The XOR function output drives the select terminal of a carry multiplexer, which selects between a carry in signal and one of the second input signal and the second function output signal to provide the carry out output signal. The sum or multiplier output value is provided by an XOR gate driven by the XOR function output and by the carry in signal, and can be optionally registered.

Abstract: A programmable logic block provides fast interconnect paths between carry multiplexer output terminals and the input terminals of function generators (e.g., lookup tables) in the same logic block. An integrated circuit includes an interconnect structure, a function generator, and a carry multiplexer having a select terminal programmably coupled to an output terminal of the function generator. An output signal from the carry multiplexer can traverse the interconnect structure to reach the input terminals of the function generator. However, a “fast connect” path is also provided that interconnects the carry multiplexer output with an input terminal of the function generator, without traversing the interconnect structure. In some embodiments, fast connect paths are also provided to input terminals of other function generators in the same logic block.

Abstract: Techniques are provided for improving signal timing characteristics of differential input/output (IO) circuits on programmable logic integrated circuits. A differential buffer receives differential signals applied to differential input pins. The output signals of the differential buffer are routed to two hard IO decoder blocks that are located in two adjacent rows/columns of programmable logic elements. Each IO decoder block has a data-in register that receives output signals of the differential buffer. The data-in registers in two adjacent IO decoder blocks support a double clocking technique. IO decoder blocks of the present invention have reduced setup times, hold times, and sampling windows relative to soft DDIO blocks, and have a minimal impact on die area.

Abstract: A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal G1 of a transistor M1 in a switch cell SC is connected only to the terminal 37 of a transistor M2, when the transistor M2 is set to off, the moving path of the charge accumulated at the gate G1 of the transistor M1 is shut off. Consequently, even if the transistor M2 is set to an on state and immediately set back to an off state, the transistor M1 remains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor M1 to remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.

Abstract: A programmable logic block provides fast interconnect paths between memory element output terminals and the input terminals of carry multiplexers in the same logic block. An integrated circuit includes an interconnect structure, a function generator, a carry chain multiplexer coupled to an output terminal of the function generator, and a memory element programmably coupled to the output terminal of the function generator. An output signal from the memory element can traverse the interconnect structure to reach an input terminal of the carry multiplexer. However, a “fast connect” path is also provided that interconnects the memory element output with an input terminal of the carry multiplexer, without traversing the interconnect structure. In some embodiments, fast connect paths are also provided to the input terminals the function generator, and to the input terminals of other function generators and/or carry multiplexers in the same logic block.

Abstract: Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states. Circuits and methods for implementing ternary and multi-value functions are also disclosed. Corrective design techniques that can be used when a logic expression is incorrectly realized are also disclosed. Circuits that use inverters and gates to realize logic expressions are also provided.

Abstract: An input circuit (a first transistor pair) that receives complementary input signals is connected to a latch circuit (a second transistor pair) that converts the amplitude of an input signal into second amplitude higher than first amplitude. A current mirror circuit (a third transistor pair) is disposed between the latch circuit and a high-level power supply line. The current mirror circuit makes a source voltage of the second transistors being turned on lower than the source voltage of the second transistors being turned off. The second transistors being turned on are likely to be turned off although the on-current of corresponding first transistors is low. To the contrary, the second transistors being turned off are likely to be turned on. Accordingly, even when a voltage of a high logic level of an input signal is low, the level conversion circuit can surely operate without malfunction.