Abstract: The process and apparatus introduce a carrier gas into a vacuum evaporation chamber, evaporate a film forming material from a evaporation source and deposit the evaporated film forming material on a substrate in sheet form to form a stimulable phosphor layer, thereby producing a evaporated phosphor sheet having a stimulable phosphor layer formed on the substrate. The stimulable phosphor layer is formed with substantially all areas of the evaporation source except opening for evaporation being masked to block movement of heat toward the substrate. The evaporated phosphor sheet includes the substrate and a CsBr:Eu evaporated stimulable phosphor layer deposited on the substrate. A maximum intensity of instantaneous light emission from the stimulable phosphor layer at 640 nm upon excitation by uv radiation is lower than a maximum intensity of the instantaneous light emission at 440 nm.

Abstract: The present invention relates to a process of forming a phase-change memory. A lower electrode is disposed in a first dielectric film. The lower electrode comprises an upper section and a lower section. The upper section extends beyond the first dielectric film. Resistivity in the upper section is higher than in the lower section. A second dielectric film is disposed over the first dielectric film and has an upper surface that is coplanar with the upper section at an upper surface.

Abstract: This invention relates to a process for manufacturing nanowire structures, the process comprising the following steps: manufacture of a thin semiconductor film (1) extending between a first terminal (4) and a second terminal (5), and passage of a current between the first and the second terminals so as to form at least one continuous overthickness (R1, R2, R3) in the thin semiconductor film by migration of a fraction of the semiconductor material, under the action of the current, the continuous overthickness being formed along the direction of the current that passes through the film.

Abstract: A solid state light emitting device having a plurality of semiconductor finger members with side walls perpendicular to a substrate. Multiple quantum wells are formed on the side walls, and are also perpendicular to the substrate. Each multiple quantum well is sandwiched between the side wall of a finger member and a second semiconductor member of a conductivity type opposite to that of the finger member. Ohmic contacts are applied to the finger members and second semiconductor member for receiving a voltage. The device is GaN based such that emitted light will be in the UV region.

Abstract: The present invention relates to a preferred semiconductor substrate for the production of devices. The semiconductor substrate is comprised of GaAs. Then, a plurality of quantum rings, which are composed of GaSb and have a substantially elliptical shape with an aspect ratio of 2 or more but 5 or less, are formed on a surface of the semiconductor substrate. These quantum rings extend along in the substantially same direction. In a case where a light beam is irradiated onto the surface of the semiconductor substrate, among the polarized components of the irradiated light, one polarized component parallel to the long-axis direction of the ellipse that is an extending direction of each quantum ring is reflected, while another polarized component parallel to the short-axis direction thereof is transmitted. That is, the semiconductor substrate reflects one polarized component, and transmits the other polarized component.

Abstract: A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

Abstract: The present invention-provides a tunnel-injection device which encompasses, a reception layer made of a first semiconductor, a barrier-forming layer made of a second semiconductor having a bandgap-narrower than the first semiconductor, being in metallurgical contact with the reception layer, a gate insulating film disposed on the barrier-forming layer. The gate electrode controls the width of the barrier generated at the heterojunction interface between the reception layer and the barrier-forming layer so as to change the tunneling probability of carriers through the barrier. The device further encompasses a carrier receiving region being contact with the reception layer and a carrier-supplying region being contact with the barrier-forming layer.

Abstract: A semiconductor detector has a tunable spectral response. These detectors may be used with processing techniques that permit the creation of “synthetic” sensors that have spectral responses that are beyond the spectral responses attainable by the underlying detectors. For example, the processing techniques may permit continuous and independent tuning of both the center wavelength and the spectral resolution of the synthesized spectral response. Other processing techniques can also generate responses that are matched to specific target signatures.

Abstract: A technique for manufacturing TFTs having little dispersion in their electrical characteristics is provided. Contamination of a semiconductor film is reduced by performing oxidation processing having an organic matter removing effect, forming a clean oxide film, after removing a natural oxide film formed on a semiconductor film surface. TFTs having little dispersion in their electrical characteristics can be obtained by using the semiconductor film thus obtained in active layers of the TFTs, and the electrical properties can be improved. In addition, deterioration in productivity and throughput can be reduced to a minimum by using a semiconductor manufacturing apparatus of the present invention.

Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.

Abstract: An inventive semiconductor device is provided with: a silicon carbide substrate 1; an n-type high resistance layer 2; well regions 3 provided in a surface region of the high resistance layer 2; a p+ contact region 4 provided within each well region 3; a source region 5 provided to laterally surround the p+ contact region 4 within each well region 3; first source electrodes 8 provided on the source regions 5 and made of nickel; second source electrodes 9 that cover the first source electrodes 8 and that are made of aluminum; a gate insulating film 6 provided on a portion of the high resistance layer 2 sandwiched between the two well regions 3; a gate electrode 10 made of aluminum; and an interlayer dielectric film 11 that covers the second source electrodes 9 and the gate electrode 10 and that is made of silicon oxide.

Abstract: A semiconductor laser device includes a one-body submount composed of a predetermined material such as SiC or AlN and placed on a mounting surface. A laser diode is placed on a front portion of an upper surface of the submount. A monitoring photodiode composed of crystalline silicon is stacked on a portion of the upper surface of the submount backward from the laser diode.

Abstract: Device structures for sheets of light active material. A first substrate has a transparent first conductive layer. A pattern of light active semiconductor elements are fixed to the first substrate. The light active semiconductor elements have an n-side and a p-side. Each light active semiconductor element has either of the n-side or the p-side in electrical communication with the transparent conductive layer. A second substrate has a second conductive layer. An adhesive secures the second substrate to the first substrate so that the other of said n-side or said p-side of each said light active semiconductor element is in electrical communication with the second conductive layer. Thus forming a solid-state light active device.

Abstract: In a surface-mounted optical transmission module, a laser diode serving as a light emitting device that converts an electric signal into an optical signal, and an optical waveguide serving as an optical transmission line that transmits and outputs the optical signal from the laser diode are placed on a substrate. A driving device for controlling the driving of the laser diode is placed at a predetermined position on the upper surface of the optical waveguide element, which is on the same side as an optical waveguide element (on the downstream side in the optical-signal transmitting direction) relative to the laser diode. This configuration eliminates the necessity of placing the driving device at a position distanced from the laser diode, whereby the size of the optical transmission module can be reduced, and this allows the optical transmission module to transmit optical signals at high speed.

Abstract: Includes a stem with a hole, a dielectric sealed into the hole of the stem and including a pair of pin insertion holes, and a pair of high frequency signal pins that penetrate and fit into the pair of pin insertion holes of the dielectric, and constituting differential lines connected to an optical semiconductor element.

Abstract: A single-chip white light emitting device, including: a substrate, a buffer layer, a first conductive cladding layer, a second conductive cladding layer, at least one broad-spectrum blue-complimentary light quantum dot emitting layer and at least one blue light emitting layer. The buffer layer is disposed over the substrate. The first conductive cladding layer is disposed over the buffer layer. The broad-spectrum blue-complimentary light quantum dot emitting layer is disposed between the first conductive cladding layer and the second conductive cladding layer. The blue-complimentary light quantum dot emitting layer includes plural quantum dots with an uneven character distribution, so as to increase FWHM of emission wavelength of the quantum dot emitting layer. The blue light emitting layers is disposed between the first and second conductive cladding layers, such that mixing of blue light and blue-complimentary light would generate white light.

Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.

Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.

Abstract: Different patterns of interconnects for connecting wells in a semiconductor device are described. For example, a semiconductor device may include n-wells and p-wells arrayed in rows and columns that lie on a rectilinear grid. Electrically conductive interconnects link at least some of the wells. The interconnects are arranged as a mesh having openings that are substantially rectangular in shape.

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Abstract: A method and apparatus for coupling to a source line. Specifically, embodiments of the present invention disclose a memory device comprising an array of flash memory cells with a source line connection that facilitates straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column implanted with n-type dopants is also isolated between an adjoining pair of STI regions. The source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions in the array. A source contact is coupled to the source column for providing electrical coupling with the plurality of source regions. The source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells.

Abstract: A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.

Abstract: A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating conditions, and provides a low-resistance current path during an ESD event.

Abstract: A CMOS image sensor and a manufacturing method thereof are disclosed. The gates of the transistors are formed in an active region of a unit pixel, and at the same time, a passivation layer is formed on an edge portion of the active region of a photodiode to have the same laminate structure as the gates of the transistors. Impurities for a diffusion region of the photodiode are ion-implanted into the active region for the photodiode, after the laminate structure is formed. The passivation layer prevents the edge portion from being damaged by ion implantation at the boundary or interface between the photodiode diffusion region and an isolation layer, which reduces dark current and/or leakage current of the CMOS image sensor.

Abstract: A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: Methods for forming platinum-iridium films, particularly in the manufacture of a semiconductor device, and devices (e.g., capacitors, integrated circuit devices, and memory cells) containing such films.

Abstract: Diffusion layers 2–5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2–5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

Abstract: A semiconductor storage device showing a good memory characteristic, and a manufacturing method thereof, includes a semiconductor layer, a stacked body including a first insulating layer, a charge trapping layer, and a second insulating layer that are provided above the semiconductor layer, a gate electrode provided above the stacked body, a side wall insulating layer provided at the side of the gate electrode, and impurity regions and provided in the semiconductor layer. The end surface of the stacked body is positioned outside the end surface of the gate electrode.

Abstract: A semiconductor device and a fabricating method thereof are disclosed. The semiconductor device includes polysilicon gate electrodes, a gate oxide layer, sidewall floating gates, a block oxide layer, source/drain areas, and sidewall spacers. In addition, the method includes the steps of: forming a block dielectric layer and a sacrificial layer on a semiconductor substrate; forming trenches by etching the sacrificial layer; forming sidewall floating gates on lateral faces of the trenches; forming a block oxide layer on the sidewall floating gates; forming polysilicon gate electrodes by a patterning process; removing the sacrificial layer; forming source/drain areas by implanting impurity ions into the resulting structure; injecting carriers or electric charges into the sidewall floating gates; and forming spacers on lateral faces of the polysilicon gate electrodes and the sidewall floating gates.

Abstract: Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded germanium content and strained silicon channels.

Abstract: A lateral semiconductor device includes: a semiconductor substrate formed on a base region therein; a plurality of emitter regions with a triangle arrangement in an upper part of the base layer and collector regions surrounding the emitter regions, respectively, apart from the emitter regions with a predetermined space through the base layer; the base layer formed in a concentric circular pattern on the upper part; the emitter regions and collector regions provided with contacts respectively; and emitter and collector wiring layers connected to the contacts.

Abstract: A trench type power semiconductor device includes proud gate electrodes that extend out of the trenches and above the surface of the semiconductor body. These proud gate electrodes allow for making ultra-shallow source regions within the semiconductor body using, for example, a low temperature source drive. In addition, a method for manufacturing the trench type power semiconductor device includes a low temperature process flow once the gate electrodes are formed.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are applied to the device.

Abstract: The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an SRAM cell have body regions linked by a leakage path diffusion region positioned beneath shallow source/drain diffusions, where the leakage path diffusion region extends from the bottom of the source/drain diffusion to the buried oxide layer, and at least one pair of NFETs from adjacent SRAM cells which have body regions linked by a similar leakage path diffusion region beneath adjacent source/drain diffusions.

Abstract: A semiconductor apparatus is provided that includes a radiator for efficiently radiating heat generated in a wiring layer used in a surge current path of an electrostatic discharge protection circuit, and also for protecting the wiring layer itself used as the surge current path. The semiconductor apparatus includes an input protection circuit coupled to a wiring provided between an external terminal and an internal circuit, the input protection circuit includes a protection element for protecting the internal circuit from an excessive electrostatic surge input supplied to the external terminal. The semiconductor apparatus further includes a first metal wiring layer coupled to the input protection circuit and included in a current path for the surge electrostatic surge input, and a radiator including a sufficient thermal conductivity material coupled to the first metal wiring layer.

Abstract: An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed in the well region. A second region formed having a portion in the weil region and another portion outside the well region, but still within the semiconductor substrate. Moreover, a third region formed within the well region and in between the first; region and the second region. A fourth region formed within the semiconductor substrate and outside the well region. A fifth region formed within the semiconductor substrate and in between the second region and the fourth region.

Abstract: Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about the same TCRs.

Abstract: A photodetector (10) includes a substrate (12) having a surface; a first layer (14) of semiconductor material that is disposed above the surface, the first layer containing a first dopant at a first concentration for having a first type of electrical conductivity; and a second layer (16) of semiconductor material overlying the first layer. The second layer contains a second dopant at a second concentration for having a second type of electrical conductivity and forms a first p-n junction (15) with the first layer. The second layer is compositionally graded through at least a portion of a thickness thereof from wider bandgap semiconductor material to narrower bandgap in a direction away from the p-n junction. The compositional grading can be done in a substantially linear fashion, or in a substantially non-linear fashion, e.g., in a stepped manner.

Abstract: To provide a solid-state imaging device in which the number of transistors for each signal readout circuit provided in a semiconductor substrate side is reduced and the number of image signal readout lines is reduced, solid-state imaging device a semiconductor substrate; a stacked photoelectric conversion films detecting different colors contained in an incident light; and pixel electrode films partitioned in accordance with pixels, wherein the semiconductor substrate includes: a plurality of color selection transistors corresponding to one of the pixels, wherein the color selection transistors each corresponds to one of the photoelectric conversion films and connects to one of the pixel electrode films on the one of the photoelectric conversion films so as to be capable of selecting the one of the photoelectric conversion films; and a charge detection cell corresponding to one of the pixels, the charge detection cell being common to the photoelectric conversion films.

Abstract: A divided drain implant structure for transistors used for electrostatic discharge protection is disclosed. At least two transistors are formed close to each other on a substrate with their gates and sources coupled together and with the drains placed next to each other and separated as a divided drain implant structure. The divided drain implant structure further comprises at least two drain implant regions separated by a lightly doped drain region and a halo implant region formed underneath. At least one of the drain implant regions is coupled to an input/output pad of a circuit.

Abstract: A semiconductor device, including a transistor having low threshold voltage and high breakdown voltage, includes a first gate electrode, a second gate electrode, and a third gate electrode arranged on a predetermined first, second, and third region of a semiconductor substrate, respectively, a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer, which are interposed between the first, second and third gate electrode and the semiconductor substrate, respectively, and first, second, and third junction regions arranged in the first, second, and third region of the semiconductor substrate, respectively, on both sides of the first, second and third gate electrode, respectively, wherein a thickness of the first gate insulating layer is greater than a thickness of either of the second or third gate insulating layers, and wherein a structure of the first junction region and a structure of the third junction region are the same.

Abstract: A method is provided for tuning (i.e. modifying, changing) the impedance of semiconductor components or devices using a focused heating source. The method may be exploited for finely tuning the impedance of semiconductor components or devices, by modifying the dopant profile of a region of low dopant concentration (i.e. increasing the dopant concentration) by diffusion of dopants from adjacent regions of higher dopant concentration through the melting action of a focused heating source, for example a laser. The present invention is in particular directed to the use of lasers in relation to circuits for the creation of conductive links and pathways where none existed before. The present invention more particularly relates to a means wherein impedance modification (i.e. trimming or tuning) may advantageously be carried out as a function of the location of one or more conductive bridge(s) along the length of a gap region.

Abstract: A semiconductor device includes a transmission power amplifier having cascaded MOSFET amplification stages disposed over a main surface of a semiconductor substrate. A CMOSFET control circuit controls the amplification stages. A first capacitor is also provided having upper and lower metal film electrodes formed over the main surface of the semiconductor substrate. The amplification stages are electrically coupled to one another via an inter-stage matching circuit which includes the first capacitor.

Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

Abstract: To provide a polishing composition whereby the stock removal rate of a silicon nitride layer is higher than the stock removal rate of a silicon oxide layer, there is substantially no adverse effect against polishing planarization, and a sufficient stock removal rate of a silicon nitride layer is obtainable, and a polishing method employing such a composition. A polishing composition which has silicon oxide abrasive grains, an acidic additive and water, wherein the acidic additive is such that when it is formed into a 85 wt % aqueous solution, the chemical etching rate of the silicon nitride layer is at most 0.1 nm/hr in an atmosphere of 80° C. Particularly preferred is one wherein the silicon oxide abrasive grains have an average particle size of from 1 to 50 nm, and the pH of the composition is from 3.5 to 6.5.

Abstract: A tape package in which a test pad is formed on a reverse surface is provided. The test pad is disposed on a reverse surface of a base film through a through hole of the base film. Accordingly, shapes of the test pads are standardized so that a universal probe card can be used. A pitch between the test pads is wide so that the accuracy in an electric test of the tape package is increased. A total length of the tape package is reduced.

Abstract: A semiconductor package comprising a plurality of elongate leads which each have opposed inner and outer ends, opposed first and second surfaces, and a third surface which is disposed in opposed relation to the first surface and recessed relative to the second surface. The second surface of each lead is positioned in close proximity to the inner end thereof. The third surface of each lead extends to the outer end thereof. A semiconductor die is attached to portions of the first surfaces of at least some of the leads. The semiconductor die is itself electrically connected to at least some of the leads. A package body covers the semiconductor die and the leads such that the second surfaces of the leads are exposed in a bottom surface of the package body and the outer ends of the leads are exposed in respective side surfaces of the package body.

Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.

Abstract: A stacked-type semiconductor device includes a first wiring substrate on which a semiconductor device element is mounted, a second wiring substrate stacked on the first wiring substrate through a plurality of electrode terminals which are electrically connected with the first wiring substrate, and a conductor supporting member disposed around the semiconductor device element, and connected with grounding wiring layers provided in the first and second wiring substrate.