Abstract: An improved chuck with lift pins within a probe station.

Abstract: An isolation resistor is incorporated into the plunger of a probe tip spring pin by, for example, doping a ceramic that is used to form the plunger, or forming the plunger of first and second electrically coupled materials, at least a first of which has a resistivity sufficient to serve as an isolation resistor. Alternately, an isolation resistor is embedded in a printed circuit board trace that is used to couple either an upper or lower blind plated hole to a via. A probe tip spring pin is then inserted into the upper blind plated hole.

Abstract: A method of automatically carrying IC-chips, on a planar array of vacuum nozzles, to a variable target in a chip tester uses a set of laser distance sensors to align the vacuum nozzles with the target. Alignment occurs when certain combinations of distance and distance changes are sensed.

Abstract: A radio frequency identification (RFID) tag with embedded memory testing scheme and the method of testing the same is disclosed, in which the RFID tag is comprised of an analog block, a digital block and a memory block. Operationally, as the analog block receives and demodulates a memory self-test signal issued from a reader, the memory block is driven to issue a non-digital memory state signal to be received by the analog block where it is being converted into a digital memory state signal, and then the digital memory state signal is being transmitted to the digital block for enabling the same to make an evaluation to determine whether the received digital memory state signal fall within the range representing the memory is in good condition, and thereafter, the evaluation is send to the reader by the RFID tag so as to enable the reader to select a posterior process to be perform accordingly.

Abstract: A flexible circuit has contacts for mounting in a socket or card edge connector. The flexible circuit includes integrated circuit devices mounted on both sides of the edge connector contacts. Preferably, the flexible circuit is wrapped about an edge of a rigid substrate and presents contacts on both sides of the substrate for mounting in a socket. Multiple flexible circuits may be overlaid with the same strategy. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers.

Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).

Abstract: A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

Abstract: A functionality test method for a technical system having at least one technical component to be regularly tested. The method including the steps of defining a test interval by setting a minimum time interval and a maximum time interval between two successive tests of the technical component, defining a test range for a decision parameter, sensing an actual value of the decision parameter, and performing a functionality test of the technical component if the minimum time interval between two successive tests of the technical component has elapsed and the sensed actual value of the decision parameter is within the predefined test range, or the maximum time interval between two successive tests of the technical component has elapsed.

Abstract: A testing method for an array substrate is disclosed which includes a first measuring step of operating a line electrode driver circuit 15 and a row electrode driver circuit 16 like in a normal display mode while implementing writing in/reading out of a test video signal to and from supplemental capacitors 13, and a second measuring step of implementing writing in/reading out of the test video signals to and from a video bus 163 while rendering TFTs 11 of a pixel section 18 and analog switches 162 of the row electrode driver circuit 16 to be held turned off. Obtaining a difference between a measured result of the first measuring step and a measured result of the second measuring step allows only a pixel component and a row electrode component with no driver component to be derived, whereupon discrimination is implemented for the presence of or the absence of electric defects in the pixel section.

Abstract: A power supply comprises a rectifier, a transformer, a switching member, a controller and a voltage blocking clamp. A power supply can receive an alternating current (AC) input voltage having any magnitude within a wide range of AC input voltage magnitudes and can produce from any such AC input voltage magnitude a direct current (DC) output voltage. The voltage blocking clamp comprises at least one transistor connected between the rectifier and the transformer and switching member that limits the amount of rectified AC input voltage applied to the transformer and switching member to a predetermined amount when the rectified input voltage exceeds that predetermined amount. When the rectified input voltage exceeds the predetermined amount, the amount of the rectified input voltage above the predetermined amount is applied to the at least one transistor instead of the transformer and switching member.

Abstract: The present invention provides a diagnostics methodology and embedded electronic system that allows optimized low-frequency data sampling for EMA motoring subsystems in an operating vehicle. Each of the EMA motoring subsystems includes: an EMA; at least one motor for driving the EMA; and power controls for operating the motor, wherein the power controls includes a DSP controller for sampling and processing data at low-frequency sampling rates. The diagnostic methodology includes a method that has the steps of: determining an operational mode of the EMA motoring subsystem; selecting a sampling rate optimized for the determined operational mode; acquiring and processing data at the selected sampling rate; and analyzing the processed data to identify and classify a fault of the EMA motoring subsystem.

Abstract: Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor includes an analog-to-digital converter which is reconfigurable responsive to input via a dynamic reconfiguration port.

Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

Abstract: The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the drive capacity of the circuit component is adjusted responsive to the determination result. In particular, the circuit component is tailored to have just sufficient drive capacity depending on the potential load which may be determined by examining a configuration information loaded to the circuit arrangement. Tailoring for sufficient drive can be achieved either by varying the size or number of circuit components or by adjusting the threshold voltage of circuit elements, or by doing both. Thereby, power consumption can be reduced when circuit components are driven at loads lower than the worst case load.

Abstract: Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output link is connectable to an off-chip impedance load, and at least one switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The input node is coupled to a reference signal and the control structure is coupled to the first and second signal links. The output node is coupled to the output link, and the channel element is sized to carry sufficient current to drive said off-chip impedance load.

Abstract: The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital high signal. The digital high signal indicates that a hot socket condition exists.

Abstract: A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (VDD) and lower voltage level (VSS), in such a way that the paired transistors operate in subthreshold. N input terminals (X1, X2, . . . XN) are connected to the respective paired transistors. Control terminals (BP, BN) are connected to control input nodes of the transistors. The circuit element provides the possibility of real time configuration between various logic functions with a minimum of transistors and wiring.

Abstract: A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.

Abstract: A differential sense amplifier is described that can be configured as a preamplifier or a latch circuit as triggered by a clock signal connected to a switch circuit. When the clock signal is set at a first signal level, the switch circuit in the differential sense amplifier is activated so that the differential sense amplifier is configured as a preamplifier with a positive feedback circuit. When the clock signal is set at a second signal level, the switch circuit in the differential sense amplifier is deactivated so that the differential sense amplifier is configured as the latch circuit. For one read cycle, the differential sense amplifier operates first as the preamplifier and then as the latch circuit.

Abstract: An integrated circuit temperature sensor includes a sensing circuit operable to determine whether the integrated circuit is currently exposed to one of a relatively low temperature or a relatively high temperature. A selection circuit operates to select a measured voltage across the base-emitter of a bipolar transistor of the integrated circuit if the sensing circuit indicates that the integrated circuit is currently exposed to the relatively low temperature or, alternatively, select a measured delta voltage across the base-emitter of the bipolar transistor of the integrated circuit if the sensing circuit indicates that the integrated circuit is currently exposed to the relatively high temperature.

Abstract: An output circuit includes: a current source transistor connected between a high-potential-side power supply and an output terminal; a current sinking transistor connected between a low-potential-side power supply and the output terminal; a third transistor constituting a current mirror circuit together with the current source transistor; a fourth transistor connected with the third transistor to control a driving current of the current source transistor; and a fifth transistor supplying a current corresponding to a base potential of the current sinking transistor to the fourth transistor.

Abstract: A low-voltage differential signal driver with a pre-emphasis circuit having a current control circuit and a pre-emphasis circuit is provided. Wherein, the pre-emphasis circuit includes the current sourcing circuit and the current sinking circuit, both of which have similar circuit structure, coupled to the current control circuit, respectively. The current sourcing circuit and the current sinking circuit are controlled by two sets of driving signals, so that the pre-emphasis circuit provides an extra driving current to the current control circuit at an instant when the current control circuit switches the current direction. In addition, each set of driving signals contains two synchronous but phase-inversed driving signals. The time it takes for the current steering circuit to switch terminated resistor current between upward and downward directions is decreased.

Abstract: A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.

Abstract: Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD includes either one or two variable delay lines that provide coarse phase adjustment of an associated input signal. Each HD also includes one or more phase mixers that provide fine phase adjustment of the input signal.

Abstract: A voltage-pulse converting circuit according to an embodiment of the invention includes: a first input terminal and a second input terminal applied with an input voltage to be converted into a pulse; an integrator having positive and negative input terminals; an input switching unit switching connection between the first and second input terminal and the positive and negative input terminals of the integrator; and a first comparator comparing a first detection voltage with an output voltage of the integrator and a second comparator comparing a second detection voltage different from the first detection voltage with the output voltage, the input switching unit switching the connection based on a comparison result of the first and second comparators.

Abstract: A driver apparatus for a voltage driven type switching element and a method for driving a voltage driven type switching element that discharge an electrical charge stored at the gate terminal of the voltage driven type switching element at a discharge rate. The discharge rate is controlled so that the change rate over time of the voltage between the collector terminal and the emitter terminal of the voltage driven type switching element approaches a predetermined change rate. Control of the change rate over time of the voltage between the collector terminal and the emitter terminal to attain the predetermined change rate is delayed for a predetermined delay time after start of the turn-off operation.

Abstract: A system on a chip integrated circuit includes a first circuit module and N other circuit modules that are operable to produce at least one output signal based on at least one input signal. A reference oscillator for generating a base clock signal for the first circuit module. A clock delay generator generates N delayed clock signals at a corresponding N clock delays, wherein N is greater than or equal to 2. The N delayed clock signals are provided to the N other circuit modules.

Abstract: A pulse circuit contains an input stage configured to receive input pulses on input nodes using push-pull elements, wherein a given push-pull element is configured to receive an input pulse on a given input node and to provide a corresponding internal signal. The pulse circuit further contains a feedback loop that includes a logic element coupled between outputs from the push-pull elements and reset nodes of the push-pull elements. This logic element is configured to provide one or more outputs from the pulse circuit and to reset the internal signals from the push-pull elements via the feedback loop.

Abstract: A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.

Abstract: An accurate temperature monitoring system that uses a precision current control circuit to apply accurately ratioed currents to a semiconductor device, which may be a bipolar junction transistor (BJT), used for sensing temperature. A change in base-emitter voltage (?VBE) proportional to the temperature of the BJT may be captured and provided to an ADC, which may generate a numeric value corresponding to that temperature. The precision current control circuit may be configured to generate a reference current, capture the base current of the BJT, generate a combined current equivalent to a sum total of the base current and a multiple of the reference current, and provide the combined current to the emitter of the BJT. In response to this combined current, the collector current of the BJT will be equivalent to the multiple of the reference current. The ratios of the various collector currents conducted by the BJT may thus be accurately controlled, leading to more accurate temperature measurements.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: A charge pump generates a voltage higher than an intermediate voltage and a regulator circuit provides a first regulated voltage higher than the intermediate voltage. A second stage includes a regulator stage using the first voltage to provide the intermediate voltage from the first voltage. A charge pump provides a pump output voltage. The pump output voltage is divided and the divided voltage is presented to a first comparator that compares it with a reference voltage. The first comparator drives the gate of a first MOS transistor to regulate the pump output voltage to a regulated voltage related to the reference voltage. The regulated voltage is presented to a second comparator that compares it with the reference voltage. The second comparator drives the gate of a second MOS transistor to downconvert the regulated output voltage to an intermediate voltage related to the reference voltage.

Abstract: A constant voltage circuit is disclosed that includes an output control transistor and an overcurrent protection circuit. The overcurrent protection circuit includes a proportional current generation circuit part, a current division circuit part, a division ratio control circuit part, a current-voltage conversion circuit part, and an output current control circuit part. When the output voltage of the current-voltage conversion circuit part reaches a predetermined voltage, the output current control circuit part prevents an increase in the output current of the output control transistor so as to reduce a voltage output from an output terminal. When the voltage output from the output terminal is reduced to a predetermined limit voltage, the division ratio control circuit part changes the division ratio of the current division circuit part so that a current supplied to the current-voltage conversion circuit part increases so as to reduce the output current of the output control transistor.

Abstract: A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.

Abstract: A differential amplifier arrangement (53) comprising an input stage (1) and an output stage (2) is described. The input stage (1) comprises a differential amplifier (3, 4) to which an offset compensation stage (10) is connected, which comprises at least one controllable current source (11) and which controls a bias signal of the differential amplifier (3, 4). With the described differential amplifier arrangement, which can preferably be used as an instrumentation amplifier, very precise compensation of input offsets can be carried out.

Abstract: In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.

Abstract: An amplifier includes: an input stage for receiving an input signal to generate a first signal corresponding to a first band; a first modulator coupled to the input stage for modulating the first signal to generate a second signal corresponding to a second band; an amplifier stage coupled to the first modulator for processing the second signal to generate a third signal, wherein the third signal includes a fourth signal corresponding to the second band and a first interference signal corresponding to the first band; and a second modulator coupled to the amplifier stage for modulating the third signal to generate a fifth signal corresponding to the first band and to generate a second interference signal corresponding to the second band.

Abstract: The present invention relates to a circuit configuration having a feedback operational amplifier (AMP), which is implemented as fully differential, for amplifying an input signal differentially input to the circuit configuration and for outputting the amplified input signal as a differential output signal. In order to increase the freedom in setting the input common mode voltage, according to the present invention, a combination made of a coupling resistor (R1b) and a level shifter (I1b, Nsfb) connecting the positive amplifier output (y1) to the inverting amplifier input (x2) and a combination made of a coupling resistor (R1a) and a level shifter (I1a, Nsfa) connecting the negative amplifier output (y2) to the noninverting amplifier input (x1) are provided.

Abstract: A transimpedance amplifier comprises a first operational amplifier having an input and an output. A second operational amplifier has an input and an output that communicates with the input of the first operational amplifier. A first feedback element has one end that communicates with the input of the first operational amplifier and another end that communicates with the output of the first operational amplifier, wherein the first feedback element comprises a first capacitance. A second feedback element communicates with the input of the first operational amplifier and another end that communicates with the output of the first operational amplifier.

Abstract: An amplifier circuit comprises a first amplifier having an input and an output. A second amplifier has an input that communicates with an output of the first amplifier. A third amplifier has an input that communicates with an input of the first amplifier. A fourth amplifier has an input that communicates with an output of the third amplifier and an output that communicates with the input of the second amplifier. A switched capacitance circuit selectively couples a capacitance to at least one of the input of the third amplifier and the output of third amplifier.

Abstract: The invention relates to optimizing the efficiency of a power amplifier of a transmitter. The objectives of the invention are achieved with a solution in which a voltage level of an output signal of an amplifier stage (301, 302) is detected (305, 306) at a signal output of each amplifier stage and the detected information is used for controlling a supply voltage of each amplifier stage in a way so that the unnecessarily high levels of the supply voltages can be avoided thus improving efficiency of the power amplifier.

Abstract: A radio frequency (RF) module provides first and second power amplifiers configured to produce first and second amplified RF signals at first and second output RF terminals, respectively; and first and second arrays of pads positioned opposite each other, the first array including the first output RF terminal and the second array including the second output RF terminal. The module also provides two reserve terminals that can be connected to capacitors, inductors, sensors for RF linearity, or can be left unconnected.

Abstract: The present invention provides lossless switching by configuring the output inductor so that the ripple current amplitude at load conditions results in small negative current during switching. The reconfigured output inductor results in increased ripple current amplitude. This increased ripple amplitude may be further controlled using zero ripple steering techniques to eliminate ripple at the output capacitor. A ripple steering technique involves adding a secondary output to the class D amplifier which steers the switching ripple away from the main output thus substantially relieving the main output from a major artifact of prior art Class D amplifiers.

Abstract: An operational amplifier and a scanning electron microscope which are capable of dealing with high voltage and large current, and which allow implementation of stable and precise amplification, the operational amplifier having a first-stage amplification unit including a differential pair, a base-grounded amplification circuit, and an active load, the base-grounded amplification circuit being cascode-connected to the differential pair a second-stage amplification unit including an inverter having an emitter follower circuit and a constant-current load circuit, and a third-stage amplification unit including a source follower circuit or an emitter follower circuit.

Abstract: A variable gain device having higher linearity and wider gain range is provided. The variable gain device includes a transduction unit for generating an output current, a control unit for adjusting the current gain of the gain amplifying unit according to a gain control signal, a gain amplifying unit receiving the current signal and generating a gain adjustable current according to the current gain of the control unit, an output DC level control unit controlling the DC level of the output signal of the variable gain device, and an output unit generating an output signal according to the signals output by the output DC level control unit and the gain amplifying unit.

Abstract: A variable gain amplifier includes a variable resistor, a first MOS transistor and a second MOS transistor. The variable resistor has one end coupled to a ground. The first MOS transistor with transconductance 2 gm amplifies a first differential input signal to provide a first current between an output node and other end of the variable resistor. The second MOS transistor with transconductance gm amplifies a second differential input signal to provide a second current between the output node and the ground. The variable resistor can be implemented using a MOS transistor operating in a linear region. The variable gain amplifier has an exponentially varying output current responsive to adjusting a gate voltage of the MOS transistor. Therefore, the transconductance of the variable gain amplifier has a linear-in-decibel characteristic.

Abstract: an analog signal processing block with differential signal inputs and including a differential amplifier with differential inputs is disclosed which is configurable to operate either in a differential output mode or in a single-ended output mode without affecting the desired frequency and time characteristics as determined by the switched capacitor networks. The analog signal processing block includes a pair of switched capacitor networks each having one of the differential signal inputs, an input-sided terminal connected to one of the differential inputs of the differential amplifier and an output-sided terminal. The output-sided terminal of a first one of the switched capacitor networks is connected to an output of the differential amplifier.

Abstract: A feedback control loop around a gain element controls the output signal of said gain element responsive to an input or reference signal, and is additionally responsive to a non-linear feedback signal. The feedback loop of this invention comprises computation means for exponentiating a signal representing the output of the gain element to generate said non-linear feedback signal. The control loop of invention provides exceptional transient response when used for driving reactive loads.

Abstract: A device for voltage-noise rejection and fast start-up is provided. It comprises a low-pass filter connected to a voltage source, a voltage-controlled switch connected in parallel with the low-pass filter, and an auxiliary start-up element connected to a DC-only voltage output. By using a transistor operating in the triode region and a capacitor with suitable capacitance, it is suitable for integration to form a low-frequency low-pass pole to suppress the noise in the reference current. The auxiliary start-up element overcomes the large turn on time caused by the low frequency low-pass pole. As there is no static current during normal operation, the power consumption for the device is low.

Abstract: A bias circuit includes a resistor in parallel with a voltage-drive bias circuit including GaAs-HBT transistor. This configuration ensures that a current can be supplied from a reference voltage input terminal to the base terminal of a first transistor via the resistor in an idling state in which a voltage applied to the base terminal is lower than a voltage at which a second transistor operates, thereby enabling a desired amplifying operation while maintaining the idling current generally constant in a temperature range, even when the reference voltage is reduced to a value lower than twice the barrier voltage of the GaAs HBT.