Abstract: Methods and kits useful in the detection of occult blood in biological samples and specimens, for example to screen for colorectal cancer or detect blood in samples ex vivo, e.g., at a crime scene. Also provided are methods useful in diagnosing whether a subject is predisposed to, or suffers from, an occult-blood related disorder; and methods for direct micro-mapping of the distribution of occluded vessels associated with cerebral vascular injury.

Abstract: A method for interpreting data that is produced after a group of amino acids and acylcarnitines are derivatized from blood spots taken from newborn babies and scanned by a tandem mass spectrometer. Concentration levels of each metabolite, which are directly proportional to the butyl ester fragment after derivatization, are compared to threshold flags for determining a significance of any deviation of the metabolite relative to the flag threshold. The threshold flags are diagnostic limits to the data retrieved from each blood spot. The data includes metabolite concentrations and molar ratios of metabolites with other metabolites. Samples are labeled normal for a disease if the concentration of any of the metabolite concentrations or molar ratio concentration do not deviate from the flag threshold, but, in contrast, the sample must be further evaluated if a value is elevated or deficient to some degree.

Abstract: Methods and compositions are disclosed for quantifying and/or identifying a nitroderivative compound, or a residue thereof, and are applicable for assessing in vivo nitrative stress and for aiding in diagnosis of mammalian pathologies such as asthma, atherosclerosis, Alzheimer's disease, inflammation, ischemia, Parkinson's disease, and cancer. A preferred method comprises a) providing a sample containing the nitroderivative compound, or residue thereof, in the form of a diazo compound or residue thereof; b) azo-coupling the diazo compound, or residue thereof, to a target compound capable of producing a signal, to yield an azo-coupled compound; c) isolating the nitroderivative compound, or residue thereof, or the azo-coupled compound; d) quantitating and/or detecting the signal, to yield a quantitation and/or detection result; and e) determining from the quantitation and/or detection result the identity and/or concentration of the nitroderivative compound, or residue thereof, in the sample.

Abstract: The invention relates to a process for the detection of hydrocarbons other than methane in a gas predominantly or essentially comprising oxygen, as well as methane and the said hydrocarbons other than methane, the said process comprising: a stage of detection of the combined hydrocarbons in the said gas, providing a first value for the combined hydrocarbons, a stage of combustion of the hydrocarbons other than methane, a stage of detection of methane in the said gas, providing a second value, a stage of calculation of the amount of hydrocarbons other than methane by the difference between the first value and the second value. The invention also relates to a device for implementing this process.

Abstract: A dielectric sensing method and apparatus are provided for detection and classification of chemical and biological materials. Resonance patterns of a sample within a resonator are detected for identifying a shift in resonance frequency and a change of line width before and after introduction of the sample. The identified shift in resonance frequency and change of line width are used for determining a complex dielectric constant of the sample for the material detection and classification. A degree of selectivity at any excitation frequency is enabled for the dielectric sensing method from the manner in which the complex dielectric constant of a material affects the resonance pattern of the resonator with respect to shift in resonance frequency and the change in line width. By selecting the excitation frequencies to generally correspond to one of the resonance frequencies of the sample material under test, the degree of selectivity and the sensitivity of detection are enhanced.

Abstract: Arrays are provided for multiplexed evanescent scanning by allowing for high-contrast Surface Plasmon Resonance images thereof. The arrays target features are typically biopolymeric in nature, though they may be any sort of chemical or ligand. The type of scanning is such that there is no need for probe labeling. As no labeling is required, a broader range of applications than otherwise possible is facilitated. In the subject arrays, target features are set upon a noble metal film deposited on a substrate. Interfeature areas are adapted to trap, divert and/or bleed-away light so that light directed through the substrate will not be reflected by those areas and interfere with evanescent scanning of the reflective areas upon which intended target features are provided. Geometric and materials-based light attenuating features are contemplated. Arrays as described, hardware and software as required for reading such arrays, and associated methodology are covered.

Abstract: Method for measuring the presence or absence of chemical groups, in particular phosphate groups, attached to biological molecules in a sample in which these molecules are tagged with fluorescent markers and these fluorescent markers are activated by means of irradiating the sample with light. The method is characterized by the following steps: a) Use of a fluorescent marker, the fluorescence lifetime of which assumes a different value depending upon the presence or absence of phosphate groups attached to the biomolecule; b) Measurement of the fluorescence lifetime of the fluorescent marker attached to a biomolecule and selected in accordance with Step a); c) Classification of the biomolecules in accordance with the presence or absence of phosphate groups attached to these, based on the different lifetime of each.

Abstract: This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be created by exposing layers of material in a superlattice and depositing material onto edges of the exposed layers.

Abstract: A scheme for aligning opaque material layers of a semiconductor device. Alignment marks are formed in a via level of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may have about the same length as vias formed in the via layer. The alignment marks comprise trenches that are not filled with material and are not exposed to a CMP process. An opaque material layer is deposited, and depressions are formed in the opaque material layer over the alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.

Abstract: According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

Abstract: A first hydrogen barrier film and an intermediate layer are formed on an interlayer dielectric film. A ferroelectric capacitor is formed on the intermediate layer, and a second hydrogen barrier film is formed over the entire surface including on the upper surface and side surfaces of the ferroelectric capacitor and on the intermediate layer. Then, the second hydrogen barrier film and the intermediate layer are removed while leaving at least portions on the upper surface and side surfaces of the ferroelectric capacitor. Then, a third hydrogen barrier film is formed on the second hydrogen barrier film, on side surfaces of the second hydrogen barrier film and the intermediate layer, and on the first hydrogen barrier film.

Abstract: The present invention is directed to controlling wafer temperature during rapid thermal processing. Regions and devices in an integrated circuit may be surrounded, inlayed, and overlaid with high absorptive structures to increase the average absorptivity of a region. This technique is useful for increasing average absorptivity in dense capacitive regions of integrated circuits. These dense capacitive regions typically have large areas of exposed low absorptivity polysilicon during rapid thermal processing steps. The exposed low absorptivity regions absorb less energy than other regions of the integrated circuit. As such, the RTP temperature varies between regions of the integrated circuit, causing variance in device size and characteristics. Adding absorptivity structures increase the absorption of energy in these regions, reducing temperature variance during RTP. The reduced temperature variance results in uniform manufacture of device.

Abstract: The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the semiconductor integrated circuit including probe pads on a top metal layer; (b) filling the dummy area with active test cells, the active test cells being connected to one another; and (c) connecting each of the active test cells to the probe pads with a metal line.

Abstract: A method of mounting a semiconductor laser component capable of preventing deterioration of laser characteristics and destruction of the semiconductor laser component due to a rise in temperature and a residual stress of the semiconductor laser component. The semiconductor laser component is mounted on a submount by heating and pressure-bonding, and is heated again up to a temperature more than a melting point of a bonding member at the released pressure to release the residual stress.

Abstract: A process of making a laser diode device includes these steps: applying a bonding layer such as molybdenum manganese to surfaces of first and second bodies of dielectric material such as beryllium oxide; joining the first and second bodies together to form a cavity; and bonding a sectored conductor ring to the bonding layer within the cavity.

Abstract: A wafer-level device fabrication process forms standing structures around emitting areas of multiple VCSELs. The standing structures can be shaped to hold ball lenses or other optical elements for respective VCSELs or can include platforms on which optical elements are formed. Ball lenses that are attached to the standing structures either during chip-level or wafer-level processes fit into the standing structures and are automatically aligned. Wafer level fabrication of optical elements can align the optical elements with accuracies associated with photolithographic processes. The optical elements can be formed using a molding or replication process, a printing method, or surface tension during a reflow of lithographically formed regions.

Abstract: A plurality of light-emitting diode light sources of the same kind are produced simultaneously. Each light source includes a light-emitting diode chip and a luminescence conversion element, which converts the wavelength of at least part of an electromagnetic radiation emitted by the light-emitting diode chip. In a first process, a layer composite with a light-emitting diode layer sequence applied to a carrier substrate is provided. The wafer is provided with trenches and then inserted into a cavity of a mold. A molding compound, which contains a luminescence conversion material, is driven in, so that the trenches are at least partly filled with the molding compound. The mold is then removed and the light-emitting diode light sources are separated from the layer composite. In a second process, instead of the layer composite, a plurality of light-emitting diode chips which are applied to a common carrier in a regular arrangement are provided.

Abstract: An array substrate for use in an X-ray sensing device and in an LCD device is fabricated using plasma gas treatment. Especially, an indium-tin-oxide (ITO) transparent conductive metallic layer is plasma-treated by N2 plasma, He plasma or Ar plasma, before forming the insulation layer on the ITO transparent conductive metallic layer. Thus, the plasma removes the impurities on a surface of the transparent conductive metallic layer and changes the lattice structure of the surface of the transparent conductive metallic layer, and thus the adhesion between the transparent conductive metallic layer and the insulation layer is improved. The defects caused by a gap or a space between the transparent conductive metallic layer and the insulation layer do not occur.

Abstract: An active-matrix substrate is provided, which suppresses the unevenness of its surface due to the height difference of the TFTs and gate and data lines from the remaining area. After TFTS, gate lines, and data lines are formed on a transparent base, a transparent dielectric layer is formed on the base to cover the TFTs, the gate lines, and the data lines. The dielectric layer is selectively etched to form transparent dielectric portions arranged in a matrix array in such a way as to form a first plurality of recesses extending along the respective gate lines and a second plurality of recesses extending along the respective data lines. Each of the portions has a thickness equal to or greater than the maximum height of the TFTs, the gate lines, or the data lines, and a distance equal to or greater than the thickness thereof from a corresponding one of the TFTs, the gate lines, or the data lines.

Abstract: A method for forming a modified semiconductor having a number of band gaps involves providing a semiconductor having a surface and a quantum region which emits photons in response to electrical or optical stimulation, the quantum region having an original band gap and being disposed under the surface and applying a number of layers of a number of materials to a number of selected regions of the surface, the materials being adapted to cause, upon thermal annealing, a number of different degrees of intermixing in a number of portions of the quantum region disposed immediately below each of the selected regions of the surface. The layers of materials can be applied in a dot or line pattern, or both, to increase the plurality of band gap tuning. The method includes thermally annealing the layers to the surface.

Abstract: In one aspect, a microelectromechanical device and method of producing the device includes an accelerometer with a thinned flexure structure. In another embodiment, the device and method of producing the device includes an accelerometer and a pressure sensor integrated on a single chip.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed. The CMOS image sensor a plurality of photosensitive devices formed on a semiconductor substrate, an interlayer dielectric formed on the photosensitive devices, and a plurality of color filter layers facing into each interlayer dielectric and filtering light for each wavelength, a planarization layer formed on each of the color filter layers, and a micro-lens layer formed on the planarization layer and having a refractive index distribution, in which light is focused to the photosensitive device facing thereto, based on an ion injection profile.

Abstract: Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors and integrated circuitry coupled to the image sensors. The method further includes providing a spacer having a web that includes an adhesive and has openings arranged to be aligned with the image sensors. For example, the web can be a film having an adhesive coating, or the web itself can be a layer of adhesive. The method continues by assembling the imager workpiece with the cover substrate such that (a) the spacer is between the imager workpiece and the cover substrate, and (b) the openings are aligned with the image sensors. The attached web is not cured after the imager workpiece and the cover substrate have both been adhered to the web.

Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass layer, formed over a first metal containing layer, formed over a first chalcogenide glass layer. The thin metal containing layer preferably is a silver layer. An electrode may be formed over the thin silver layer. The electrode preferably does not contain silver.

Abstract: This invention provides a new procedure for attaching molecules to semiconductor surfaces, in particular silicon. The molecules, which include, but are not limited to porphyrins and ferrocenes, have been previously shown to be attractive candidates for molecular-based information storage. The new attachment procedure is simple, can be completed in short times, requires minimal amounts of material, is compatible with diverse molecular functional groups, and in some instances affords unprecedented attachment motifs. These features greatly enhance the integration of the molecular materials into the processing steps that are needed to create hybrid molecular/semiconductor information storage devices.

Abstract: A method of manufacturing an optoelectronic packaging comprises placing a solder preform between a metal cover and an insulating base, applying pressure to the metal cover and the insulating base, and applying a current through multiple conductive vias to heat the solder preform to melt.

Abstract: A low stress, protective coating for a semiconductor device and a method for its manufacture. A preferred embodiment comprises coating the top surface of a semiconductor die with polyimide except for corner regions of the die. Not having corners in the polyimide protective overcoat generally reduces shear stresses in the die. Reducing stress, in turn, generally reduces the occurrence of problems such as fracture, delamination, or cracking within the die. A low stress coating may be particularly advantageous in semiconductor devices having low-k insulating materials, which are generally of low mechanical strength.

Abstract: An integrated circuit (IC) package includes a mold compound, a die, and a window. The mold compound has a frame embedded within it. The frame has a top surface, a bottom surface, and a top-to-bottom opening therein. The die is attached to the mold compound, wherein the embedded frame lies below a periphery of the die. The window is attached to the mold compound and located above the die to allow light to reach the die.

Abstract: An active matrix substrate comprises a substrate, a thick-film adhesive pad made of organic resin, provided on the substrate and including, at least at a part of a side face thereof, an inclined region having a first contact angle smaller than 90 degrees to the main face of the substrate, a thin-film active element provided on the thick-film adhesive pad, and a thin-film interconnection line connected to the thin-film active element and extending onto the substrate via the inclined region, a film thickness of the thick-film adhesive pad being four or more times that of the thin-film interconnection line.

Abstract: An apparatus that includes a first component defining an interior of the apparatus; a first solder composition exterior to the first component; a second solder composition exterior to the first solder composition and the first component; and a second component exterior to the second solder composition, the first solder composition, and the first component.

Abstract: Exemplary embodiments of the present invention include a semiconductor device, a method for manufacturing the same, a circuit board and an electronic apparatus with increased productivity and reliability. An exemplary method for manufacturing a semiconductor device of the present invention includes forming a conductive part in a concave part on a first surface of a semiconductor substrate, the first surface having a plurality of chip mounting areas. Stacking at least one semiconductor chip in each of the chip mounting areas, providing a sealing member on the first surface of the semiconductor substrate and making part of a second surface of the semiconductor substrate thin so as to make the conductive part penetrate from the first surface to the second surface.

Abstract: An electronic apparatus comprising one or more microstructures on a substrate and a method for fabricating the electronic apparatus. The microstructures have alignment structures that allow the microstructures to be oriented in receptacles having shapes that are complementary to the shapes of the alignment structures. The alignment structures are shapes that vary when rotated 360°, such that the microstructures are positioned at a specific orientation in the receptacles.

Abstract: In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body to perform a first division under bending stress. Thereafter, the upward-located clamper is rotatably swung (lower swing) downward to allow an upper clamp claw to press down the protruded wiring board portion, thereby performing a reverse division at the first division section again as a second division. Since the second division allows a tensile force to act on a remaining and thin non-divided resin portion, the non-divided resin portion is torn off. Thus, the perfect division is enabled. Fractionalizing is done by a one-row division and an individual division so that each semiconductor device is formed.

Abstract: A sensor device includes a sensor chip and a bonding wire being fixed on a substrate. The sensor device is manufactured by using a binding material made of an adhesive containing a foaming agent that evaporates upon exposure to heat. The binding material reduces its elasticity after a wire bonding process because voids being functional as a cushion are formed by evaporation of the foaming agent.

Abstract: A thermally conductive member is placed adjacent a microelectronic die with a thermal interface material between the microelectronic die and a wetting layer formed on a surface of the thermally conductive member. The thermal interface material is heated to cause reflow thereof. The first portion of the thermal interface material is directed by the wetting layer into a first cavity formed in the thermally conductive member. The thermal interface material is then allowed to cool and solidify.

Abstract: The electronic component has a semiconductor chip embedded in a plastic compound. The electronic component is produced by first producing a number of electronic components on a panel and subsequent dicing into single electronic components. The semiconductor chip of this component is disposed on a substrate which includes or is entirely formed of plastic and is embedded in a plastic package molding compound. The plastic of the substrate has a glass transition temperature range which is lower than the glass transition temperature range of the plastic package molding compound.

Abstract: A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.

Abstract: A method for manufacturing a semiconductor device by a small number of processes and by a means with high usability of materials to have high-definition and a gate insulating with a high step coverage property is disclosed. According to the present invention, a method for manufacturing a semiconductor device comprises the steps of forming a plurality of first conductive layers over a substrate; forming a first insulating layer to fill the gaps of the plurality of the first conductive layers; forming a second insulating layer over the first insulating layer and the plurality of the first conductive layers; and forming a semiconductor region and a second conductive layer over the second insulating layer.

Abstract: A method for fabricating a TFT array substrate for a liquid crystal display device is provided. The method includes: preparing a substrate; forming a gate line on the substrate using a first etchant; forming an insulation layer on the gate line; forming a semiconductor layer on a portion of the insulation layer; forming a test line on the insulation layer and source and drain electrodes on the semiconductor layer; forming a passivation layer having passivation hole to expose a portion of the gate line on the substrate; and forming a pixel electrode on the passivation layer by applying a second etchant including HNO3, a ferric compound, HClO4 and flouro compound.

Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.

Abstract: A method for manufacturing a thin-film semiconductor includes polycrystallization to focus visible light pulse laser into a line shape on a surface of an object to be irradiated, and repeat irradiation with displacing the visible light pulse laser such that a line-shaped irradiated region is overlapped with a region irradiated at a next timing in a width direction of the line-shaped irradiated region, to form a polycrystalline silicon film on the surface of the object. The step of polycrystallization applies ultraviolet light pulse laser onto a second irradiated region partially overlapping the first irradiated region while or before the visible light pulse laser is applied to the first irradiated region.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor film, and impurities to become the source/drain are introduced in this state. Then the impurities are activated, and the amorphized portion is recrystallized, by low temperature solid-phase epitaxial regrowth. With the processing temperature required for the low temperature solid-phase epitaxial regrowth being within a range of 450° C.–650° C., thermal diffusion of the impurities into the semiconductor film is suppressed, thereby maintaining the initial steep step-profile.

Abstract: An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.

Abstract: A method for manufacturing a semiconductor element, comprises: (1) forming a first insulating layer for electric field relaxation that is thicker than a first gate insulating layer in a first channel region of a transistor of a first conductive type that is one of P-type and N-type polarity formed on a semiconductor silicon wafer to surround an edge of a first gate electrode in order to reduce an electric field concentrated to a region surrounding the edge of the first gate electrode because of a voltage applied to the first gate electrode and a first drain region of the transistor of the first conductive type, and forming a second insulating layer for electric field relaxation that is thicker than a second gate insulating layer in a second channel region of a transistor of a second conductive type to surround the edge of the first gate electrode in order to reduce an electric field concentrated to a region surrounding an edge of a second gate electrode because of a voltage applied to the second gate electrod

Abstract: Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

Abstract: Embodiments of the invention include a circuit with a transistor having a self-aligned gate. Insulating isolation structures may be formed, self-aligned to diffusions. The gate may then be formed self-aligned to the insulating isolation structures.

Abstract: A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substrate with a selectively grown epitaxial layer. The selection transistor is formed in the selectively grown epitaxial layer, comprises a source region connected to the trench capacitor and a drain region connected to a bit line. The junction depth of the source region is chosen so that the source region reaches as far as the insulating covering layer. Optionally, the thickness of the epitaxial layer can be reduced to a thickness by oxidation and a subsequent etching. Afterwards, a contact trench is etched through the source region down to the conductive trench filling, which trench is filled with a conductive contact and electrically connects the conductive trench filling to the source region.

Abstract: A capacitor includes a capacitor part formed of a dielectric film sandwiched by a pair of electrodes and a support body formed of a film of an organic polysilane. The support body is provided so as to support the capacitor part thereon.

Abstract: A method is provided for making a buried plate region in a semiconductor substrate. According to such method, a trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed below the upper portion. A dopant source layer is formed along the lower portion of the trench sidewall, the dopant source layer not being disposed along the upper portion of the trench sidewall. A layer is formed to cover the upper portion of the trench sidewall. Annealing is then performed to drive a dopant from the dopant source layer into the semiconductor substrate adjacent to the lower portion of the trench sidewall.