Abstract: A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer formed over a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.

Abstract: Disclosed is a method for manufacturing a NAND flash device. After a source line plug hole is formed, a drain contact plug hole is formed. The holes are filled with a conductive material film and are then polished. It is therefore possible to simplify the process since a blanket etch process step is omitted. Moreover, loss of a drain contact plug by the blanket etch process is prevented. It is therefore possible to improve the electrical properties of a device and reduce the manufacturing cost price.

Abstract: Methods of fabricating a floating gate of a flash memory cell are provided in which a first polysilicon layer is formed between first and second isolation layers. An upper region of the first polysilicon layer is then oxidized. The oxidized upper region of the first polysilicon layer is subsequently removed. A second polysilicon layer is formed on the first polysilicon layer. The second polysilicon layer and the first polysilicon layer are patterned to form the floating gate.

Abstract: A flash memory structure comprises a semiconductor substrate having a V-groove, a first doped region positioned in the semiconductor substrate, two second doped regions positioned in the semiconductor substrate and at two sides of the V-groove, a dielectric stack having trapping sites interposed therein positioned on the V-groove, and a conductive layer positioned on the surface of the dielectric stack above the V-groove. A method for forming the V-groove comprises steps of forming a mask layer on the surface of the semiconductor substrate, forming an opening in the mask layer, etching a portion of the semiconductor substrate below the opening to form the V-groove, and removing the mask layer. The semiconductor substrate can be a (100)-oriented silicon substrate, and the V-groove has inclined surface planes with (111) orientation.

Abstract: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

Abstract: The present disclosure relates to a rapid thermal processing system that may be useful for processing semiconductor devices. A flash lamp may be utilized to provide pulse heating of a semiconductor for annealing or other purposes. A sensor may be provided to sense a characteristic of a semiconductor when a pre-pulse is applied to the semiconductor. Subsequent pulses may then be adjusted based on the characteristic sensed by the sensor.

Abstract: The method includes forming an isolation film on a silicon substrate to define an active region; forming an antireflective film on an entire surface of the substrate containing the isolation film; forming a photosensitive film pattern on the antireflective film while exposing a portion of the isolation film or the active region adjacent to the isolation film; etching the antireflective film, the isolation film, and the substrate by using the photosensitive film pattern as an etching mask to recess the active region; performing a light etch treatment on a substrate resultant without removing the remaining photosensitive film pattern, so as to remove a damaged layer and a carbon pollutant formed on a surface of the recessed active region; and removing the remaining photosensitive film pattern and the antireflective film.

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract: MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.

Abstract: The semiconductor device comprises gate electrodes 50 formed on a silicon substrate 32 with a gate insulation film 48 formed therebetween, source/drain diffused layers 66n, 66p formed in the silicon substrate 32 on both sides of the gate electrodes 50, a skirt-like insulation film 58 formed on a lower part of the side wall of the gate electrode 50 and on the side end of the gate insulation film 48, and a sidewall insulation film 60 formed on the exposed part of the side wall of the gate electrode 50, which is not covered with the skirt-like insulation film 58 and the side surface of the shirt-like insulation film 58.

Abstract: A method for manufacturing a dielectric thin film capacitor of the present invention includes the steps of coating a liquid raw material on a substrate and performing a first heat treatment to form an adhesive layer, forming a lower electrode on the adhesive layer, coating a liquid raw material on the lower electrode and performing a second heat treatment to form a dielectric thin film by crystallization, forming an upper electrode on the dielectric thin film, and performing a third heat treatment at a temperature higher than those of the first and second heat treatments. The adhesive layer and the dielectric thin film are formed by using materials having the same composition system or using the same material.

Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.

Abstract: Apparatus and method of providing a CMOS varactor device having improved linearity. At least two differential varactor elements are connected in parallel. Each of the differential elements includes first, second and third doped regions in a well. A first gate controls the first and second regions and a second gate controls the second and third regions. A resistor is formed such that power applied to the bulk region of the two differential elements will differ by the voltage drop across the resistor.

Abstract: An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.

Abstract: A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.

Abstract: A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current.

Abstract: The present invention provides an electrolytic capacitor that operates stably even when used for a long period of time under severe conditions, and forms an intermediate composition portion of metal and oxide within a chemical conversion film to a thickness of 40 nm or more so as to suppress the migration of oxygen atoms within a chemical conversion film of a valve metal. This intermediate composition portion is obtained by subjecting a base metal comprised by containing nitrogen in a valve action metal to anodic oxidation treatment.

Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.

Abstract: A method of forming a crack prevention ring at the exterior edge of an integrated circuit to prevent delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring may be formed simultaneously with the formation of test pads of the integrated circuits. The crack prevention ring may be partially or completely filled with conductive material. An air pocket may be formed within the crack prevention ring beneath a passivation layer of the integrated circuit. The crack prevention ring may be removed during the singulation process. An optional seal ring may be formed between the crack prevention ring and the integrated circuit.

Abstract: Disclosed herein are methods for forming photolithography alignment markers on the back side of a substrate, such as a crystalline silicon substrate used in the manufacture of semiconductor integrated circuits. According to the disclosed techniques, laser radiation is used to remove the material (e.g., silicon) from the back side of a substrate to form the back side alignment markers at specified areas. Such removal can comprise the use of laser ablation or laser-assisted etching. The substrate is placed on a motor-controlled substrate holding mechanism in a laser removal chamber, and the areas are automatically moved underneath the laser radiation to removal the material. The substrate holding mechanism can comprise a standard chuck (in which case use of a protective layer on the front side of the substrate is preferred), or a substrate clamping assembly which suspends the substrate at its edges (in which case the protective layer is not necessary).

Abstract: A method of forming a pre-metal dielectric (PMD) layer is disclosed. In the method, after a nitride liner layer is formed on a substrate having a transistor, a USG layer is deposited thereon and then planarized. Next, ion implantation and annealing are performed for gettering, first in a gate region and then in a non-gate region of the USG layer. The USG layer is generally free from plasma damage and has a good gap-fill capability. Further, ion implantation and annealing after deposition of the USG layer may enhance a gap-fill capability, a gettering capability, and electrical properties of a transistor.

Abstract: A low temperature process for depositing a coating containing any of silicon, nitrogen, hydrogen or oxygen on a workpiece includes placing the workpiece in a reactor chamber facing a processing region of the chamber, introducing a process gas containing any of silicon, nitrogen, hydrogen or oxygen into the reactor chamber, generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at an HF frequency on the order of about 10 MHz to a portion of a reentrant conduit external of the chamber and forming a portion of the reentrant path, applying RF plasma bias power at an LF frequency on the order of one or a few MHz to the workpiece, and maintaining the temperature of the workpiece under about 100 degrees C.

Abstract: The present invention provides a method for manufacturing a semiconductor device comprising an insulating layer that includes a seed layer formed on a silicon substrate. The seed layer is formed by exposing a hydrogen-terminated surface of the silicon substrate in a substantially oxygen-free environment to a seed layer precursor comprising a methylated metal. Forming the insulating layer further includes depositing a dielectric material on the seed layer.

Abstract: A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.

Abstract: An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.

Abstract: A method of making a semiconductor device by forming bumps on pads of a test piece. The method includes a fastening process of pouring a bump material including a liquid and a plurality of individual pump materials toward a target face of a mask substrate, the mask substrate having a plurality of holding holes, and making bump materials to become fastened to the holding holes; a removing process of removing the individual bump materials remaining on the target face from the target face; and a compression process of compressing the pads of the test piece from the side of the target face of the mask substrate toward the mask substrate so as to bond the individual bump materials onto the pads. By this method, micro bump materials can be accurately attached onto pads on a silicon wafer, or the like, and the size of the mask substrate can be easily increased.

Abstract: A bumping process mainly comprises the following steps. Initially, a wafer having a plurality of bonding pads and a passivation layer with passivation openings exposing the bonding pads is provided. Next, a first dielectric layer with first openings and second openings is disposed on the wafer. The first openings and second openings expose the bonding pads and the portions of the passivation layer respectively. Afterwards, a patterned first electrically conductive layer is formed over the first dielectric layer and the bonding pads. Then a second dielectric layer is formed over the first dielectric layer and the patterned first electrically conductive layer and exposes the patterned first conductive layer through the second openings to form a plurality of bump pads wherein the bump pads are electrically connected to bonding pads. Next, a second electrically conductive layer is formed over the second dielectric layer and the bump pads.

Abstract: A structure and method of fabricating a dual damascene interconnect structure, the structure including a dual damascene wire in a dielectric layer, the dual damascene wires extending a distance into the dielectric layer less than the thickness of the dielectric layer and dual damascene via bars integral with and extending from bottom surfaces of the dual damascene wires to a bottom surface of the dielectric layer.

Abstract: The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer.

Abstract: An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.

Abstract: A method of fabricating a printed wiring board comprising the following steps is provided. A portion of each of two dielectric layers or metal layers bonds to both sides of a carrier plate, respectively. Two build-up wiring structures are respectively formed on the dielectric layers or the metal layers by a build-up process. The portions of the dielectric layers or metal layers bonded to the carrier plate are removed such that the dielectric layers or metal layers and the build-up wiring structures formed thereon are released from the carrier plate to form two printed wiring boards.

Abstract: An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.

Abstract: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.

Abstract: A substrate processing method comprising steps for forming a copper film on a surface of a substrate. These steps includes the step of filling a first metal in the trenches so as to form a plated film of the first metal on an entire surface of the substrate by electroplating, wherein the electromagnetic field is adjusted by the virtual anode so that differences of thickness of the plated film between the central portion and the peripheral portion of the substrate being minimized, and polishing and removing the plated film by pressing the substrate to the polishing surface, wherein the pressures pressing the substrate to the polishing surface at a central portion and a peripheral portion are adjusted.

Abstract: A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

Abstract: A multi-layer semiconductor device including copper interconnects with improved interlayer adhesion and a method for forming the same, the method including providing a semiconductor substrate comprising a dielectric insulating layer comprising copper containing interconnects the dielectric insulating layer and copper containing interconnects comprising an exposed surface; forming a first capping layer on the exposed surface; providing a treatment on the first capping layer to increase interface adhesion between the capping layer and the dielectric insulating layer; and, forming a second capping layer on the first capping layer.

Abstract: Methods are provided for fabricating contacts in integrated circuit devices, such as phase-change memories. A protection layer and a sacrificial layer are sequentially formed on a semiconductor substrate. A contact hole is formed through the sacrificial layer and the protection layer. A conductive layer is formed on the sacrificial layer and in the contact hole, and portions of the conductive layer and the sacrificial layer are removed to expose the protection layer and form a conductive plug protruding from the protection layer. A protruding portion of the conductive plug removed to leave a contact plug in the protection layer. A phase-change data storage element may be formed on the contact plug.

Abstract: A method of depositing a metal cladding on conductors in a damascene process is described. The potential between, for instance, cobalt ions in electroless solution and the surface of an ILD between the conductors is adjusted so as to repel the metal from the ILD.

Abstract: Metal alloy barrier layers formed of a group VIII metal alloyed with boron (B) and/or phosphorous (P) and an at least one element from glyoxylic acid, such as carbon (C), hydrogen (H), or carbon and hydrogen (CH) formed by electoless plating are described. These barrier layers may be used as a barrier layer over copper bumps that are soldered to a tin-based solder in a die package. Such barrier layers may also be used as barrier layer liners within trenches in which copper interconnects or vias are formed and as capping layers over copper interconnects or vias to prevent the electromigration of copper.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A method of forming a structure, an array of structures and a memory cell, the method of fabricating a structure, including: (a) forming a trench in a substrate; (b) depositing a first layer of polysilicon on a surface of the substrate, the first layer of polysilicon filling the trench; (c) chemical-mechanical-polishing the first layer of polysilicon at a first temperature to expose the surface of the substrate; (d) removing an upper portion of the first polysilicon from the trench; (e) depositing a second layer of polysilicon on the surface of the substrate, the second layer of polysilicon filling the trench; and (f) chemical-mechanical-polishing the second layer of polysilicon at a second temperature to expose the surface of the substrate, the second temperature different from the first temperature.

Abstract: A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: A method and system for masking a surface to be etched is described. The method includes the operation of heating a phase-change masking material and using a droplet source to eject droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze after upon contact with the thin-film or substrate surface. The thin-film or substrate is then treated to alter the surface characteristics, typically by depositing a self assembled monolayer on the surface. After deposition, the masking material is removed. A material of interest is then deposited over the substrate such that the material adheres only to regions not originally covered by the mask such that the mask acts as a negative resist. Using such techniques, feature sizes of devices smaller than the smallest droplet printed may be fabricated.

Abstract: During microelectronic processing of a substrate, a gap on the substrate surface may be filled with a material by alternating deposition and etch processes while the substrate remains in the same process chamber. Alternating deposition and etch processes allows the gap to be completely filled absent a void.

Abstract: A method of manufacturing a semiconductor device includes first and second processes, the latter requiring more processing time. An apparatus for performing the semiconductor manufacturing process includes a first reactor, and a plurality of second reactors for each first reactor. A first group of wafers are subjected to the first process within the first reactor, and are then transferred into a second reactor as isolated from the outside air. The first group of wafers is subjected to the second process within the second reactor. At the same time, a second group of wafers are subjected to the first process within the first reactor. After the first process is completed, the second group of wafers is transferred into an unoccupied one of the second reactors as isolated from the outside air. There, the second group of wafers is subjected to the second process.

Abstract: In forming a mask pattern on a circuit board, a mask pattern of N-layer structure is formed in a region where the mechanical strength of the circuit board needs to be increased. N photosensitive layers are first stacked on a substrate so that they becomes lower in sensitivity from the first photosensitive layer toward the Nth photosensitive layer. In the first photosensitive layer (bottom layer), a first pattern is formed and has the same shape as a predetermined pattern to be formed on the circuit board. In the Kth photosensitive layer (N?K?2), a Kth pattern is formed so that the Kth pattern is smaller than a (K?1)st pattern formed in the (K?1)st photosensitive layer and arranged inside the (K?1)st pattern.

Abstract: A method of repairing damaged low-k dielectric materials is disclosed. Plasma-based processes, which are commonly used in semiconductor device manufacturing, frequently damage carbon-containing, low-k dielectric materials. Upon exposure to moisture, the damaged dielectric material may form silanol groups. In preferred embodiments, a two-step approach converts the silanol to a suitable organic group. The first step includes using a halogenating reagent to convert the silanol to a silicon halide. The second step includes using a derivatization reagent, preferably an organometallic compound, to replace the halide with the suitable organic group. In a preferred embodiment, the halogenating agent includes thionyl chloride and the organometallic compound includes an alkyllithium, preferably methyllithium. In another preferred embodiment, the organometallic compound comprises a Grignard reagent.