Abstract: A storage node having a metal-insulator-metal structure, a non-volatile memory device including a storage node having a metal-insulator-metal (MIM) structure and a method of operating the same are provided. The memory device may include a switching element and a storage node connected to the switching element. The storage node may include a first metal layer, a first insulating layer and a second metal layer, sequentially stacked, and a nano-structure layer. The storage node may further include a second insulating layer and a third metal layer. The nano-structure layer, which is used as a carbon nano-structure layer, may include at least one fullerene layer.

Abstract: In a circuit device having a field effect transistor and a capacitor, the capacitor is connected to at least one of a gate electrode, a source electrode and a drain electrode of a field effect transistor, the field effect transistor has a channel comprised of a first nano-wire, and the capacitor comprises a first electrode comprised of a second nano-wire having electroconductivity, a dielectric layer partly covering the peripheral face of the first electrode and a second electrode covering the peripheral face of the dielectric layer.

Abstract: A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.

Abstract: According to the invention, there is provided a nonvolatile semiconductor memory having: a floating gate electrode formed on a gate insulating film on an element region isolated by an element isolation region on a semiconductor substrate; an inter-gate insulating film formed to cover a portion from an upper surface to a middle of a side surface of the floating gate electrode; and a control gate electrode formed on the floating gate electrode via the inter-gate insulating film, wherein a portion from the upper surface of the floating gate electrode to at least a middle of the portion of the side surface which is covered with the inter-gate insulating film has a tapered shape largely inclined to a direction perpendicular to a surface of the semiconductor substrate, compared to the other portion of the side surface.

Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

Abstract: The present invention discloses a ROM memory cell that has significantly less total area than previously known ROM memory cells. Instead of using only one layer in the manufacturing process to program the memory cells, the present invention uses at least two layers to program the memory cells. This flexibility allows the memory cell to be reduced in area, which in turn produces a ROM that is more area efficient and consequently lower in cost. As the bitline length and capacitance are reduced, the speed and power consumption are also improved.

Abstract: A flash memory cell transistor is presented that includes a stacked structure of successively formed tunnel oxide layer, floating gate, inter-gate insulating layer and control gate on a semiconductor substrate, an insulating thin film formed on a first sidewall of the stacked structure, and an access gate formed on the first sidewall of the stacked structure while interposing the insulating thin film. A drain region is formed in a first region of the substrate in which the first region is exposed by the floating gate and a source region is formed in a second region of the substrate in which the second region is exposed by the access gate. The access gate overlaps, along the vertical direction of the stacked structure, the control gate and the floating gate.

Abstract: A semiconductor memory device having a stable characteristic and high reliability is achieved with formation of nano-dots with excellent interface stability. Source/drain diffusion layers are formed on a P-type silicon substrate to form a silicon oxide film. On this silicon oxide film, a silicon-rich oxide film is formed in a dot shape. On the silicon-rich oxide film, an interlayer dielectric made of SiO2 is formed. The silicon-rich oxide film has a property of storing charges in the film and excellent in stability of an interface with a silicon oxide film used for a tunneling dielectric. With this, a semiconductor memory device having a stable characteristic and high reliability is achieved with formation of nano-dots with excellent interface stability.

Abstract: A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and patterning the word gate poly layer and the first dielectric layer to form an array of word gate structures. The method further includes forming a poly plug layer and patterning the poly plug layer to form a plurality of poly plugs surrounded in the plane of the substrate on three sides, forming a plurality of control gates, forming a second dielectric layer, planarizing the second dielectric layer using a chemical-mechanical polishing process, and depositing a metal layer to provide electrical contact to the word gate structures.

Abstract: A memory array having a smaller active area pitch is provided. In accordance with embodiments of the present invention, active regions are formed in a substrate and transistors are formed between adjacent active regions such that the active regions form the source/drain regions of the transistors. Word lines are formed perpendicular to the active regions and are electrically coupled to the gates of the transistors. Bit lines may be formed over the active regions to provide electrical contacts to the source/drain regions. In an embodiment, the word lines may be formed of poly-silicon over a layer of dielectric material formed over the transistors. In this embodiment, the bit lines may be formed on the metal layers. The word lines and dielectric layer may have a planar or non-planar surface.

Abstract: A nonvolatile memory device that effectively prevents the occurrence of the hump phenomenon as well as a manufacturing method for fabricating the same, is presented. In one embodiment, the nonvolatile memory device includes an insulating spacer formed at interface between the active region and isolation layer, and a charge trapping dielectric layer that is formed in the active region between the neighboring two insulating spacers. The device also includes a gate electrode layer formed on the charge trapping dielectric layer and a source and drain formed in the active region at both sides of the gate electrode layer.

Abstract: The invention relates to a trench MOSFET with drain (8), drift (10) body (12) and source (14) regions. The drift region is doped to have a high concentration gradient. A field plate electrode (34) is provided adjacent to the drift region (10) and a gate electrode (32) next to the body region (12).

Abstract: A trench structure semiconductor device is disclosed. In one embodiment, field electrode devices are arranged in a trench structure, in direct spatial proximity in comparison with essentially planar or smooth conditions, have an enlarged common interface region with an insulation material in between, whereby a comparatively stronger electrical coupling of the directly adjacent field electrode devices is achieved.

Abstract: In a lateral DMOS device which has a drain diffusion region, an insulator is provided on the drain diffusion region. The insulator is helpful to reduce the lateral electric field under silicon surface. The gate of the DMOS does not overlap with the insulator over the drain diffusion region such that the lateral DMOS device is insensitive to oxide corner loss.

Abstract: It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle ? (0° <?<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more.

Abstract: An object is to provide a semiconductor device which includes an anti-collision function during or after production of an IC chip just by a change of a program, even when there is a change of a specification of a product accompanying a change of the kind or standard of a signal of a wireless means for each product. A semiconductor device includes an arithmetic circuit and a circuit for transmitting/receiving a signal to/from outside. The arithmetic circuit includes a central processing unit, a random access memory, a read only memory, and a controller. The read only memory stores a program for processing collision avoidance in transmitting/receiving the signal to/from outside. The program is executed in the central processing unit, so that the arithmetic circuit processes collision avoidance.

Abstract: A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled between the supply source and the complementary supply source. The cell further includes a first pass-gate and second pass-gate transistors coupled to the first and second inverters, respectively. The first pass-gate transistor and the first pull-up transistor are respectively constructed on a first P-type well and a first N-type well adjacent to one another, which are overlaid by a first doped region and a second doped region of substantially the same width in alignment with one another, respectively.

Abstract: A four terminal field effect device comprises a silicon field effect device with a silicon N-type semiconductor channel and an N+ source and drain region. An insulator is deposited over the N-type semiconductor channel. An organic semiconductor material is deposited over the insulator gate forming a organic semiconductor channel and is exposed to the ambient environment. Drain and source electrodes are deposited and electrically couple to respective ends of the organic semiconductor channel. The two independent source electrodes and the two independent drain electrodes form the four terminals of the new field effect device. The organic semiconductor channel may be charged and discharged electrically and have its charge modified in response to chemicals in the ambient environment. The conductivity of silicon semiconductor channel is modulated by induced charges in the common gate in response to charges in the organic semiconductor channel.

Abstract: A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.

Abstract: A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller than that of the silicide gate electrode of the n-type MISFET, the silicide gate electrode of the p-type MISFET having a ratio of metal content higher than that of the silicide gate electrode of the n-type MISFET.

Abstract: An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

Abstract: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same.

Abstract: A semiconductor cell and a semiconductor circuit utilizing semiconductor cells. The semiconductor cell includes a rectangular boundary and a power layout, where the power layout does not contact any pair of opposite sides of the rectangular boundary. Additionally, the semiconductor circuit includes a plurality of semiconductor cells. Each semiconductor cell includes a rectangular boundary and a power layout, where the power layout does not contact any pair of opposite sides of the rectangular boundary. Because conventional power strips are avoided, the present invention can reduce height of each semiconductor cell, and therefore increase integration of the semiconductor circuit (i.e., the integrated circuit).

Abstract: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.

Abstract: The microcavity is delineated by a cover which is formed on a sacrificial layer and in which at least one hole is formed for removal of the sacrificial layer. A plug covers the hole and part of the cover along the periphery of the hole. The plug is made from a material that can undergo creep deformation and can be a polymerized material, in particular selected from photoresists and polyimide, or glass, in particular selected from phosphosilicate glasses. A sealing layer is deposited on the plug and the cover such as to seal the microcavity hermetically. The hole has, for example, a dimension of less than 5 micrometers and is preferably arranged on the highest part of the microcavity. The plug can have a thickness of between 2 and 6 micrometers.

Abstract: A micromechanical device and a method for producing this device are provided, the device having a sensor pattern that includes a spring pattern and a seismic mass. The seismic mass may be connected to the substrate material via the spring pattern, and a clearance may be provided in a direction perpendicular to the major substrate plane between the spring pattern and the substrate material. Alternatively, the spring pattern and the seismic mass may have a common, essentially continuous, front side surface.

Abstract: A semiconductor device is provided with a main electrode of main switching elements region, a sensor electrode of sensor switching elements region, and a protective device formed between the main electrode and the sensor electrode. The protective device electrically connects the main electrode and the sensor electrode when a predetermined potential difference is produced between the main electrode and the sensor electrode. The semiconductor device can handle excessive voltage such as ESD generated between the sensor electrode and the gate electrode while simultaneously preventing gate drive loss from increasing.

Abstract: A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.

Abstract: Improved SAW pressure sensors and manufacturing methods thereof. A SAW wafer including a number of SAW transducers disposed thereon may be provided. A cover wafer may also be provided, with a glass wall situated between the cover wafer and the SAW wafer. The cover wafer may be secured to the SAW wafer such that the glass wall surrounds the SAW transducers. In some instances, the glass wall may define, at least in part, a separation between the cover wafer and the SAW wafer. One or more contours may also be provided between the cover wafer and the SAW wafer such that at least one of the contours surrounds at least one of the SAW transducers when the cover wafer is disposed over and secured relative to the SAW wafer.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: An optical sheet includes an substrate having a first surface and a second surface opposite to the first surface, a light gathering layer formed on the first surface of the substrate, and an light diffusion layer formed on the second surface of the substrate. The light diffusion layer includes a polymeric resin having a plurality of bubbles mixed therein. The optical sheet of the subject invention can be used in LCDs as a photo-diffusive brightness enhancement film.

Abstract: A method for packaging an semiconductor device includes following steps. First, a first substrate including at least one first pattern is provided. At least one semiconductor device is disposed on the surface of the first substrate. Next, a spacer with at least one aperture and at least one through hole is provided. Then, the first pattern is aimed at the through hole to connect the first substrate and the spacer, so that the semiconductor device is positioned correspondingly to the aperture. Afterwards, a second substrate including at least one second pattern is provided. Thereon, the second pattern is aimed at the through hole, so that the second substrate is connected to the spacer correspondingly.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.

Abstract: A semiconductor device includes an interlayer insulating film on a substrate. A runner part includes a plurality of runner lines spaced apart from each other by a regular interval under the interlayer insulating film. A fuse cut part includes a plurality of fuse lines spaced apart from each other by a wider interval than the interval between the runner lines. A via in the interlayer insulating film connects a fuse line and a runner line to each other.

Abstract: An interdigitized capacitor comprising first and second electrodes. The first electrode comprises two combs symmetrical to a first mirror plane. The fingers of the combs extend toward the first mirror plane. The second electrode comprises two combs and a linear plate. The combs are symmetrical to a second mirror plane and the fingers thereof extend toward the second mirror plane. The linear plate is located at the second mirror plane and connected to one finger of the combs of the second electrode. The first and second mirror planes are orthogonal. The fingers of the combs of the first and second electrodes are interdigitized.

Abstract: A capacitor comprises a first electrode comprised of an electroconductive nano-wire, a dielectric layer partly covering the peripheral face of the first electrode, and a second electrode covering the peripheral face of the dielectric layer. In a circuit device employing the capacitor, a plurality of the capacitors are arranged roughly perpendicularly to a substrate comprised in the circuit device or in parallel to a substrate comprised in the circuit device.

Abstract: The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends between the first STI region and the collection region and undercuts a portion of the active base region with an undercut angle of not more than about 90°. For example, the second STI region may a substantially triangular cross-section with an undercut angle of less than about 90°, or a substantially rectangular cross-section with an undercut angle of about 90°. Such a second STI region can be fabricated using a porous surface section formed in an upper surface of the collector region.

Abstract: A digital camera module (200) includes a carrier (20), an image sensor chip (30), a number of wires (50), a holder (60), and a lens module (70). The carrier includes a base (21) and a leadframe (23) embedded in the base. The base includes a board (211), a sidewall (213) and a cavity (24). The leadframe includes a number of conductive leads (233) spaced from each other. Each lead has a first terminal portion (235), a second terminal portion (236), and an interconnecting portion (237) connecting the first and second terminal portions. The chip is mounted on the carrier, and has an active area (301). The wires electrically connect the chip and the leadframe. The holder is mounted to the carrier to close the cavity. The lens module is received in the holder and guides light to the active area of the chip.

Abstract: A task is to provide a simple method for obtaining a bipolar transistor being free of current gain dispersion and having a lowered base resistance. The method of the present invention comprises forming a base layer on a semiconductor substrate, and then forming in an insulating film stacked on the base layer a base electrode lead opening and an emitter electrode lead opening at the same time, and subsequently forming a base electrode lead portion and an emitter electrode lead portion in, respectively, the base electrode lead opening and the emitter electrode lead opening.

Abstract: The semiconductor device provided assures stable communication processes. For example, a varactor diode for adjusting the reference frequency is comprised within a digital crystal-controlled oscillating circuit provided as an internal circuit of the front-end circuit for generating the reference oscillation signal of a PLL circuit or the like. The varactor diode is formed to a semiconductor layer DF of the so-called SOI structure in the structure where an embedded insulating layer, a n?type semiconductor region, a p type semiconductor region, and a n+ type semiconductor region are formed in this sequence and the n+ type semiconductor region is connected to a cathode node which becomes the frequency adjusting node. Moreover, a p+ type semiconductor region connected to the p type semiconductor region is formed in both sides of the n+ type semiconductor region, and this p+ type semiconductor region is connected to an anode node to which the ground voltage is applied.

Abstract: Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The first conductive layer may be formed at the first level, while the second conductive layer may be formed at a different level. For a laser repair method, a target region may be divided into sub-regions. In one selected sub-region, the fuse focus detector may be laser scanned in a direction for a reflection light measurement providing information on a thickness of the fuse focus detector. Using the thickness information, a focus offset value of a fuse in the selected sub-region may be calculated. When the focus offset value is within an allowable range, fuse cutting may be performed.

Abstract: A semiconductor device includes an interconnect member, a first semiconductor chip, a second semiconductor chip, a resin layer, an inorganic insulating layer, and a through electrode. The first semiconductor chip is mounted in a face-down manner on the interconnect member. The resin layer covers the side surface of the first semiconductor chip. This inorganic insulating layer is in contact with the back surface of the first semiconductor chip, and directly covers the back surface. Also, the inorganic insulating layer extends over the resin layer. The through electrode penetrates the inorganic insulating layer and the semiconductor substrate of the first semiconductor chip. The second semiconductor chip is mounted in a face-down manner on the inorganic insulating layer that covers the back surface of the first semiconductor chip in the uppermost layer.

Abstract: A semiconductor device is provided with a semiconductor substrate having circuit elements formed therein, and an insulating protective film formed on the semiconductor substrate. Hydroxyl groups (OH) are attached to a surface of the protective film. As a result, the contact angle between surface of the protective film and a water droplet is less than or equal to 40 degrees.

Abstract: An electronic component includes a package having a cavity formed therein by providing an annular protrusion on a substrate as well as having a metallized layer on a bottom surface of the cavity, and an element disposed on the bottom surface of the cavity via the metallized layer and housed in the cavity, wherein the element has an electrode formed on a surface opposite to a surface which touches the bottom surface of the cavity when the element is disposed on the bottom surface, wherein, in the cavity, an internal electrode to be an electrical connecting destination of the electrode on the element is formed at opposed positions with the element between the positions in a first direction, in which the electrode lies between the positions when seen from the top, in such a manner that there is clearance between the internal electrode and the element, and wherein, on the bottom surface of the cavity, an distinction mark, which is distinguished from the metallized layer, is formed at opposed positions with the el

Abstract: A sensor package apparatus includes a lead frame substrate that supports one or more electrical components, which are connected to and located on the lead frame substrate. A plurality of wire bonds are also provided, which electrically connect the electrical components to the lead frame substrate, wherein the lead frame substrate is encapsulated by a thermoset plastic to protect the plurality of wire bonds and at least one electrical component, thereby providing a sensor package apparatus comprising the lead frame substrate, the electrical component(s), and the wire bonds, while eliminating a need for a Printed Circuit Board (PCB) or a ceramic substrate in place of the lead frame substrate as a part of the sensor package apparatus. A conductive epoxy can also be provided for maintaining a connection of the electrical component(s) to the lead frame substrate. The electrical components can constitute, for example, an IC chip and/or a sensing element (e.g., a magnetoresistive component) or sense die.

Abstract: A lead frame comprises a stage for mounting a semiconductor chip thereon, a plurality of leads arranged in the periphery of the stage, and a plurality of lead interconnection members (e.g., dam bars) for interconnecting the leads, wherein a plurality of through holes are formed to penetrate through the lead frame in a thickness direction with respect to the leads or the lead interconnection members so as to allow a plurality of cutting lines to pass therethrough, whereby the leads are subjected to cutting and are made electrically independent of each other. A semiconductor package of a QFN type is produced by enclosing the lead frame within a molded resin, from which the leads are partially exposed to the exterior and are subjected to plating and are then subjected to cutting at the cutting lines.

Abstract: Heat dissipation, is improved, of a semiconductor device on a tape carrier package, in which the number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration and narrower pitches are employed. There are included a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns are formed.

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire.

Abstract: A package to encase a semiconductor package is manufactured by the following steps. First, an electrically conductive frame is provided. This frame has a plurality of leadframes arranged in a matrix with each leadframe having a plurality of spaced leads extending outwardly from a central aperture. The electrically conductive frame further includes a plurality of connecting bars joining outer end portions of adjacent ones of the leadframes. Second, a groove is formed in the connecting bars to form a reduced thickness portion between the outer end portions of adjacent ones of the leadframes. Third, a semiconductor device is electrically coupled to inner portions of said leads. Fourth, the frame and the semiconductor devices are encapsulated in a molding compound. Finally, the molding compound and the frame are cut along the grooves to form singulated semiconductor packages having outer lead portions with a height greater than the height of the reduced thickness portion.