Abstract: An anti-reversing pawl mechanism is claimed that includes a pawl that is engaged by a flexible coupling but that is also biased toward a driven member such that when the engagement of the flexible coupling is removed, the pawl engages the driven member and stops it from moving.

Abstract: A system, apparatus and method for shielding an area from wind is shown. The system, apparatus and method comprise at least one or a plurality of windscreens that yield to a wind to facilitate or reducing or eliminating stresses or forces on a fence to which the at least one or a plurality of windscreens are attached.

Abstract: A structure using integrated optical elements is comprised of a substrate, a buffer layer grown on the substrate, one or more first patterned layers deposited on top of the buffer layer, wherein each of the first patterned layers is comprised of a bottom lateral epitaxial overgrowth (LEO) mask layer and a LEO nitride layer filling holes in the bottom LEO mask layer, one or more active layers formed on the first patterned layers, and one or more second patterned layers deposited on top of the active layer, wherein each of the second patterned layers is comprised of a top LEO mask layer and a LEO nitride layer filling holes in the top LEO mask layer, wherein the top and/or bottom LEO mask layers act as a mirror, optical confinement layer, grating, wavelength selective element, beam shaping element or beam directing element for the active layers.

Abstract: A crystal foundation having dislocations is used to obtain a crystal film of low dislocation density, a crystal substrate, and a semiconductor device. One side of a growth substrate (11) is provided with a crystal layer (13) with a buffer layer (12) in between. The crystal layer (13) has spaces (13a), (13b) in an end of each threading dislocation D1 elongating from below. The threading dislocation D1 is separated from the upper layer by the spaces (13a), (13b), so that each threading dislocation D1 is blocked from propagating to the upper layer. When the displacement of the threading dislocation D1 expressed by Burgers vector is preserved to develop another dislocation, the spaces (13a), (13b) vary the direction of its displacement. As a result, the upper layer above the spaces (13a), (13b) turns crystalline with a low dislocation density.

Abstract: Provided are a light-controlling structure having a simple structure and a short response time and a display device employing the structure, wherein the structure includes a first electrode; a second electrode which is disposed apart from the first electrode; at least one heat-emitting unit which is electrically connected to the first and second electrodes; and a phase change material, of which light permeability changes according to temperature, which is disposed to contact the heat-emitting unit.

Abstract: A method of forming a powder and/or discrete gel particles of a compound selected from the group of a metallic oxide, a metalloid oxide, a mixed oxide, an organometallic oxide, an organometalloid oxide, an organomixed oxide resin, and/or an organic resin from one or more respective organometallic precursor(s), organometalloid precursor(s) and/or organic precursors and mixtures thereof, comprising the steps of passing a gas into a means for forming excited and/or unstable gas species (1a), typically an atmospheric plasma generating means; treating said gas such that upon leaving said means the gas comprises excited and/or unstable gas species which are substantially free of electrical charges at a temperature of between 10° C. and 500° C. A gaseous and/or liquid precursor is then introduced (50a,50b) into said excited and unstable gas species in a downstream region external (20) to the means for forming excited and/or unstable gas.

Abstract: Configurable power segmentation using a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer in an integrated circuit, and coupling a power region in the transistor layer to at least one power source based on a state of the nanotube structure. Nanotube material may be sputtered over a plurality of layers to form the nanotube structure. The nanotube structure may be curved to flex to a conductive surface when a current is applied to the nanotube structure. The power region may be coupled with at least two power sources that are concatenated together to provide cascaded current to the power region. One or more power regions in the integrated circuit may be enable based on the patterning the nanotube structure and the coupling of the power region to at least one power source.

Abstract: An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilcon layer to form a polysilicon channel layer.

Abstract: An organic semiconductor device and a method of fabricating the same are provided. The device includes: a first electrode; an electron channel layer formed on the first electrode; and a second electrode formed on the electron channel layer, wherein the electron channel layer comprises: a lower organic layer formed on the first electrode; a nano-particle layer formed on the lower organic layer and including predetermined sizes of nano-particles that are spaced a predetermined distance apart from each other; and an upper organic layer formed over the nano-particle layer. Accordingly, a highly integrated organic semiconductor device can be fabricated by a simple fabrication process, and nonuniformity of devices due to threshold voltage characteristics and downsizing of the device can resolved, so that a semiconductor device having excellent performance can be implemented.

Abstract: A thin-film transistor includes a gate electrode, a source electrode, a drain electrode, a semiconductor layer, and a gate insulating layer for insulating the source electrode and the drain electrode from the gate electrode, wherein the gate insulating layer includes composite particles in which a hydrophobic compound is provided on the surfaces of insulating inorganic particles.

Abstract: The present method prevents malfunctions in switching caused by a light leakage current in an active matrix type thin film transistor substrate for a liquid crystal display and prevents display failures, by selectively disposing a self assembled monolayer film in a gate electrode-projected region of the surface of an insulator film with high definition, and by selectively improving the orientation order of an organic semiconductor film only in the gate electrode-projected region without improving the order at an irradiated portion with light outside the gate electrode-projected region.

Abstract: Solid-state area illumination stems and method for forming such systems are provided. The illumination system comprises: a plurality of OLED devices each device formed on a separate substrate and each device emitting light at a plurality of angles relative to the substrate, the emitted light having different ranges of frequencies at different ranges of the plurality of angles; and a support positioning each of the plurality of OLED devices at a plurality of orientations relative to an area of illumination, the positioning being defined so that any point on any surface within the area of illumination will receive a broadband combination of light from more than one of the OLED devices.

Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.

Abstract: A display includes a thin film transistor, a repair structure for repairing a defect in a signal line coupled to the thin film transistor, the repair structure including a first repair metal layer and a second repair metal layer. The transistor includes a gate electrode, a source electrode, and a drain electrode. A dielectric layer is disposed above the thin film transistor and the repair structure, the dielectric layer defining a repair opening to expose the second repair metal layer, the dielectric layer also defining a contact window that exposes at least one of the source and drain electrodes. A floating electrode is electrically connected to the second repair metal layer through the repair opening, the floating electrode being electrically floated.

Abstract: A SiC semiconductor device and method of fabricating a SiC semiconductor device is provided. The method includes forming a source region and a drain region over a silicon carbide layer which is activated at a high temperature. A gate oxide layer is formed over the silicon carbide layer and is ion-implanted with an atomic species. In another method the gate oxide layer has a thickness of less than about 200 nm.

Abstract: An object of the present invention is to provide a flip-chip-type gallium nitride compound semiconductor light-emitting device exhibiting excellent ohmic characteristics, excellent bonding characteristics, and high emission output. The inventive flip-chip-type gallium nitride compound semiconductor light-emitting device comprises a positive electrode which has a three-layer structure comprising an ohmic electrode layer composed of rhodium which is in contact with the p-type semiconductor layer, an adhesion layer composed of titanium which is provided on the ohmic electrode layer and has a thickness of 10 ? or more, and a bonding pad layer provided on the adhesion layer and being composed of a metal selected from the group consisting of gold, aluminum, nickel, and copper, or composed of an alloy containing at least one of these metals.

Abstract: An object of the present invention is to provide a Group III nitride semiconductor element which comprises a thick AlGaN layer exhibiting high crystallinity and containing no cracks, and which does not include a thick GaN layer (which generally serves as a light-absorbing layer in an ultraviolet LED). The inventive Group III nitride semiconductor element comprises a substrate; a first nitride semiconductor layer composed of AlN which is provided on the substrate; a second nitride semiconductor layer composed of Alx1Ga1-x1N (0?x1?0.1) which is provided on the first nitride semiconductor layer; and a third nitride semiconductor layer composed of Alx2Ga1-x2N (0<x2<1 and x1+0.02?x2) which is provided on the second nitride semiconductor layer.

Abstract: A microlens structure is mounted directly onto the upper surface of a packaged VCSEL device and positioned to locate microlenses directly over corresponding VCSEL elements. The microlens structure includes a block-like pedestal having a lower surface that faces the upper surface of the VSCEL device. The microlenses are formed in a central region of the lower surface, and several legs (stand-offs) extend from peripheral edges of the lower surface. During assembly, the VCSEL device is positioned under the microlens structure such that each microlens is aligned over its corresponding VCSEL element, and then raised until the legs contact the upper surface of the VCSEL device. The legs serve to self-align the microlenses to the VCSEL device, and are sized to maintain an optimal distance between the microlenses and the VCSEL elements. The pedestal is attached to a carrier plate that is secured to an IC package housing the VCSEL device.

Abstract: The present invention relates to a white light emitting diode comprising a blue light emitting diode chip; a green light emitting diode chip; and a molding member that encapsulates the blue light emitting diode chip and a green light emitting diode chip, the molding member containing a red fluorescent substance.

Abstract: A combined thickness of an optical distance between an anode and a cathode together with a red-light-emitting layer, a blue-light-emitting layer, and the like of a light-emitting element and the anode is set to a thickness by which red and blue light can be intensified by interference. Thus, light of necessary wavelength can be intensified, and white light can be extracted efficiently.

Abstract: A light emitting device and a method for fabricating the same are disclosed, whereby a thin mask film is changed to agglomerates by a simple thermal treatment process, and a plurality of nano openings, each opening spaced a distance apart, are formed in the agglomerates, a light emitting structure exposed to the nano openings is etched to form nano grooves and nano openings therein, enabling to enhance a light emitting area and to reduce the totally reflected light for an improvement of the light extraction efficiency.

Abstract: A method for manufacturing a light-emitting element with a heterojunction of group IV is provided. The method comprises at least the steps of: (1) providing a silicon substrate having a first and a second surfaces; (2) forming a germanium layer on the first surface; (3) forming a cap layer on the germanium layer; (4) forming a oxidation layer on the cap layer; (5) forming a first conductive layer on the oxidation layer; (6) forming a second conductive layer on the second surface; and (7) respectively forming a conductive wire on the first and second conductive layers. The light-emitting element of MOS semiconductor manufactured by the abovementioned steps is characterized in the emission of long wavelength.

Abstract: A semi-insulating zinc-oxide (ZnO) single crystal. The crystal has resistivity of at least 1.5×103 ohm-centimeter (?-cm). The ZnO crystal can be produced from a melt contained by solid-phase ZnO to prevent introduction of undesired impurities into the crystal. The crystal can be a bulk single crystal that is cut and processed into wafer form of specified thickness. A dopant in a concentration ranging from 1×1015 atoms per cubic centimeter (atoms/cc) to 5×1021 atoms/cc can increase resistivity of the crystal relative to intrinsic ZnO. The dopant can be lithium (Li), sodium (Na), copper (Cu), nitrogen (N), phosphorus (P), and/or manganese (Mn).

Abstract: A flip-chip LED including a light emitting structure, a first dielectric layer, a first metal layer, a second metal layer, and a second dielectric layer is provided. The light emitting structure includes a first conductive layer, an active layer, and a second conductive layer. The active layer is disposed on the first conductive layer, and the second conductive layer is disposed on the active layer. The first metal layer is disposed on the light emitting structure and is contact with the first conductive layer, and part of the first metal layer is disposed on the first dielectric layer. The second metal layer is disposed on the light emitting structure and is in contact with the second conductive layer, and part of the second metal layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The first conductive layer includes a rough surface so as to improve a light extraction efficiency.

Abstract: A semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is attached to a compound substrate including a host which provides mechanical support to the device and a ceramic layer including a luminescent material. In some embodiments the compound substrate includes a crystalline seed layer on which the semiconductor structure is grown. The ceramic layer is disposed between the seed layer and the host. In some embodiments, the compound substrate is attached to the semiconductor structure compound substrate is spaced apart from the semiconductor structure and does not provide mechanical support to the structure. In some embodiments, the ceramic layer has a thickness less than 500 ?m.

Abstract: A voltage switchable dielectric material (VSD) material as part of a light-emitting component, including LEDs and OLEDs.

Abstract: A light emitting element (100) comprising an element chip (100C) provided, at least in a partial section in the thickness direction thereof, with a part of reduced cross-section where the cross sectional area decreases continuously or stepwise in the direction perpendicular to the thickness direction from the first major surface side toward the second major surface side. A part of a molded section (25) has a first mold layer (26) covering at least the part of reduced cross-section, and a second mold layer (25m) covering the outside of the first mold layer (26), wherein the first mold layer (26) is composed of a polymer mold material softer than that of the second mold layer (25m). A light emitting element, having such a structure that the element chip bonded onto a metal stage is not stripped easily even if mold resin expands, is thereby provided.

Abstract: A packaging structure and a related fabrication method for high-power LED chip are provided herein, which mainly contains a base made of a metallic material and an electrically insulating material integrated into a single object. The metallic material forms a heat sinking seat in the middle of the base, which is exposed from the top surface of the base, and from the bottom surface or a side surface of the base. The metallic material also forms a plurality of electrodes surrounding the heat sinking seat, which are exposed from the top surface of the base, and from the bottom surface or a side surface of the base, respectively. The electrically insulating material is interposed between the electrodes and the heat sinking seat so that they are adhere together, and so that the heat sinking seat and any one of the electrodes, and any two electrodes are electrically insulated.

Abstract: Layered and film structures for improving the performance of semiconductor devices include single and multiple quantum wells and double heterostructures and superlattice structures.

Abstract: A vertical GaN-based LED and a method of manufacturing the same are provided. The vertical GaN-based LED can prevent the damage of an n-type GaN layer contacting an n-type electrode, thereby stably securing the contact resistance of the n-electrode. The vertical GaN-based LED includes: a support layer; a p-electrode formed on the support layer; a p-type GaN layer formed on the p-electrode; an active layer formed on the p-type GaN layer; an n-type GaN layer for an n-type electrode contact, formed on the active layer; an etch stop layer formed on the n-type GaN layer to expose a portion of the n-type GaN layer; and an n-electrode formed on the n-type GaN layer exposed by the etch stop layer.

Abstract: Lateral epitaxial overgrowth (LEO) of non-polar gallium nitride (GaN) films results in significantly reduced defect density.

Abstract: An over-voltage protection device includes a substrate including an upper surface and a lower surface; a first electrode provided on the upper surface of the substrate; a second electrode provided on the lower surface on the substrate; a first conductive layer overlying the lower surface of the substrate, the first conductive region being a conductive region of a first type; a plurality of first conductive regions provided proximate the upper surface of the substrate, the plurality of first conductive regions being conductive regions of the first type; and a plurality of second conductive region provided proximate the upper surface of the substrate, the plurality of second conductive region being conductive regions of a second type. The plurality of the first conductive regions are provided in an alternating manner with the plurality of second conductive regions. The first electrode is contacting the plurality of the first and second conductive regions.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of first wirings disposed above the semiconductor substrate along a first direction, a diffusion layer that is disposed on the surface of the semiconductor substrate so as to extend along a second direction perpendicular to the first direction and which includes a plurality of first diffusion portions overlapping with the plurality of first wirings, a first conductive film that is disposed between adjacent first diffusion layer portions of the plurality of the first diffusion layer portions disposed along the plurality of first wirings, respectively, in a layer between the semiconductor substrate and the plurality of first wirings, and electrically coupled to the plurality of first wirings, a plurality of sidewall portions, each of which is formed on a lateral side of the first conductive film to be disposed between the first conductive film and its adjacent first diffusion layer portion so as to extend along the diffusion layer, and a sec

Abstract: A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode, and a gate electrode formed on the second group-III nitride semiconductor layer, the gate electrode controlling a current flowing between the source and drain electrodes; and a heat radiation film with high thermal conductivity which covers, as a surface passivation film, the entire surface other than a bonding pad.

Abstract: To provide a superluminescent diode capable of emitting high output super luminescent light having a central wavelength within a range of 0.95 ?m to 1.2 ?m and an undistorted beam cross section, having a long element life. The super luminescent diode is constituted by: an n-type GaAs substrate; an optical waveguide path constituted by an InGaAs active layer that emits light having a central wavelength within a range of 0.95 ?m to 1.2 ?m, formed on the GaAs substrate; and a window region layer having a greater energy gap and a smaller refractive index than the active layer, constituted by p-type GaAs that lattice matches with the GaAs substrate, provided at a rear emitting facet of the optical waveguide path. The p-type GaAs window region layer has a favorable crystal membrane with the InGaAs active layer that emits light having the central wavelength within the range of 0.95 ?m to 1.2 ?m, which does not deteriorate.

Abstract: A plug is formed by depositing a first material to partially fill an opening, leaving an unfilled portion with a lower aspect ratio than the original opening. A second material is then deposited to fill the remaining portion of the opening. The first material has good filling characteristics but has higher resistivity than the second material. The second material has low resistivity to give the plug low resistance.

Abstract: An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of the integrated circuit device. A buffer pattern is provided between the integrated circuit substrate and the window layer and a fuse pattern is provided between the buffer pattern and the window layer. Methods of forming integrated circuit devices are also described.

Abstract: Disclosed herein is a semiconductor device including: a semiconductor chip; a first insulating layer covering the semiconductor chip in a condition where at least a portion of a terminal electrode of the semiconductor chip is exposed; a second insulating layer formed over the first insulating layer; and a rewiring layer extracting the terminal electrode of the semiconductor chip via the second insulating layer to a position of connection with an external circuit; wherein an underlying layer for plating connected with the terminal electrode is provided in an existing area of the terminal electrode alone or in a region covering from the existing area to above the first insulating layer, and at least a part of the rewiring layer is formed of a plated layer formed on the underlying layer.

Abstract: Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-type impurity-implanted region, a gate insulating layer, and a gate electrode. The P-type FET includes P-type impurity diffusion layers, an N-type impurity-implanted region, a gate insulating layer, and a gate electrode. The capacitor includes N-type impurity diffusion layers, an N-type impurity-implanted region, a capacitance insulating layer, and an upper electrode. The capacitor includes P-type impurity diffusion layers, a P-type impurity-implanted region, a capacitance insulating layer, and an upper electrode.

Abstract: The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.

Abstract: A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.

Abstract: An opening 35 is formed on an assembly having a silicon germanium layer 32, a silicon layer 33, and a silicon oxide layer 34 sequentially formed on a silicon basis material 31. An additional silicon oxide layer 36 is formed so as to cover the silicon oxide layer 34 and an inner surface of the opening 35. Then, the silicon germanium layer 32 is removed by etching, and a thermal oxidation treatment and an annealing treatment are sequentially performed on the silicon basis material 31 and the silicon layer 33 to form thermal oxidation layers 37 and 38. Then, a flat film 39 is formed for flat treatment to manufacture a semiconductor substrate 10 having an island part 12 made of silicon buried in an component 13 made of silicon oxide.

Abstract: The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate (700) as well as at least one improved structure (702) capable of forming one or more transistor channels. This structure, formed by a plurality of bars stacked on the substrate, can make it possible to save space in the integration of field-effect transistors as well as to improve the performance thereof.

Abstract: A semiconductor device is configured so that there is formed a stressor film 4 covering the first field effect transistor and the second field effect transistor, formed with openings from which the originating area and the terminating area of each of the first field effect transistor and the second field effect transistor are partially exposed, and applying a stress to at least an area extending from the vicinity of the originating area to the vicinity of the terminating area of each of the first field effect transistor and the second field effect transistor, and that a height of a first gate electrode 3 (3A) in a direction substantially perpendicular to a first insulating layer is set different from a height of a second electrode 3 (3B) in the direction substantially perpendicular to a second insulating layer.

Abstract: An electric device having a plurality of nanowires, in which at least one of the nanowires is cut or changed in its electric characteristics so as to have a desired characteristic value of the electric device.

Abstract: In a semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET) is formed in a semiconductor substrate, and an isolation layer is formed on the semiconductor substrate so as to extend along a side of the semiconductor substrate. A first conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a gate of the MOSFET. A second conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a drain of the MOSFET. A protection circuit is made of at least two diodes which are defined between the first conductive layer and the second conductive layer.

Abstract: A 3Tr-operated CMOS solid-state imaging apparatus comprises a plurality of pixels including adjacent first and second pixels 230 and 231 including photodiodes 201 for converting light into signal charges and transfer transistors for reading out the signal charges accumulated in the photodiodes, respectively. The first pixel 230 further includes a reset transistor connected at one end to the photodiodes 201 of the first and second pixels 230 and 231 and supplied at the other end with a power voltage, and the second pixel 231 further includes an amplifier transistor having a gate electrode 204 connected to the transfer transistors of the first and second pixel 230 and 231 and supplied at its drain with a power voltage.

Abstract: A memory device with improved thermal isolation. The memory cell includes a first electrode element, having an upper surface; an insulator stack formed on the first electrode element, including first, second and third insulating members, all generally planar in form and having a central cavity formed therein and extending therethrough, wherein the second insulator member is recessed from the cavity; a phase change element, generally T-shaped in form, having a base portion extending into the cavity to make contact with the first electrode element and making contact with the first and third insulating members, and a crossbar portion extending over and in contact with the third insulating member, wherein the base portion of the phase change element, the recessed portions of the second insulating member and the surfaces of the first and third insulating members define a thermal isolation void; and a second electrode formed in contact with the phase change member.

Abstract: A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.

Abstract: A transistor type ferroelectric memory including: a substrate; a gate electrode formed above the substrate; a ferroelectric layer formed above the substrate to cover the gate electrode; a source electrode formed above the ferroelectric layer; a drain electrode formed above the ferroelectric layer and apart from the source electrode; and a channel layer formed above the ferroelectric layer and between the source electrode and the drain electrode.