Abstract: A method and apparatus for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the microstructure becomes integral with the substrate. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then dispensed evenly or circulated over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.

Abstract: A method for packaging a semiconductor device wherein a chip is interconnected with a substrate by performing a flip-chip bonding by using an Au bump formed on a bond pad of the chip. In the method, a wire-bonding process and a molding process using an epoxy molding compound are not required. Further, a process of attaching solder balls to the substrate is not required, which eliminates subsequent flux printing and deflux processes. Accordingly, a packaging process of the semiconductor device becomes simplified and therefore the cost of the semiconductor device is decreased.

Abstract: A method of manufacturing a plurality of semiconductor chip packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A first microelectronic element is arranged with the substrate and contacts on the microelectronic element are connected to the substrate. A conductive member is placed on top of the first microelectronic element and is used to support a second microelectronic element. The second microelectronic element is arranged with the conductive member in a top and bottom position. The second microelectronic element is then also connected by leads from contacts on the second microelectronic element to pads and terminals on the circuitized substrate. The conductive member is then connected to a third pad or set of pads on the substrate. An encapsulant material may be deposited so as to encapsulate the leads and at least one surface of the microelectronic elements.

Abstract: A the semiconductor chip stack in which an intermediate space between semiconductor chips is filled at least along one edge of the upper face of a top chip by a spacer composed of a polymer which can be structured photographically, of photoresist, of an encapsulation compound or an adhesive, and is sealed from the outside. During the passivating process, the connecting contact pads are kept free of the material of this spacer for bonding wires or other external connections on the upper face of the bottom chip.

Abstract: An adhesive layer containing a photo-curing adhesive and a thermosetting adhesive is formed on a semiconductor wafer in which a plurality of semiconductor elements are formed. The adhesive layer and the semiconductor wafer are adhered together by selectively exposing the adhesive layer to light and curing the photo-curing adhesive contained in the adhesive layer on the peripheral portion of each semiconductor element. By developing the photo-curing adhesive, the adhesive layer in an area that has not been exposed is removed. Whether the pattern of the adhesive layer is satisfactory or not is determined for each semiconductor element. A lid part is placed on the adhesive layer of the semiconductor element determined to be satisfactory, and the adhesive layer and the lid part are adhered together by heating the adhesive layer and causing the thermosetting adhesive contained in the adhesive layer to exhibit adhesive properties.

Abstract: A method of making a semiconductor chip assembly includes providing a metal base that includes a metal plate and a metal layer, providing a routing line that contacts the metal layer and an etch mask that contacts the metal plate, providing a semiconductor chip that includes a conductive pad, mechanically attaching the chip to the routing line, electrically connecting the routing line to the pad, and etching the metal base using a first wet chemical that is selective of the metal plate and then a second wet chemical etch that is selective of the metal layer and the etch mask to form a pillar from an unetched portion of the metal base that contacts the routing line.

Abstract: A component mounting apparatus includes a component feeder (20) that feeds a component (2) with its bump electrodes facing down, a mounting head (5) that mounts the component onto a substrate (3), a supporting base (8) that secures the substrate, and a positioning device (6, 7) that aligns the component with the substrate. The mounting head includes an ultrasonic vibration generator (24), an ultrasonic vibration propagation member (34, 38, 54) that conveys the ultrasonic vibration provided by the ultrasonic vibration generator to a working face (33, 41, 57) holding the component as vibration parallel thereto, a pressure loader (22, 23, 39, 55, 59) that applies a pressure load to the working face from a position immediately thereabove in the direction perpendicular thereto, and a heater (32, 47, 49, 50, 51, 52, 53) that heats the vicinity of the working face. Thereby, ultrasonic bonding is carried out with high reliability even if the component has a number of bump electrodes (2a) on its face.

Abstract: A process for producing a circuit component having a double-sided circuit device between a pair of substrates. The process entails depositing a solder material on contact areas on surfaces of the substrates, placing a first of the substrates within a cavity in a receptacle, and then placing a lead member on the substrate so that the lead member is supported by the receptacle and a portion of the lead member is aligned with a portion of the contact area of the substrate. A fixture is then placed on the lead member and over the substrate so that the fixture is supported by the receptacle. After aligning the circuit device with the contact area of the remaining substrate, the substrate-device assembly is placed in an aperture in the fixture so that a surface of the device electrically contacts the contact area of the first substrate and the opposite surface of the device electrically contacts the contact area of the second substrate. The resulting fixtured assembly then undergoes reflow.

Abstract: A method of manufacturing an electronic part packaging structure including a step of mounting an electronic part, which has a connection terminal and a passivating film to cover the connection terminal, on a mounted body to direct the connection terminal upward, a step of forming an insulating layer to cover the electronic part, a step of forming a via hole in a portion of the passivating film and the insulating layer on the connection terminal to expose the connection terminal, and a step of forming a wiring pattern, which is connected electrically to the connection terminal via the via hole, on the insulating layer.

Abstract: The invention relates to a method for producing a protection for the chip edges of electronic components that are not provided with a housing, according to which semiconductor chips provided with a laterally open bonding channel are mounted on a substrate with a tape interposed between. The invention further relates to a system for protecting chip edges.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor wafer is prepared that includes a plurality of IC chips, each having a circuit including a terminal for applying an electrical quantity to the circuit, and a switch electrically connected to the terminal. A wire is formed between adjacent IC chips to provide a parallel or series electrical connection between the terminals of the IC chips via the switch. A test is performed to determine the operability (defective or non-defective) of each of the IC chips. The switch is then operated to provide an electrical connection between the terminals of only those IC chips that were determined to not be defective and the wire. A conduction test is performed on the circuits of the IC chips through the wire.

Abstract: Any one of an insulating film forming a TFT, a silicon film and a conductive film is formed by applying a solution and annealing it. In a spin coater (102), a coating solution containing a thin film component which is supplied from a solution storage section (105) is spin-coated onto a substrate. The substrate after coating the coating solution is annealed in an annealing section (103) to form a coating film on the substrate. Additional laser annealing improves one of film characteristics, i.e., crystallinity, density and adhesiveness. Application of the coating solution or a resist by an ink jet process increases utilization of the solution and permits forming a patterned coating film. Because a thin film device in accordance with the present invention is inexpensive and has a high throughput, TFT production by a production system having high utilization of the coating solution drastically reduces initial investment and production cost of a liquid crystal display device.

Abstract: A manufacturing method of a thin film transistor. An amorphous silicon thin film is formed on an insulating substrate, and is crystallized by a lateral solidification process with illumination of laser beams into the amorphous silicon thin film to form a polysilicon thin film. Next, protrusion portions protruding from the surface of the polysilicon thin film are removed by plasma dry-etching using a gas mixture including Cl2, SF6 and Ar at the ratio of 3:1:2 to smooth the surface of the polysilicon thin film, and the semiconductor layer is formed by patterning the polysilicon thin film. A gate insulating film covering the semiconductor layer is formed and a gate electrode is formed on the gate insulating film opposite the semiconductor layer.

Abstract: In producing a thin film transistor, after an amorphous silicon film is formed on a substrate, a nickel silicide layer is formed by spin coating with a solution (nickel acetate solution) containing nickel as the metal element which accelerates (promotes) the crystallization of silicon and by heat treating. The nickel silicide layer is selectively patterned to form island-like nickel silicide layer. The amorphous silicon film is patterned. A laser light is irradiated while moving the laser, so that crystal growth occurs from the region in which the nickel silicide layer is formed and a region equivalent to a single crystal (a monodomain region) is obtained.

Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device of which manufacturing process is simplified by improving usage rate of a material.

Abstract: A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor layer in sequence. The second conductive layer is patterned such that each side of thereof above the gate has a taper profile and the first conductive layer is exposed. A first plasma process is performed to transform the surface and the taper profile of the second conductive layer into a first protection layer. The first conductive layer not covered by the first protection layer and the second conductive layer is removed to form a source/drain. The source/drain is with fine dimensions and the diffusion of metallic ions from the second conductive layer to the patterned semiconductor layer can be avoided.

Abstract: By using lasers having different wavelengths in laser annealing of an amorphous semiconductor film, the amorphous semiconductor film can be crystallized and the crystallinity of the crystallized film is improved. A laser 126 to 370 nm in wavelength is used first to subject an amorphous semiconductor film to laser annealing, thereby obtaining a crystalline semiconductor film. In desirable laser annealing, a subject surface is irradiated with a laser beam processed by an optical system into a linear laser beam that is linear in section on the subject surface. Next, a laser 370 to 650 nm in wavelength is used to irradiate the above crystalline semiconductor film by again processing the laser beam into a linear beam through an optical system. A crystalline semiconductor film thus obtained has an excellent crystallinity. If this crystalline semiconductor film is used to form an active layer of a TFT, an electric characteristic of the TFT can be improved.

Abstract: The invention includes SOI thin film transistor constructions, memory devices, computer systems, and methods of forming various structures, devices and systems. The structures typically comprise a thin crystalline layer of silicon/germanium formed over a wide range of suitable substrates. The crystalline properties of the silicon/germanium can be controlled during formation of the silicon/germanium so that the material has a relaxed crystalline lattice and large crystalline grain sizes. The crystalline grain sizes can be sufficiently large so that transistor devices formed in association with the thin crystalline material have active regions utilizing only a single grain of the silicon/germanium material.

Abstract: A guard ring is formed in a semiconductor region that is part of a Schottky junction or Schottky diode. The guard ring is formed by ion implantation into the semiconductor contact layer without completely annealing the semiconductor contact layer to form a high resistance region. The guard ring may be located at the edge of the layer or, alternatively, at a distance away from the edge of the layer. A Schottky metal contact is formed atop the layer, and the edges of the Schottky contact are disposed atop the guard ring.

Abstract: A substrate supporting a portion of a semiconductor material is used to produce a field-effect transistor. A portion of a temporary material lies between the portion of semiconductor material and the substrate. A gate is formed, which comprises an upper part in rigid connection with the portion of semiconductor material, and at least one bearing part settled on the substrate. The temporary material is removed and replaced with an electrically insulating material. During removal and replacement of the temporary material, the portion of semiconductor material is held in place relative to the substrate by the gate.

Abstract: The invention relates to an organic field-effect transistor, to a method for structuring an OFET and to an integrated circuit with improved structuring of the functional polymer layers. The improved structuring is obtained by introducing, using a doctor blade, the functional polymer in the mold layer in which recesses are initially produced by imprinting.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).

Abstract: Methods of fabricating CMOS transistors are disclosed. A disclosed method includes forming first and second gate patterns on the first and second wells, respectively; forming a sidewall insulating layer over the substrate; forming first lightly doped regions in the first well by NMOS LDD ion implantation; forming a first gate spacer insulating layer over the substrate; forming second lightly doped regions in the second well by PMOS LDD ion implantation; sequentially stacking a spacer insulating layer and a second gate spacer insulating layer on the first gate spacer insulating layer; forming first and second spacers on sidewalls of the first and second gate patterns; and forming first and second heavily doped regions in the first and second wells by NMOS and PMOS source/drain ion implantations, respectively.

Abstract: A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.

Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 ? to 1400 ? and the nitride is subsequently removed and a thin oxide, for example 320 ? is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.

Abstract: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

Abstract: A method and apparatus for depositing self-aligned base contacts where over-etching the emitter sidewall to undercut the emitter contact is not needed. A semiconductor structure has a T-shaped emitter contact that comprises a T-top and T-foot. The T-top acts as a mask for depositing the base contacts. In forming the T-top, its dimensions may be varied, thereby allowing the spacing between the base contacts and emitter to be adjusted.

Abstract: Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

Abstract: Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI arrays and logic transistors on (100) surface orientation silicon, and p-type CMOS logic transistors on (110) surface orientation silicon. In addition, the method fabricates a silicon substrate trench capacitor within a hybrid surface orientation SOI and bulk substrate. Cost-savings is realized in that the array mask open and patterning for silicon epitaxial growth is accomplished in the same step and with the same mask.

Abstract: A phototransistor of a CMOS image sensor suitable for decreasing the size of layout, and a method for fabricating the phototransistor are disclosed, in which the phototransistor includes a first conductive type semiconductor substrate; an STI layer on the first conductive type semiconductor substrate, to define an active area and a device isolation area in the first conductive type semiconductor substrate; a second conductive type well in the first conductive type semiconductor substrate; a gate line on the first conductive type semiconductor substrate; an ohmic contact layer in the second conductive type well, wherein the ohmic contact layer is overlapped with the gate line in state of interposing the STI layer therebetween; and a contact to connect the gate line with the ohmic contact layer through the STI layer.

Abstract: A microelectronic product and a method for fabricating the same each provide a capacitor formed interposed between a first dielectric layer and a second dielectric layer formed over a substrate having a first contact region and a second contact region exposed therein. The capacitor is also connected to a first conductor stud that penetrates the first dielectric layer and contacts the first contact region and a second conductor stud that penetrates the second dielectric layer. A contiguous conductor interconnect and conductor stud layer is formed within a dual damascene aperture through the second dielectric layer and the first dielectric layer and contacting the second contact region. An etch stop layer employed when forming a trench within the dual damascene aperture also passivates a capacitor sidewall.

Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell.

Abstract: The present invention discloses an improved DRAM of semiconductor device and method for manufacturing the same wherein an ONO (oxide-nitride-oxide) structure for trapping electrons or holes used in a non-volatile memory is employed in a gate insulating film of the DRAM to reduce impurity concentrations of a channel region and a well region.

Abstract: A semiconductor device of the present invention includes an MOSFET which has a stacked gate insulation film formed of at least two types of insulation films, that is, a thermal oxide film provided on a semiconductor substrate and a CVD oxide film provided nearer to a gate electrode than thermal oxide film. The stacked insulation film is provided so that the ratio of the thickness of the CVD oxide film to that of the entire stacked gate insulation film is at least 20%. By such a structure, the gate insulation film thickness is kept uniform. Further, nitrogen may be segregated at an interface between the thermal oxide film and a semiconductor substrate and an interface between the gate electrode and the CVD oxide film. Thus, the occurrence of interface states is prevented between the gate insulation film and the semiconductor substrate as well as between the gate insulation film and the gate electrode.

Abstract: A method of manufacturing a memory device is provided. The method includes forming an electrode over a substrate. The method also includes forming an opening in the electrode to provide a tapered electrode contact surface proximate the opening. The method further includes forming a phase change feature over the electrode and on the tapered electrode contact surface.

Abstract: Integrated circuit field effect transistors are manufactured by forming a pre-active pattern on a surface of a substrate, while refraining from doping the pre-active pattern with phosphorus. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate, at opposite ends of the pre-active pattern. The interchannel layers are then selectively removed, to form tunnels passing through the pre-active pattern, thereby defining an active channel pattern including the tunnels and channels including the channel layers. The channels are doped with phosphorus after selectively removing the interchannel layers. A gate electrode is then formed in the tunnels and surrounding the channels.

Abstract: A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed round the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion regions.

Abstract: A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a switch on a semiconductor substrate, and forming a driver switch of a driver embodied in a transistor. The method of forming the transistor includes forming a gate over the semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate, and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region. The method of forming the transistor still further includes forming a doped region with a doping concentration profile less than the heavily doped region between the heavily doped region and the oppositely doped well.

Abstract: The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change memory material. The second side has a length that is less than the first side. Additionally, a second dielectric may overlie the lower electrode. The second dielectric has a shape that is substantially similar to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes providing a lower electrode material in a recess. The method also includes removing at least a portion of the second side.

Abstract: The present invention relates to a capacitor having a hafnium oxide and aluminum oxide alloyed dielectric layer and a method for fabricating the same. The capacitor includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer, wherein a portion of the dielectric layer contacting one of the lower electrode and the upper electrode is formed by alloying hafnium oxide and aluminum oxide together.

Abstract: A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one or more of the activated sites. A metallic conductive material can then be plated on the seed layer to form the gate conductor. Semiconductor devices having a gate conductor plated thereon to a width of between about 1 to about 7 nanometers are also provided.

Abstract: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.

Abstract: Semiconductor devices have device regions in which semiconductor properties such as spreading resistivity and its profile are significant. In making a p-type device region on a semiconductor wafer, an initial semiconductor device region is defined by a buried region, and an initial spreading resistivity profile is developed by annealing. After annealing, semiconductor device properties can be enhanced by removing a surface sub-region of the initial device region, and can be further improved by epitaxially growing thereon a monocrystalline film as an improved channel layer for FET devices. Such properties are relevant in MOS as well as bipolar devices.

Abstract: A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on a side of the first semiconductor layer, epitaxially growing a second semiconductor layer in a region on the semiconductor substrate other than a region formed with the first insulating layer, forming a first semiconductor element in the first semiconductor layer on the first insulating layer, and forming a second semiconductor element in the second semiconductor layer on the second insulating layer.

Abstract: A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.

Abstract: An active cell isolation body of a semiconductor device and a method for forming the same are disclosed. An example active cell isolation body of a semiconductor device includes a trench with a depth in a semiconductor substrate at an active cell isolation region, a buried gap in the semiconductor substrate at a lower portion of the active cell isolation region, where the buried gap is in communication with the trench and extended toward active regions of the semiconductor substrate, and an active cell isolation film filled in the trench to close the buried gap.

Abstract: A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

Abstract: The present invention discloses an improved shallow trench isolation process. A semiconductor substrate having a pad oxide disposed thereon and a pad nitride disposed directly on the pad oxide is provided. A trench is etched, through the pad oxide and the pad nitride, into the semiconductor substrate. A thermal oxide liner is then grown in the trench. A silicon nitride liner is deposited into the trench, wherein the silicon nitride liner covering the pad nitride and the thermal oxide liner has a first stress status. A stress alteration process is performed to alter the silicon nitride liner from the first stress status to a second stress status. A trench fill dielectric having the second stress status is deposited into the trench.

Abstract: Method for producing a stacked structure by obtaining at least two crystalline parts by detaching them from a same initial structure, each crystalline part having one face created by the detachment having a tilt angle with a reference crystalline plane of the initial structure. Structures are formed from the crystalline parts, each structure having a face to be assembled that has a controlled tilt angle in relation to the tilt angle of the created face of the corresponding crystalline part. The structures are assembled while controlling their relative positions, rotating in an interface plane, in relation to relative positions of respective crystalline parts within the initial structure, to obtain a controlled resulting tilt angle at the interface between the structures. The method may find application particularly in microelectronics, optics, and optoelectronics.