Abstract: Improved fabrication processes for manufacturing GeOI type wafers are disclosed. In an implementation, a method for fabricating a germanium on insulator wafer includes providing a source substrate having a surface, at least a layer of germanium and a weakened area. The weakened area is located at a predetermined depth in the germanium layer of the source substrate and is generally parallel to the source substrate surface. The technique also includes providing a germanium oxynitride layer in or on the source substrate, bonding the source substrate surface to a handle substrate to form a source-handle structure, and detaching the source substrate from the source-handle structure at the weakened area of the source substrate to create the germanium on insulator wafer having, as a surface, a useful layer of germanium.

Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.

Abstract: It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective film that is likely to damage an element if the protective film is formed on the element directly) is previously formed on a heat-resistant substrate other than a substrate with the element formed thereon. The protective film is peeled off from the heat-resistant substrate, and transferred over the substrate with the element formed thereon so as to seal the element.

Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.

Abstract: A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming at least one pair of oppositely-doped regions in the superlattice defining at least one semiconductor junction.

Abstract: A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

Abstract: Disclosed is a method for forming landing plug contacts in a semiconductor device. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the gate structures; planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process until the gate hard mask is exposed; forming a hard mask material on the planarized inter-layer insulation layer; patterning the hard mask material, thereby forming a hard mask; forming a plurality of contact holes exposing the substrate disposed between the gate structures by etching the planarized inter-layer insulation layer with use of the hard mask as an etch mask; forming a polysilicon layer on the contact holes; and forming the landing plug contacts buried into the contact holes through a planarization process performed to the polysilicon layer until the gate hard mask is exposed.

Abstract: A semiconductor device formed by an automated wire bonding system. The semiconductor device comprises a lead frame having a plurality of lead fingers and a die paddle, and a semiconductor die mounted to the die paddle. The die paddle comprises a plurality of eyepoint features that extend from the die. The die comprises a first plurality of bonding pads and the lead fingers comprise a second plurality of bonding pads. The first and second bonding pads are interconnected by a plurality of connecting wires which are installed by the automated wire bonding system. The wire bonding system obtains an image of the lead frame and identifies the eyepoint features of the die paddle within the image so as to more accurately determine the positions of the second wire bonding pads of the lead frame with respect to the wire bonding system.

Abstract: The present invention is a method and apparatus for forming a bump for semiconductor interconnect applications, such as reverse wire bonding or stud bumping for flip chip interconnections. The bump is formed by (1) ball bonding at the bump site, (2) raising the capillary a predetermined height after forming the ball bond with the wire paying out of the capillary tip, (3) moving the capillary laterally a predetermined distance, preferably in a direction toward the site of other end of the wire loop, if the bump is to be used as the platform for a stitch bond of a wire loop, (4) raising the capillary further, and (5) moving the capillary diagonally downwardly and in the opposite direction of the first lateral motion. The wire is then severed by raising the capillary, closing the clamps and raising the capillary again to snap the wire pigtail off at the bump.

Abstract: Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a barrier metal over the dielectric material and the exposed portion of the substrate; depositing a conductive metal over the barrier metal, the deposited conductive metal having a thickness sufficient to fill the etched pattern; planarizing the conductive metal to form a planar metal layer; and polishing the metal layer and the barrier metal in a single polishing step using an abrasive-free polish until the dielectric material surrounding the pattern is exposed.

Abstract: A system and method is described for manufacturing an out of plane integrated circuit inductor. A plurality of parallel metal bars are formed on a substrate and covered with a first passivation layer. A ferromagnetic core is then deposited over the first passivation layer with its length perpendicular to the plurality of parallel metal bars. A second passivation layer is deposited over the ferromagnetic core and vias are etched through the passivation layers to the alternate ends of the underlying parallel metal bars. A plurality of cross connection metal bars are then formed on the second passivation layer with vertical portions that fill the vias and connect the alternate ends of the plurality of parallel metal bars to form an inductor coil. A third passivation layer is then deposited over the cross connection metal bars.

Abstract: A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

Abstract: The object of the present invention is to improve the interfacial adhesion between the film with low dielectric constant and protective film, without damaging the excellent dielectric, flatness and gap-filling characteristics of the organic material of low dielectric constant, and for that purpose there is provided a wiring structure with the copper film embedded in the insulation film of the wiring layer, wherein the insulation film of the wiring layer is of a multi-layered structure with the laminated methyl silisesquioxane (MSQ) film, methylated hydrogen silisesquioxane (MHSQ) film and silicon oxide film.

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer. In one aspect, the invention provides a method for processing a substrate including positioning a substrate having a conductive material disposed thereon, introducing a reducing compound or a silicon based compound, exposing the conductive material to the reducing compound or the silicon based compound, and depositing a silicon carbide layer without breaking vacuum.

Abstract: Disclosed are a method of manufacturing a semiconductor device and a structure of a semiconductor device. A method of forming a passivation film of a semiconductor device comprises the steps of forming metal wires on a semiconductor substrate, forming a buffer oxide film being a first passivation film on the metal wires, wherein the buffer oxide film can mitigate damage by plasma, forming a high density plasma film being a second passivation film on the buffer oxide film, and forming a third passivation film on the second passivation film. According to the present invention, it is possible to significantly reduce the leakage current between a select source line and a common source line.

Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.

Abstract: Wiring layers through that come into direct contact with an electrode of a ferroelectric capacitor provide a wiring layer structure configured so that the characteristic of the ferroelectric substance is not degraded by production of a reducing agent. One of coating layers through is provided on the periphery of the Al main wiring layer. A single Ti film or TiN film or a combination of both is used as the coating film. The TiN film suppresses reaction between water and aluminum. The Ti film occludes hydrogen. Therefore, the coating layer provided on the periphery of the Al wiring layer inhibits water or molecular hydrogen from entering the Al wiring layer from the outside and therefore there is no degradation of the characteristics of the ferroelectric capacitor.

Abstract: A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film as a mask, the resist film and the antireflective film are removed by ashing. Thereafter, the first insulating film is dry etched, using the third insulating film as a mask, to form a wiring trench extending to the lower-layer wiring. The dry etching of the third insulating film and the second insulating film is performed using a gas containing fluorine at a pressure of 0.1 Pa to 4 Pa. Ashing is preferably performed using at least one of hydrogen and an inert gas.

Abstract: A method of manufacturing a semiconductor device is to be provided, which improves filling performance of a conductive layer to be formed by an electrolytic plating process in an interconnect trench or a via hole, and achieves a higher in-plane uniformity in bottom-up performance. An electrolytic plating process to fill with a conductive layer at least one of an interconnect trench and a via hole formed in a dielectric layer on a semiconductor substrate includes a first step of executing a plating operation under a predetermined integrated current density, which is a product of a current density representing a current value supplied per unit area of a plating solution containing a material which constitutes the conductive layer and a plating time, and a second step of executing a plating operation under a lower current density than that of the first step.

Abstract: A film-formation method for a semiconductor process includes seed film formation and main film formation. In the seed film formation, a metal-containing raw material gas and a first assist gas to react therewith are supplied into a process container, which accommodates a target substrate having an underlying layer, thereby forming a seed film on the underlying layer by CVD. In the main film formation, the raw material gas and a second assist gas to react therewith are supplied into the process container, thereby forming a main film on the seed film by CVD. The seed film formation includes first and second periods performed alternately and continuously. In each first period, the raw material gas is supplied into the process container while the first assist gas is stopped. In each second period, the first assist gas is supplied into the process container while the raw material gas is stopped.

Abstract: Methods of forming barrier layers and structures thereof are disclosed. A nitrogen rich region is formed at a top surface of a barrier layer by exposing the barrier layer to a nitridation treatment. The nitrogen rich region increases the oxidation resistance of the barrier layer. The barrier layers have improved diffusion barrier properties. A stack of barrier layers may be formed, with one or more of the barrier layers in the stack being exposed to a nitridation treatment.

Abstract: A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.

Abstract: A method of fabricating a metal silicide layer over a substrate is provided. First, a hard mask layer is formed over a gate formed on a substrate and a portion of the substrate is exposed. Thereafter, a first metal silicide layer, which is a cobalt silicide or a titanium silicide layer, is formed on the exposed substrate. After that, the hard mask layer is removed and a second metal silicide layer is formed over the gate, wherein a material of the second metal silicide layer is selected from a group consisting of nickel silicide, platinum silicide, palladium silicide and nickel alloy. Since different metal silicide layers are formed on the substrate and the gate, the problem of having a high resistance in lines with a narrow line width and the problem of nickel silicide forming spikes and pipelines in the source region and the drain region are improved.

Abstract: In a method of manufacturing a semiconductor device, a first wiring line composed of a copper containing metal film is formed on or above a semiconductor substrate. A first interlayer insulating film is formed on a whole surface of the semiconductor substrate to cover the first wiring line. The first interlayer insulating film is selectively removed to form a connection hole reaching the first wiring line. A barrier metal film is formed to cover an inner surface of the connection hole and then a copper containing metal film is formed to fill the connection hole. The copper containing metal film formed outside the connection hole is removed. A second interlayer insulating film is formed on a whole surface of the semiconductor substrate to cover the copper containing metal film formed in the connection hole. The second interlayer insulating film is selectively removed to form a wiring line groove such that the copper containing metal film formed in the connection hole is exposed at a bottom.

Abstract: A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

Abstract: Methods for forming robust copper structures include steps for providing a substrate with an insulating layer with openings formed therein. At least two barrier layers are then formed followed by the deposition of a copper seed layer which is annealed. Bulk copper deposition of copper and planarization can follow. In one approach the seed layer is implanted with suitable materials forming an implanted seed layer upon which a bulk layer of conductive material is formed and annealed to form a final barrier layer. In another approach, a barrier layer is formed between two seed layers which forms a base for bulk copper deposition. Another method involves forming a first barrier layer and forming a copper seed layer thereon. The seed layer being implanted with a barrier material (e.g. palladium, chromium, tantalum, magnesium, and molybdenum or other suitable materials) and then bulk deposition of copper-containing material is performed followed by annealing.

Abstract: A semiconductor device structure having a barrier layer comprising a conductive portion and a nonconductive portion is disclosed. The conductive portion includes a metal nitride compound and the nonconductive portion includes a metal oxide, metal oxynitride, metal carbide, or metal carbonitride compound. A method of forming the semiconductor device structure is also disclosed. The method comprises forming a barrier layer over a metallization layer and a dielectric layer in the semiconductor device structure. The barrier layer is formed by depositing a thin, metal layer over the metallization layer and the dielectric layer. The metal layer is exposed to a nitrogen atmosphere and the nitrogen reacts with portions of the metal layer over the metallization layer to form a conductive, metal nitride portion of the barrier layer. Portions of the metal layer over the dielectric layer react with carbon or oxygen in the dielectric layer to produce a nonconductive portion of the barrier layer.

Abstract: Methods of forming a pattern for a semiconductor device are disclosed, wherein a critical dimension (CD) of a pattern can be accurately controlled and, thus, finer critical dimension can be realized. An illustrated example method comprises: forming an etching target layer on a semiconductor substrate; forming a photoresist pattern on the etching target layer; forming polymer spacers on side surfaces of the photoresist pattern to improve side-surface roughness of the photoresist pattern; and etching the etching target layer using the photoresist pattern and the polymer spacers as a mask to form a pattern.

Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, warp will be a large ±40 ?m to ±100 ?m. Since with that warp device fabrication by photolithography is challenging, reducing the warp to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the warp. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the warp.

Abstract: The invention utilizes colloidal silica soot (62) in a semiconductor process for chemical-mechanical planarizing a semiconductor integrated circuit workpiece (24) with a slurry (60). The particulate abrasive agent colloidal solid sphere fused silica soot (62) provides a beneficial CMP slurry/process for semiconductor device manufacturing compared to standard semiconductor CMP slurries with conventional colloidal sol-gel or fumed silica.

Abstract: A resist layer is deposited a resist layer on a first layer of a layered stack. The stack also includes a second layer below the first layer. The resist layer is processed with a lithographic method to achieve a first structured resist layer. At least a part of the first structured resist layer is trimmed to achieve a second structured resist layer having at least in parts a structure with a critical dimension smaller than obtainable by processing the resist with a lithographic method. The first layer is selectively removed from the second layer in the areas not covered by the second structured resist layer. The second layer is modified by implantation to become a layer with defined selectivity to the non-modified material. The remains of the first layer are removed. The non-modified structures of the second layer are removed to create a hardmask layer by the remaining layer. The layered stack is further structured with the hardmask layer.

Abstract: A method of making a semiconductor structure, comprises etching a nitride layer with a plasma to form a patterned nitride layer. The nitride layer is on a semiconductor substrate, a photoresist layer is on the nitride layer, and the plasma is prepared from a gas mixture comprising CF4 and CHF3 at a pressure of at least 10 mTorr.

Abstract: The present invention provides a low-k dielectric etching process with high etching selectivities with respect to adjacent layers of other materials, such as an overlying photoresist mask and an underlying barrier/liner layer. The process comprises the step of exposing a portion of the low-k dielectric layer to a plasma of a process gas that includes a fluorocarbon gas having a relatively low fluorine to carbon ratio, a nitrogen-containing gas, and an inert gas, wherein a volumetric flow ratio of the nitrogen-containing gas to the fluorocarbon gas is greater than about 20:1. The process can be used to over etch the low-k dielectric layer to provide improved selectivity to the photoresist mask and the barrier/liner layer, reduced striations and reduced CD loss as compared with conventional low-k dielectric etching processes.

Abstract: Methods are provided for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A process gas having a silicon-containing gas, an oxygen-containing gas, and a fluent gas is flowed into the substrate processing chamber. The fluent gas is introduced into the substrate processing chamber at a flow rate of at least 500 sccm. A plasma is formed having an ion density of at least 1011 ions/cm3 from the process gas to deposit a first portion of the silicon oxide film over the substrate and into the gap. Thereafter, the deposited first portion is exposed to an oxygen plasma having at least 1011 ions/cm3. Thereafter, a second portion of the silicon oxide film is deposited over the substrate and into the gap.

Abstract: A method for manufacturing a mask for integrated circuit devices. The method includes providing a quartz substrate having a surface and forming a MoSi film overlying the surface of the quartz substrate. The method also includes patterning the MoSi film overlying the quartz substrate to form a mask pattern. A step of forming an opaque edge structure comprising a carbon bearing material on a portion of the surface around a peripheral region of the mask pattern is also included.

Abstract: A mounting substrate includes an imprinted structure on one side for containing electrical bumps. The imprinted structure is imprinted and also cured under conditions that allow retention of significant features of the cured polymer film. A chip package is also made of the imprinted structure. A computing system is also disclosed that includes the imprinted structure.

Abstract: Oxycarbosilane materials make excellent matrix materials for the formation of porous low-k materials using incorporated pore generators(porogens). The elastic modulus numbers measured for porous samples prepared in this fashion are 3–6 times higher than porous organosilicates prepared using the sacrificial porogen route. The oxycarbosilane materials are used to produce integrated circuits for use in electronics devices.

Abstract: A method for forming a thin film includes: supplying an additive gas, a dilution gas, and a silicon-containing source gas into a reaction chamber wherein a substrate is placed; forming a thin film on the substrate by plasma CVD under a given pressure with a given intensity of radio-frequency (RF) power from a first point in time to a second point in time; at the second point in time, stopping the supply of the silicon-containing source gas; and at the second point in time, beginning reducing but not stopping the RF power, and beginning reducing the pressure, wherein the reduction of the RF power and the reduction of the pressure are synchronized up to a third point in time.

Abstract: A method is provided for preparing a substrate for photolithographic patterning. The method includes providing a substrate having at least an exposed rough surface layer including a polymeric material. The rough surface layer has surface features characterized by feature step height varying between about two percent and twenty percent of the minimum photolithographic half-pitch. A layer of photoresist material is then provided over the exposed rough surface layer and patterned.

Abstract: This invention relates to a thin reinforced nonwoven fabric for fire blocking an article, articles containing such fabrics, and methods for making the fabrics and fire blocking the articles. When exposed to heat or flame, the fabric is capable of increasing its thickness by at least three times. The fabric comprises an open mesh scrim having a having crimped, heat-resistant organic fibers compressed thereon and held in a compressed state by a thermoplastic binder. When subjected to high heat or flame, the binder in the structure softens and flows, releasing the restrained crimped fibers and allowing the thickness of the fabric to increase dramatically.

Abstract: A heat and fire resistant planar unitary shield formed of heat and flame resistant fibers and voluminous bulking fibers. The shield material has a heat and flame resistant zone with a majority of the heat and flame resistant fibers, and a voluminous bulking zone with a majority of the voluminous bulking fibers. The fibers are distributed through the shield material in an manner that the heat and flame resistant fibers collect closest to the outer surface of the shield with the heat and flame resistant zone, and the voluminous bulking fibers collect closest to the outer surface of the shield material with the voluminous bulking zone.

Abstract: A multilayer ceramic substrate which is obtained by firing multilayers of ceramic green sheets each having a dielectric layer, made of a glass-ceramic material comprising a mixture of alumina and a glass containing at least Si and Ca, and an electrode layer made of Ag and formed on the dielectric layer. The dielectric layer after firing includes anorthite (CaAl2Si2O8) crystals having a grain size of up to 84 nm.

Abstract: A dense cordierite based sintered body is provided, containing at least 93% by mass of cordierite among crystal components present in the sintered body. The average particle diameter of the particles constituting the sintered body is 2 ?m or less.

Abstract: A catalyst is described based on crystalline aluminosilicates of the pentasil type, characterized in that it is constructed from primary crystallites with an average diameter of at least 0.01 ?m and less than 0.1 ?m, that are combined to at least 20% to agglomerates of 5 to 500 ?m, in which the primary crystallites or agglomerates are bonded together by finely divided aluminum oxide, that its BET surface is 300 to 600 m2/g and its pore volume (determined according to mercury porosimetry) is 0.3 to 0.8 cm3/g, that it is present in H form and that the amount of finely divided aluminum oxide binder is 10 to 40 wt. %, referred to the total weight of the aluminosilicate, in which the finely divided aluminum oxide binder is used in the reaction charge as peptizable aluminum oxide hydrate, sodium aluminate being used as aluminum and alkali source, and primary synthesis of the crystalline aluminosilicate occurs without addition of acid.

Abstract: The invention provides and a highly-dispersed supported catalyst that has a reduced average particle size of catalytic metal particles and is also supported by a porous support material. A method of preparing a supported catalyst that can reduce the average particle size of catalytic metal particles supported by a support material includes first mixing a charged support material with a solution containing a polymer electrolyte having a charge opposite to that of the support material to adsorb the polymer electrolyte on the support material. Next, the support material having the polymer electrolyte adsorbed thereon is mixed with a solution containing a catalytic metal precursor ion having a charge opposite to that of the polymer electrolyte to adsorb the catalytic metal precursor ion on the support material having the polymer electrolyte adsorbed on it.

Abstract: A polymerisation catalyst comprising (1) a transition metal compound of Formula A, and optionally (2) an activating quantity of a Lewis acid activator. Z is a five-membered heterocyclic group containing at least one carbon atom, at least one nitrogen atom and at least one other hetero atom selected from nitrogen, sulphur and oxygen, the remaining atoms in the ring being nitrogen or carbon; M is a metal from Group 3 to 11 of the Periodic Table or a lanthanide metal; E1 and E2 are divalent groups from (i) aliphatic hydrocarbon, (ii) alicyclic hydrocarbon, (iii) aromatic hydrocarbon, (iv) alkyl substituted aromatic hydrocarbon (v) heterocyclic groups and (vi) heterosubstituted derivatives of groups (i) to (v); D1 and D2 are donor groups; X is an anionic group, L is a neutral donor group; n=m=zero or 1; y and z are zero or integers. The catalysts are useful for polymerising or oligomerising 1-olefins.

Abstract: Fiber structures that include a catalytic material are provided. The fiber structures (e.g., membranes) may be formed of interconnected carbon fibers. The catalytic material may be in the form of nanosize particles supported on the fibers. In one method of the invention, the structures are produced by electrospinning a polymeric material fiber structure that is subsequently converted to a carbon fiber structure in a heat treatment step which also causes the catalytic material particles to nucleate on the carbon fibers and grow to a desired size. The catalytic material may be uniformly distributed across the carbon fiber structure and the amount of catalytic material may be controlled. These factors may enhance catalytic performance and/or enable using less catalytic material for equivalent catalytic performance which can lead to cost savings, amongst other advantages. The fiber structures may be used in a variety of applications including electrodes in batteries and fuel cells.

Abstract: The present invention is for a process for making a catalyst for production of unsaturated aldehydes, such as methacrolein, by gas phase catalytic oxidation of olefins, such as isobutylene, said catalyst containing oxides of molybdenum, bismuth, iron, cesium, tungsten, cobalt, nickel, antimony, magnesium and zinc. The process is a two-part synthesis of the catalyst with the water insoluble components in one part and the water soluble components in the other part. The water insoluble components are co-precipitated to form an intermediate catalyst precursor of a precipitated support incorporating oxides of the metal components. The intermediate catalyst precursor is filtered and washed to remove nitrates. The intermediate catalyst precursor is slurried with the remaining water soluble components. A final catalyst precursor is formed by removing the water and incorporating the water soluble components. This two-part process reduces the amount of nitrates in the final catalyst precursor.

Abstract: A catalyst composition having the formula: Mo1VaSbbNbcMdOx wherein M is gallium, bismuth, silver or gold, a is 0.01 to 1, b is 0.01 to 1, c is 0.01 to 1, d is 0.01 to 1 and x is determined by the valence requirements of the other components. Other metals, such as tantalum, titanium, aluminum, zirconium, chromium, manganese, iron, ruthenium, cobalt, rhodium, nickel, platinum, boron, arsenic, lithium, sodium, potassium, rubidium, calcium, beryllium, magnesium, cerium, strontium, hafnium, phosphorus, europium, gadolinium, dysprosium, holmium, erbium, thulium, terbium, ytterbium, lutetium, lanthanum, scandium, palladium, praseodymium, neodymium, yttrium, thorium, tungsten, cesium, zinc, tin, germanium, silicon, lead, barium or thallium may also be components of the catalyst. This catalyst is prepared by co-precipitation of metal compounds which are calcined to form a mixed metal oxide catalyst that can be used for the selective conversion of an alkane to an unsaturated carboxylic acid in a one-step process.

Abstract: An NOx sorption-and-reduction type catalyst is made which includes a hydrogen generating catalyst in which Rh is loaded on a support including an Al2O3—ZrO2 composite oxide. Since the Al2O3—ZrO2 composite oxide exhibits a basicity lower than ZrO2, SOx are less likely to approach so that it is possible to suppress the sulfur poisoning of Rh. Moreover, the Al2O3—ZrO2 composite oxide exhibits higher heat resistance than ZrO2, and it has a function of improving the steam reforming reaction activity of Rh in the same manner as ZrO2. Therefore, the post-durability NOx purifying ability of the NOx sorption-and-reduction type catalyst is improved.