Abstract: In an embodiment, a substrate includes a thin film capacitor embedded within. In an embodiment, a plurality of adhesion holes extend through the thin film capacitor. These adhesion holes may improve the adhesion of the capacitor to other portions of the substrate.

Abstract: An electrical resistor structure overlies a substrate and comprises a composite resistor having a first resistor of relatively low resistance and a second resistor of relatively high resistance overlying the first resistor. First and second electrodes make contact with the composite resistor at spaced locations, and a bond pad overlies the second resistor at a position between the electrodes. A metallized fiber is soldered a to a metal bond pad by providing a stacked resistor structure beneath the bond pad, disposing a solder preform over the bond pad, disposing the metallized fiber over the bond pad, and flowing a current through the stacked resistor structure. The stacked resistor structure, when subjected to a current flowing generally along a first axis, is characterized by a temperature profile that has first and second peaks on either side of the bond pad.

Abstract: Provided are a paraelectric thin film structure and a high frequency tunable device with the paraelectric thin film structure. The paraelectric thin film structure has a large dielectric constant tuning rate and a low dielectric loss at a high frequency. The paraelectric thin film structure includes a perovskite ABO3 type paraelectric film formed on an oxide single crystal substrate. The paraelectric film is formed of a material selected from Ba(Zrx,Ti1-x)O3, Ba(Hfy,Ti1-y)O3, or Ba(Snz,Ti1-z)O3. Instead of the paraelectric film, the paraelectric thin film structure may include a compositionally graded paraelectric film having at least two paraelectric films formed of the selected material by varying the composition ratio x, y, or z. A high-frequency/phase tunable device employing the paraelectric thin film structure can have improved microwave characteristics and high-speed, low-power-consuming, low-cost characteristics.

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract: A large-sized substrate having a diagonal length of not less than 500 mm and a ratio of flatness/diagonal length of not more than 6×10?6 is disclosed. By use of the large-sized substrate for exposure of the present invention, the exposure accuracy, particularly the register accuracy and resolution are enhanced, so that it is possible to achieve high-precision exposure of a large-sized panel. With the processing method according to the present invention, it is possible to stably obtain a large-sized photomask substrate with a high flatness, and since the CD accuracy (dimensional accuracy) at the time of exposure of the panel is enhanced, it is possible to perform exposure of a fine pattern, leading to a higher yield of the panel. Furthermore, by applying the processing method according to the present invention, it is also possible to create an arbitrary surface shape.

Abstract: A semiconductor chip including a substrate, a metal interconnection structure and a circuit is provided. The substrate has at least one dielectric ring on a substrate surface of the substrate. The metal interconnection structure is disposed on the substrate surface and has at least one guard ring. The circuit lies over the substrate. The projection of the dielectric ring on the substrate surface surrounds the circuit, and the projection of the guard ring on the substrate surface surrounds that of the dielectric ring and that of the circuit on the substrate surface.

Abstract: A chip package includes a microstrip spacer disposed between a first die and a second die. The microstrip spacer includes electrically conductive planes that are ground planes for at least one of the first die and the second die. A method includes operating the first die at a first clock speed and operating the second die at a second clock speed. A system includes a chip package with a microstrip spacer and a system housing.

Abstract: A package module with an alignment structure is provided by this invention. The package module comprises a package substrate having a die region and a die disposed thereon. At least one pair of conductive alignment protrusions is disposed in the die region and is separated from each other by the die. A test pad is disposed on the package substrate opposing the die and electrically connected to the pair of conductive alignment protrusions. An electronic device with an alignment structure and an inspection method after mounting is also disclosed.

Abstract: A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first inner circuit has multiple contact pads disposed on the contact surface. The ceramic stiffener is disposed on the carrying surface and has a first opening. In addition, the chip is disposed on the carrying surface and within the first opening and electrically connected to at least one of the contact pads.

Abstract: A packaged semiconductor device includes a two piece lead assembly having vertically separated top and bottom lead frames. A semiconductor die is between the two lead frames and makes electrical and thermal contact to the two lead frames. The lower lead frame is generally flat while the upper lead frame has a flat top surface and downward extensions that fall on two opposite sides of the lower lead frame and that end in flanges that have bottom surfaces that are coplanar with the bottom surface of the bottom lead frame. When the assembly is molded, the top surface of the top lead frame and the bottom surfaces of the flanges and the bottom lead frame are exposed to allow electrical contact to the semiconductor die and to provide thermal conductive paths to dissipate heat developed in the semiconductor die.

Abstract: An improved chip package structure includes a chip carrier, a chip, a plurality of pins, a plurality of leads, a package body and a heat spreader. The chip is fixed on the chip carrier. The leads are electrically connected between the chip and the pins. The package body is packaged outside the chip carrier, the chip and the leads. The heat spreader is disposed in the package body. The heat spreader contacts the chip carrier, and is partially exposed out of a face (top face) of the package body. Heat generated by the chip can thus be transmitted to a heatsink via the chip carrier and the heat spreader so as to discharge a large amount of heat generated by the chip to the outside. The improved chip package structure has a good heat conduction efficiency and an effectively enhanced heat spreading efficiency.

Abstract: A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second surfaces (111b) are coplanar (130) with the passive chip surface (101b). Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound (150) covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar (130) with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 ?m. Reflow metals may be on the passive chip surface and the second segment surfaces.

Abstract: A sensor package apparatus and method are disclosed in which a sensor die is provided and based on a substrate. An integrated circuit is generally associated with the sensor die. A leadframe is also provided, which is connected by at least one weld to the integrated circuit and the substrate. The integrated circuit, the leadframe, and the sensor die are configured in a flip-chip arrangement to protect the sensor die and form a sensor package apparatus that provides compact and robust electrical and physical connections thereof. The integrated circuit can be formed from, for example, silicon carbide. A metallization layer can also be formed on the integrated circuit, wherein the integrated circuit is configured upon the substrate of the sensor die. The metallization layer thus adheres to the integrated circuit via the weld(s).

Abstract: The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device to the leads and an encapsulation layer protects the package. In a second embodiment, the MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package according to each embodiment.

Abstract: An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the underfill, and together with the underfill, constitutes the underfill film. The device may include solder bumps affixing the component to the circuit board, the underfill film having holes within which the solder bumps are aligned. There may be solder bumps on the underside of the circuit board promoting heat dissipation. There may be heat sinks on the circuit board to which the thermally conductive sheet is affixed promoting heat dissipation. The thermally conductive sheet may be affixed to a chassis promoting heat dissipation. The thermally conductive sheet thus promotes heat dissipation from the component to at least the circuit board.

Abstract: A power semiconductor component (30) with power semiconductor chip stack (14) has a base power semiconductor chip (16) and a power semiconductor chip (17) stacked on the rear side of the base power semiconductor chip (16), a rewiring structure for the electrical coupling of the power semiconductor chips being arranged within the rear side metallization.

Abstract: A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11?). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.

Abstract: A semiconductor package including a first substrate having a die receiving area, a first adhesive layer, a window opening, and a plurality of conductive traces, a first semiconductor die having two sides and with an electrically active side mounted to the substrate through the first adhesive layer, a second adhesive layer having a first side attached to an electrically inactive side of the first semiconductor die, a second substrate having a die receiving area and a plurality of conductive traces and terminals, a last adhesive layer having a first side attached to a side of the second substrate with the terminals, a last semiconductor die having two sides and with an electrically inactive side being mounted to the second side of the third adhesive layer, and an electrically active side being electrically coupled to the conductive traces of the first or second substrate directly or through a redistribution device, and an encapsulant to encapsulate the semiconductor dies and electrical coupling, and signal tran

Abstract: An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.

Abstract: A multichip stacking structure is provided, including a chip carrier; a plurality of semiconductor chips stacked on the chip carrier in a stepped manner that an overlying chip mounted on an underlying chip of the plurality of semiconductor chips has a suspended portion free of being in contact with the underlying chip; and a bump mounted on the chip carrier at a position corresponding to a suspended side of the stacked semiconductor chips where the suspended portion of the overlying chip is located. The bump can serve as a blocking member or a filling member to prevent the semiconductor chips from delamination or formation of voids during a molding process.

Abstract: As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.

Abstract: An integrated circuit device includes a die having an interconnect structure formed over a surface thereof. A volume of compliant material located within the interconnect structure underlies one or more bond pads disposed on an uppermost layer of the interconnect structure. The compliant material may absorb stresses exerted on the interconnect structure during assembly, testing, or subsequent operation. Other embodiments are described and claimed.

Abstract: Disclosed herein are a via hole having a fine hole land with which the density of circuit patterns can be increased and a method for forming the same. The method comprises: step 1 of forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; step 2 of forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and step 3 of forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.

Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a flexed microelectronic die mounted to the support member. The flexed microelectronic die has a plurality of terminals electrically coupled to the support member and an integrated circuit operably coupled to the terminals. The die can be a processor, memory, imager, or other suitable die. The support member can be a lead frame, a plurality of electrically conductive leads, and/or an interposer substrate.

Abstract: A semiconductor device (20) in which a semiconductor element (2) is mounted on one of a front side and a back side of a wiring board (3), and a plurality of lands (9)(23) for external connection are provided on the other side of the wiring board, the land (9)(23) including a land terminal (10)(24) formed on the wiring board and a spherical solder ball (11)(25) formed on the land terminal, wherein a first land (23) immediately below an outer end corner (B) of the semiconductor element (2) is larger in size than the other lands (9).

Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

Abstract: An LED assembly includes a packaged LED module (30) and a heat dissipation device (50). The LED module includes at least an LED die therein and a plurality of conductive pins (32, 34) extending downwardly from a bottom portion thereof. The heat dissipation device is thermally and electrically connected with the at least an LED die. The heat dissipation device defines at least a mounting hole (542) therein. At least one of the conductive pins is fittingly received in the at least a mounting hole and thermally and electrically connects with the heat dissipation device.

Abstract: A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.

Abstract: In a circuit module for a high frequency, a resistance film is formed on a side of a semiconductor circuit chip, mounted above a dielectric substrate through ground metal layers, opposite to the dielectric substrate. A distance from the ground metal layer to the resistance film is a ¼ wavelength at a predetermined frequency, and the resistance film has a sheet resistance equal to a characteristic impedance of air. A second dielectric substrate with the metal layer formed on a side opposite to the resistance film can be mounted. When being adhered to the second dielectric substrate, the resistance film has a characteristic impedance determined by a permittivity of a material of the semiconductor circuit chip. When being formed in space from the semiconductor circuit chip, the resistance film has a sheet resistance equal to a characteristic impedance of air. The thickness of the second dielectric substrate is a ¼ wavelength in a desired frequency.

Abstract: An integrated circuit chip has a dielectric surface layer and, below this layer, internal pads. The chip is fabricated by producing multiplicities of vias made of an electrically conducting material which pass through said surface layer and are positioned respectively above the internal pads. Projecting external contact pads are formed on the surface layer and connected respectively to the multiplicities of vias.

Abstract: A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path. Thus, density of the electricity charged on the package seal resin or the surface of the buffer coat film is lowered, and electric discharge can be suppressed. Since the electric discharge is suppressed, no high voltage is applied to an external input/output terminal. As a result, it is possible to prevent a circuit metal wire connected to an integrated circuit from being fused and an interlayer insulating film from being damaged.

Abstract: A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die and a bumped packaged IC device. The projections are arranged to make electrical contact with the solder balls of a bumped IC device without substantially deforming the solder ball. Accordingly, reflow of solder balls to reform the solder balls is not necessary with the contact pad of the present invention. Such a contact pad may be provided on various testing equipment such as probes and the like and may be used for both temporary and permanent connections.

Abstract: An electronic device includes an electronic part including at least one first electrode, a substrate including at least one second electrode, and at least one bump formed on the at least one first electrode and formed from an elastic conductive resin including a resin having rubbery elasticity, and an acicular conductive filler including a surface layer coated with one of gold, silver, nickel, and copper. The at least one first electrode and the at least one second electrode are electrically connected to each other by mechanically contacting the at least one bump with the at least one second electrode.

Abstract: A semiconductor device, including a semiconductor chip having electrodes, a substrate having an interconnect pattern, and an adhesive, the adhesive having a first portion and a second portion, the first portion interposed between a surface of the substrate on which the interconnect pattern is formed and a surface of the semiconductor chip on which the electrodes are formed, the second portion not overlapping with the semiconductor chip. Further disclosed is the semiconductor device mounted on the circuit board and an electronic instrument having the semiconductor device.

Abstract: A semiconductor device includes an insulation film 6 formed on a silicon substrate 1, a buried interconnect 10 formed in the insulation film 6, and a barrier metal film A1 formed between the insulation film 6 and the buried interconnect 10. The barrier metal film A1 is formed of a lamination layer of a metal compound film 7 and a metal film 9 which does not loose its conductivity when being oxidized. In the vicinity of an interface between the metal compound film 7 and the metal film 9, a fusion layer 8 obtained through fusion of the metal compound film 7 and the metal film 9 is provided.

Abstract: A semiconductor device may include the following. A diffusion barrier formed over a semiconductor substrate having a conductive layer. An etching stop layer formed over a diffusion barrier. Inter-metal dielectric (IMD) layers (e.g. having via holes formed over an etching stop layer and trenches wider than the via holes). Metal interconnections that fill via holes and trenches. Via holes in IMD layers may pass through a diffusion barrier and an etching stop layer to connect to a conductive layer in a semiconductor substrate.

Abstract: A relay board provided in a semiconductor device, including an entire main surface that is made of a conductive material. The relay board may further include a substrate made of the same material as at least one semiconductor element provided in the semiconductor device. The main surface of the relay board may be formed at an upper part of the substrate.

Abstract: A semiconductor device includes a first wiring layer having a first wiring, a second wiring layer having a second wiring formed over the first wiring layer, and a first insulating layer interposed between the first and second wiring layers, wherein the second wiring layer or an upper layer thereof has a fine projection, and the diameter of a circle circumscribing the projection in a plane or sectional view is 40 nm or less.

Abstract: A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Abstract: A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps is formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.

Abstract: A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.

Abstract: Devices and methods for electrical interconnection for microelectronic circuits are disclosed. One method of electrical interconnection includes forming a bundle of microfilaments, wherein at least two of the microfilaments include electrically conductive portions extending along their lengths. The method can also include bonding the microfilaments to corresponding bond pads of a microelectronic circuit substrate to form electrical connections between the electrically conductive portions and the corresponding bond pads. A microelectronic circuit can include a bundle of microfilaments bonded to corresponding bond pads to make electrical connection between corresponding bonds pads and electrically-conductive portions of the microfilaments.

Abstract: A semiconductor device having a molded package includes a semiconductor chip, a thick-film lead electrode to which the semiconductor chip is die-bonded, a thin-film lead electrode having a thickness smaller than that of the thick-film lead electrode, a wire which electrically connects the semiconductor chip to the thin-film lead wire, and a molding material in which the semiconductor chip and the wire are encapsulated. A portion of a lower surface of the thick-film lead electrode is exposed at a package lower surface as a heat dissipating electrode. A portion of an upper surface of the thin-film lead electrode is exposed at a package upper surface as an input/output electrode. A portion of an upper surface of the thick-film lead electrode is exposed at the package upper surface as a grounding electrode.

Abstract: A fine-sized chip package structure is disclosed to include a memory chip, a leadframe having a plurality of leads bilaterally arranged on the bottom surface of the memory chip, gold wires connected between respective bonding pads at the middle part of the bottom surface of the memory chip and respective stitches at the bottom surface of each rectangular block-like lead of the leadframe, and a molding compound locally molded on a part of the memory chip and a part of each leadframe with a difference of elevation between the bottom surface of the molding compound and the bottom surfaces of the leads of the leadframe for receiving a solder material used to bond the memory chip and the leadframe to a circuit board, preventing overflow of the solder material during bonding of the memory chip and the leadframe to the circuit board.

Abstract: A semiconductor device includes a pair of power chips, an IC chip, a plurality of leads one of which having a die pad on which the power chips are mounted and another one having a die attach portion on which the IC chip is mounted, a resin sheet firmly adhered to one side of the die pad, and a resin casing made by molding operation to encapsulate the power chips, the IC chip and the resin sheet by a resin in such a manner that one surface of the resin sheet opposite the die pad is exposed to the exterior of the resin casing. The resin casing has a groove formed in one surface opposite the exposed surface of the resin sheet, the groove extending parallel to the resin sheet and perpendicular to a runner through which the resin was supplied in the molding operation.