Abstract: A thyristor has a radiation-sensitive breakdown structure (20), a gate electrode (92) that is placed at a distance from the latter in a lateral direction and an ignition stage structure having at least one ignition stage (51, 91) equipped with an n-doped auxiliary emitter (51), which forms a pn-junction (55) together with the p-doped base (6), the thyristor being both electrically and radiation-ignited. In a method for contacting a thyristor that can be ignited by radiation with a gate electrode (92), a contact ram (200) that is adapted to the geometry of the gate electrode (92) is pressed against the thyristor. In a method for monitoring the ignition of a thyristor that is ignited by incident radiation, the electric voltage that is applied to the gate electrode (92) or the electrically conductive electrode (105, 201) is monitored.

Abstract: Embodiments relate to a semiconductor device and a method of manufacturing the same. According to embodiments, a semiconductor device may include a gate insulating layer and a gate electrode formed on a semiconductor substrate with an isolation layer, a low-density junction region formed at both sides of the gate electrode, a patterned insulating layer formed while exposing a portion of the low-density junction region, and a high-density junction region formed beneath the exposed low-density junction region of the semiconductor substrate.

Abstract: An ESD protection device with a silicon controlled rectifier (SCR) structure which is applied to a nano-device-based high-speed I/O interface circuit and semiconductor substrate operated by a low power voltage. The triple-well low-voltage-triggered ESD protection device includes: a deep n-type well formed on a p-type substrate; n- and p-type wells formed to be mutually connected in the deep n-type well; and a bias application region for applying a direct bias voltage to the p-type well.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A self-standing gallium nitride-based semiconductor single crystal substrate has a surface (Ga-face) mirror-polished, and a rear surface (N-face) having an arithmetic mean roughness Ra of 1 micrometer or more and 10 micrometers or less. A nitride semiconductor device is fabricated such that, before the gallium nitride-based semiconductor single crystal substrate is attached to a substrate holder of a vapor phase growth apparatus, the substrate is adjusted such that its rear surface (N-face) has a arithmetic mean roughness Ra to be in face-to-face contact with the substrate holder.

Abstract: A material of a gate electrode is a conductive oxide having a higher work function than that of conventionally used Pd and so on, thereby achieving a normally-off transistor without reducing the sheet carrier concentration of a heterojunction. It is thus possible to achieve a normally-off operation while reducing an increase in the specific on-state resistance.

Abstract: On a semiconductor substrate having a lamination structure in which Si and SiGe are stacked together, a gate electrode is formed, with a gate insulating film interposed between the semiconductor substrate and the gate electrode. Further, a channel region is provided in a surface of the semiconductor substrate, which is located below the gate electrode. On the surface of the semiconductor substrate, source and drain regions are formed such that the channel region is interposed between the source and drain regions. The concentration of Ge in a region located below the channel region is different from that of Ge in the source and drain regions.

Abstract: This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN barrier and a GaN buffer, with the channel disposed, when present, at the interface of the barrier and the buffer. Surface treated with ammonia plasma resembles untreated surface. The method pertains to treatment of the device with ammonia plasma prior to passivation to extend reliability of the device beyond a period of time on the order of 300 hours of operation, the device typically being a 2 DEG AlGaN/GaN high electron mobility transistor with essentially no gate lag and with essentially no rf power output degradation.

Abstract: Provided are a hetero-junction bipolar transistor (HBT) that can increase data processing speed and a method of manufacturing the hetero-junction bipolar transistor.

Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.

Abstract: Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical direction of the trench line, a drain region on an opposite side of the gate line to the common source region, a drain contact over the drain region, and a uniform by-product layer on the common source region.

Abstract: A solid-state imaging device includes a transfer element line for transferring an electric charge that is photoelectrically converted in a photoelectric conversion element line formed of a plurality of photoelectric conversion elements, and a charge detector for detecting an electric charge that is transferred by the transfer element line. The charge detector includes output gates disposed adjacently to a final transfer gate of the transfer element line, a reset gate for resetting an electric charge in the charge detector, a floating diffusion formed on a substrate surface adjacently to the output gates and the reset gate, and addition gates formed above the floating diffusion and along the direction from the output gates to the reset gate.

Abstract: A transistor has a source electrode (22) on the opposite side of a semiconductor body layer (10) to a gate electrode (4) insulated from the body layer (10) by gate insulator (8). The source electrode (22) has a potential barrier to the semiconductor body layer (10), for example a Schottky barrier. At least one drain electrode (54) is also connected to the semiconductor body layer (10). A suitable source-drain voltage and gate voltage depletes the region of the semiconductor body layer adjacent to the source electrode (22), and then source-drain current is controlled by the gate voltage.

Abstract: In case that a conventional TFT is formed to have an inversely staggered type, a resist mask is required to be formed by an exposing, developing, and droplet discharging in forming an island-like semiconductor region. It resulted in the increase in the number of processes and the number of materials. According to the present invention, a process can be simplified since after forming a source region and a drain region, a portion serving as a channel region is covered by an insulating film serving as a channel protecting film to form an island-like semiconductor film, and so a semiconductor element can be manufactured by using only metal mask without using a resist mask.

Abstract: A photodiode and method of forming a photodiode has a substrate. An absorption layer is formed on the substrate to absorb lightwaves of a desired frequency range. A multiplication structure is formed on the absorption layer. The multiplication layer uses a low dark current avalanching material. The absorption layer and the multiplication layer are formed into at least one mesa having in an inverted “T” configuration to reduce junction area between the absorption layer and the multiplication layer. A dielectric layer is formed over the at least one mesa. At least one contact is formed on the dielectric layer and coupled to the at least one mesa.

Abstract: Channel stop sections are formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.

Abstract: A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow trench isolations. The height of top surface of a filling oxide film in the shallow trench isolation which is adjacent to each drain contact is equal to that of top surface of the drain region. The top surface of a filling oxide film in the shallow trench isolation which is adjacent to each channel region is higher than a top surface of the semiconductor substrate in the channel region.

Abstract: A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element.

Abstract: Patterning method, and field effect transistors An explanation is given of, inter alia, a patterning method, in which a filling material (22) with a T-shaped cross section is used as a mask during patterning in order to produce structures having sublithographic dimensions, in particular a double-fin field effect transistor.

Abstract: A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.

Abstract: Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon body of the memory cell. A layer of a high-k dielectric and at least a metal layer cover the silicon bodies and their overlying layers. Next, gain regions of the transistors are filled with polysilicon. Thus, a gate is formed on the top surface and both sidewalls of a tri-gate transistor. Thereafter, the high-k dielectric and the metal layer overlying the insulative layer of the memory cell are removed to expose the insulative layer. Thus, two electrically-isolated gates of the memory cell are formed.

Abstract: A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma reaction films grown in a plasma atmosphere to cover the top surfaces of the first gate electrode and first source and drain.

Abstract: A semiconductor device and a method for manufacturing the same are provided, in which the work function of a gate electrode being in contact with a gate insulating film can be efficiently adjusted while depletion of the gate electrode is suppressed. An SOI substrate is composed of a p-type silicon substrate, a buried oxide film, and a single crystal silicon layer. Furthermore, source and drain regions are provided in the single crystal silicon layer. In the single crystal silicon layer, the surface between the source and drain regions serves as a channel layer. A gate insulating film is formed on the single crystal silicon layer (the channel layer). On the gate insulating film is provided a polysilicon gate electrode composed of metal particles of TiN and a polysilicon film. The metal particles of TiN include particles being in contact with the gate insulating film and particles being out of contact with this film.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an LDD which may include a space having a first width and may be formed in a semiconductor substrate, a channel area which may be formed in the semiconductor substrate within a space having a first width, a gate insulating layer which has a width wider than the first width and may be formed on an upper side of the channel area on the semiconductor substrate, a gate which may be formed with the first width on the gate insulating layer, and a spacer including a first spacer formed at both sides of the gate insulating layer and a second spacer formed at sidewalls of the gate.

Abstract: Disclosed are a vertical color filter detector group (image sensor) and a method for manufacturing the same, capable of simplifying a manufacturing process by reducing the number of ion implantations and masks for connecting a green sensitive layer and a red sensitive layer to a sensor on a surface of a silicon substrate. The image sensor includes a semiconductor substrate on which first and second conductive type silicon layers are stacked, and having at least two second conductive type regions at different depths from the semiconductor surface, a trench having a bottom lower than a first region farthest away from the semiconductor surface, to set a peripheral border area of a unit pixel, an insulating layer in the trench in contact with an interfacial surface between the semiconductor and the trench, a channel area in an active area between the first and second regions without contacting the interfacial surface between the semiconductor and the trench, and a transfer gate in the insulating layer.

Abstract: CMOS image sensor devices and fabrication methods thereof. A CMOS image sensor device comprises an array of photo-sensing pixels in a first region of a substrate. Each photo-sensing pixel comprises a fully non-salicide transistor and a pinned photodiode. A logic circuit comprises a complementary metal oxide semiconductor (CMOS) transistor in a second region of the substrate, wherein a salicide is formed on the CMOS transistor in the second region but non-salicide is formed on the first region of the substrate.

Abstract: A thin film transistor (TFT) array substrate for reducing electrostatic discharge damage includes a substrate, a plurality of pixel units, scan lines and data lines. The substrate has a pixel area and a peripheral area adjacent to the pixel area. The pixel units are disposed in the pixel area. The scan lines and data lines are disposed in the pixel area of the substrate and electrically connected with the pixel units, wherein one end of each scan line extending to the peripheral area is a bonding pad for the scan line. One end of each data line extending to the peripheral area is a bonding pad for the data line. The other end of each data line extending to the peripheral area is an end part of the data line. Particularly, the end part of the data line does not exceed the outmost scan line.

Abstract: A system for manufacturing a flat panel display includes a substrate storage part for storing a plurality of substrates; a first chamber including a substrate loading part for loading the plurality of substrates; a substrate transfer part, disposed between the substrate storage part and the first chamber, including an end effector for transferring the plurality of substrates between the substrate storage part and the substrate loading part; a second chamber including a source gas supplying part for uniformly supplying source gas to the entire surface of the plurality of substrates and a substrate heating part for heating the plurality of substrates; and a source powder supplying part including a source powder evaporating part for evaporating source powder in order to supply the source gas to the source gas supplying part and a source powder storage part for supplying the source powder to the source powder evaporating part.

Abstract: A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio are provided. The solid-state imaging device comprises an integrated array of a plurality of pixels, each of which comprises a photodiode PD for receiving light and generating photoelectric charges, a transfer transistor Tr1 for transferring the photoelectric charges, and a storage capacitor element C connected to the photodiode PD at least through the transfer transistor Tr1 for accumulating, at least through the transfer transistor Tr1, the photoelectric charge overflowing from the photodiode PD during accumulating operation.

Abstract: A color multiple sensor pixel image sensor includes multiple photo-sensing devices, a combined photosensing and charge storage device, and multiple triggering switches. Each of the multiple photo-sensing devices is structured for conversion of photons of one differentiated color component to photoelectrons. The combined photosensing and charge storage device is structured for conversion of photons of a principal color photoelectrons and connected to sequentially receive photoelectrons from each of the multiple photo-sensing devices. Each triggering switch is connected such that photoelectrons are selectively and sequentially transferred from each of the multiple photo-sensing devices to the combined photosensing and charge storage device.

Abstract: Adjacent pixels in a pixel circuit of an imaging device use a primary capacitance, an amplifying transistor, a reset switch and a selection switch in common. Each pixel has a photodiode and a transfer switch having first and second gates provided on the photodiode side and the primary capacitance side, respectively. In a pixel downsampling read mode, the first and second gate voltages of each pixel to be discarded are brought to high level, and thereafter the first and second gate voltages of each pixel to be read are brought to high level, to transfer charge generated in the photodiode of the pixel to be read to the primary capacitance and the photodiode in each pixel to be discarded. This enables reduction of the potential of the primary capacitance, and hence reduction of the pixel sensitivity than using only the primary capacitance to store charge transferred from the transfer switch.

Abstract: A ferroelectric memory includes a ferroelectric capacitor formed from a lower electrode, an upper electrode and a ferroelectric layer interposed between the lower electrode and the upper electrode; and a metal wiring provided in an interlayer dielectric film, wherein a portion of the metal wiring that may otherwise come in contact with the interlayer dielectric film is covered by a diffusion prevention film.

Abstract: Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer is then selectively recessed with a peroxide mixture and subsequently the HSG silicon layer is recessed using tetramethyl ammoniumhydroxide. Thus, the bottom electrode is recessed below the level of particles which may overlie the memory cell capacitors and cause shorts by contacting the bottom electrode.

Abstract: The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.

Abstract: A semiconductor device includes a capacitor formed by successively stacking a lower electrode, a capacitor dielectric film and an upper electrode on a substrate. The lower electrode includes a first conducting layer and a second conducting layer formed on the first conducting layer and having higher resistivity than the first conducting layer, and the capacitor dielectric film is formed so as to be in contact with the second conducting layer of the lower electrode.

Abstract: A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory cell comprises a straddle gate, a carrier trapping structure and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping structure is located between the straddle gate and the substrate, wherein the carrier trapping structure comprises a trapping layer directly in contact with the straddle gate and a tunnel layer located between the trapping layer and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

Abstract: A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates is higher than that of the select gate forming a hollow structure on the select gate between the two floating gates. The control gate disposed on the substrate covers the select gate and the two floating gates and fills the hollow structure. The doped region is disposed in the substrate on one side of the two floating gates opposite to the select gate.

Abstract: A structure and a manufacturing method for an OTP-EPROM in an embedded EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. The structure has a gate dielectric is overlying the surface region. The structure also a first OTP-EPROM gate overlying the gate dielectric layer in a first cell region, and an EEPROM floating gate and a select gate overlying the gate dielectric layer in a second cell region. An insulating layer is overlying the first OTP-EPROM gate, the EEPROM floating gate and the select gate. An OTP-EPROM control gate is overlying the insulating layer and coupled to the first OTP-EPROM gate. An EEPROM control gate is overlying the insulating layer and coupled to the EEPROM floating gate.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film which is formed on the semiconductor substrate, a floating gate electrode which is formed on the first insulating film and made of a conductive metal oxide, a second insulating film which is formed on the floating gate electrode, has a relative dielectric constant of not less than 7.8, and is made of an insulating metal oxide of a paraelectric material, and a control gate electrode which is formed on the second insulating film and made of one of a metal and a conductive metal oxide.

Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes source/drain diffusion layers, a first insulation film on a channel between the source/drain diffusion layers, a floating gate electrode on the first insulation film and composed of first electrically conductive layers, a second insulation film on the floating gate electrode, and a control gate electrode on the second insulation film. In the case where one first electrically conductive layer excluding a top layer is defined as a reference layer among first electrically conductive layers, a work function of the reference layer is 4.0 eV or more and work functions of the reference layer and of the first electrically conductive layers above the reference layer gradually increase as the layers are proximal to the second insulation film.

Abstract: An electrically erasable and programmable read only memory (EEPROM) is fabricated by forming isolation patterns defining active regions in predetermined regions of a semiconductor substrate including a memory transistor region and a selection transistor region. A gate insulating layer having tunnel regions is formed on the active regions. A first conductive layer is formed on the resultant structure having the gate insulating layer. The first conductive layer is patterned to form openings exposing top surfaces of the isolation patterns. The patterning takes place such that a distance between a selected opening and the active region adjacent the opening varies depending on the width of the isolation pattern disposed under the opening. Related EEPROM devices are also disclosed.

Abstract: According to an aspect of the invention, a nonvolatile semiconductor memory comprises: a semiconductor substrate; a trench formed in the semiconductor substrate; a first insulating film being formed on a wall surface of the trench; a floating gate electrode formed on the first insulating film inside the trench; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a channel region formed between the source region and the drain region in the semiconductor substrate, a second insulating film formed on a surface of the semiconductor substrate; and a control gate electrode formed on the channel region and a surface of the second insulating film. The channel region is adjacent to the trench. A storage state of the nonvolatile semiconductor memory is formed by injecting or drawing charge into or from the floating gate electrode when a tunnel current flows through the first insulating film.

Abstract: A nonvolatile semiconductor memory includes active regions . . . AAj-1, AAj, AAj-1, . . . formed in a semiconductor substrate; a plurality of word lines WL0, WL1, . . . in the row direction; memory cell transistors, each including a floating gate provided on the semiconductor substrate via a tunneling insulating film, an inter-gate insulating film disposed on the floating gate, and a control gate disposed on the inter-gate insulating film, disposed on intersections of word lines and active regions; select gate lines SGD in the row direction; bit line contacts CB disposed on the active regions; and a plurality of bit lines in the column direction and connected to the active regions via the bit line contacts; and the bit line contacts are formed by forming an electrode material for the bit line contacts in lines in the row direction and cutting the electrode material for each of the bit lines to avoid contact-failure of bit line contacts CB.

Abstract: A high voltage integrated circuit contains a freewheeling diode embedded in a transistor. It further includes a control block controlling a high voltage transistor and a power block—including the high voltage transistor—isolated from the control block by a device isolation region. The high voltage transistor includes a semiconductor substrate of a first conductivity type, a epitaxial layer of a second conductivity type on the semiconductor substrate, a buried layer of the second conductivity type between the semiconductor substrate and the epitaxial layer, a collector region of the second conductivity type on the buried layer, a base region of the first conductivity type on the epitaxial layer, and an emitter region of the second conductivity type formed in the base region. The power block further includes a deep impurity region of the first conductivity type near the collector region to form a PN junction.

Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Abstract: A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or LaAlO3. A charge trapping layer is formed over the tunnel barrier. A high-k charge blocking layer is formed over the charge trapping layer. A control gate is formed over the charge blocking layer. Another embodiment forms a floating gate over the tunnel barrier that is comprised of two oxide layers with an amorphous layer of silicon and/or germanium between the oxide layers.

Abstract: A semiconductor device includes a semiconductor layer formed on a semiconductor substrate by epitaxial growth, a first embedded insulating layer embedded in a first region between the semiconductor substrate and the substrate layer, and a second embedded insulating layer embedded in a second region between the semiconductor substrate and the semiconductor layer, wherein the first embedded insulating layer and the second embedded insulating layer are mutually different in at least either of effective work function and fixed charge amount.

Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a plurality of first cylindrical semiconductor pillar regions of the first conductivity type periodically provided on a major surface of the semiconductor layer; a plurality of second cylindrical semiconductor pillar regions of a second conductivity type provided on the major surface of the semiconductor layer and being adjacent to the first semiconductor pillar regions; a plurality of first semiconductor regions of the second conductivity type provided in contact with the top of the second semiconductor pillar regions; second semiconductor regions of the first conductivity type selectively provided on the surface of the first semiconductor regions; a first main electrode provided on the first semiconductor region and the second semiconductor region; an insulating film provided on the first semiconductor pillar regions, the first semiconductor regions, and the second semiconductor regions; a control electrode provided on the