Abstract: A system for detecting a rail break or train occupancy includes a current source adapted to deliver a current to an isolated block of a rail track. A voltage sensor is coupled to the isolated block and configured to detect voltage across the isolated block. A shunt device is coupled to the isolated block and configured to receive a shunt current from the current delivered by the current source. A shunt current sensor is coupled to the shunt device and adapted to detect the shunt current flowing through the shunt device. A control unit is adapted to receive input from the voltage sensor and the shunt current sensor and to monitor a variation of the shunt current with respect to the voltage to detect the rail break or train occupancy.

Abstract: A magnetic-field-measuring probe includes at least one magnetoresistive or magnetoinductive sensor which is sensitive to the magnetic field along a privileged measurement axis. The probe includes: at least two magnetoresistive or magnetoinductive sensors (14, 16) which are rigidly connected to one another in a position such that the privileged measurement axes thereof are parallel and offset in relation to one another in a direction that is transverse to the privileged measurement axes; and output terminals specific to each magnetoresistive or magnetoinductive sensor, in order to supply a signal that is representative of the magnetic field measured by each sensor along the privileged measurement axis thereof.

Abstract: A probe station allows for effective EMI shielding of the passage of the probe through the wall of the housing of such probe station. The probe is freely movable in the X, Y and Z directions. The probe station comprises a housing having at least one aperture through which a probe can extend, a chuck for supporting a test device, the chuck being arranged inside the housing, at least one probe support for supporting a probe, the probe support being arranged relative to the housing such that a first portion of the probe extends into the housing through one of said apertures, at least one positioning mechanism enabling at least one of said probe and said chuck to move relative to the other, and is characterized in that at least one electrically conductive, elastic bellows is attached to the edge of an aperture which provides a variable passage for the probe.

Abstract: Method and apparatus using a retention arrangement with a potting enclosure for holding a plurality of probes by their retention portions, the probes being of the type having contacting tips for establishing electrical contact with pads or bumps of a device under test (DUT) to perform an electrical test. The retention arrangement has a top plate with top openings for the probes, a bottom plate with bottom openings for the probes, the plates being preferably made of ceramic with laser-machined openings, and a potting enclosure between the plates for admitting a potting agent that upon curing pots the retaining portions of the probes. In some embodiments a spacer is positioned between the top and bottom plates for defining the potting enclosure. Alternatively, the retention arrangement has intermediate plates located in the potting enclosure and having probe guiding openings to guide the probes.

Abstract: A probe card and its corresponding illumination device are provided for performing electrical operating tests, preferably done in parallel, with respect to a plurality of chips provided with connection pads, under illumination conditions given by a lighting source, the probe card being a printed circuit board (PCB) including electrical connections to the chip on its lower face, the probe card also including electrical connections to the lighting.

Abstract: The present invention provides a probe test apparatus capable of easily correcting a probe needle of a probe card. A pad image by which the position of an electrode pad P can be specified is captured from a semiconductor wafer, and the captured pad image is stored. While capturing a probe image by which the position of the tip Q of a probe needle can be specified from a probe card, the probe image is displayed while being overlaid on the inverted pad image in a real time manner. Since the positional relation of the probe needle with respect to the electrode pad P is displayed in a real time manner, at the time of correcting a probe needle with tweezers or the like with reference to the image, the operator can correct the probe needle while observing the state of the probe needle in a real time manner.

Abstract: A second temperature control mechanism is configured by providing a gas circulator circulating a gas, in this case air, with an expected temperature, a pair of temperature sensors installed on upper and lower side surfaces of a mounted probe card respectively, and a gas temperature controller adjusting and controlling the temperature of the air circulated in the gas circulator.

Abstract: Optoelectronic properties of optical communication LEDs, LDs and PDs should be examined in a wide range of temperatures between ?40° C. and +85° C. Low temperature photocharacteristics of as-chip devices are tested by preparing an inspection stage cooled at a low temperature encapsulated in a shield casing with a front opening, conveying a chip of LD, LED or PD by a collet via the opening, placing the chip on the cold stage, blowing the stage and chip with cool dry air for preventing the chip from wetting, touching the chip by a probe, applying a current/voltage to the chip, examining emission/detection of the chip and taking the chip off via the opening by the collet.

Abstract: A method, system and device for testing an integrated circuit or device under test over a range of temperatures with a plunger, clamp or lid over the integrated circuit or device under test is disclosed.

Abstract: Devices to be tested using the measuring terminal of a semiconductor testing apparatus are increased in number. The devices can be formed by executing a step at which a plurality of integrated circuits are provided on a wafer, a photomask for use in forming the integrated circuits is provided with first to nth device patterns, and test result outputs for use in checking that certain functions of the integrated circuits are normal have mutually different characteristics at the individual integrated circuits which correspond to the first to nth device patterns. This makes it possible to observe the test result outputs of the integrated circuits through the use of the common measuring device (measuring terminal) of the semiconductor testing apparatus and more easily increase the number of the devices to be measured simultaneously.

Abstract: A method of measuring variability of integrated circuit components is provided. A specified parameter of at least one first array configuration comprising a plurality of the integrated circuit components without specified internal connections between the integrated circuit components is measured. The specified parameter of at least one second array configuration comprising a plurality of the integrated circuit components nominally identical to those of the first array configuration with specified internal connections between the integrated circuit components is also measured. A variation coefficient is determined for the integrated circuit components based on the measured specified parameter of the at least one first array configuration and the at least one second array configuration.

Abstract: An automated platform for electronic apparatus environmental testing and the methods of its operation holds and positions electronic devices during environmental testing. The automated platform may be a multi-legged table and includes a surface for providing vertical support. A plurality of bracket mechanisms, each hold in position an electronic device. A bracket positioning mechanism associates with the plurality of bracket mechanisms for controllably positioning the bracket mechanisms. Control circuitry associated with the bracket turntable controls the positioning of the bracket mechanisms. At least one brush mechanism may be positioned in association with the bracket mechanisms for brushing said bracket mechanisms and an electronic device held in position by said bracket mechanism.

Abstract: A semiconductor device test method for testing a semiconductor device is disclosed. In one embodiment, for transmitting control information to a device that is connected between a test device and the semiconductor device, a non-standard-compliant signal is sent to the device. Furthermore, the invention relates to a semiconductor device test device and a device that is, for performing a semiconductor device test method, connected between a test device and a semiconductor device to be tested.

Abstract: Disclosed is a method of forming a circuit pattern on a printed circuit board. More particularly, this invention relates to a method of forming a circuit pattern on a printed circuit board, including filling a grooved plate having grooves corresponding to a desired circuit pattern in the surface thereof with a conductive material and then bringing portions of the grooved plate sequentially into contact with the surface of the base substrate on which a circuit pattern is formed, to thus transfer the conductive material from the grooves to the surface of the base substrate, consequently forming the circuit pattern. Thereby, according to the method of this invention, a fine circuit pattern and a light, slim, short and small product, as well as a simple process, can be realized.

Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Abstract: A method and system for sealing or covering exposed fuses on a semiconductor device are disclosed. A semiconductor device prober incorporating a spray device for applying a sealing compound to individual fuses on a semiconductor device subsequent to testing the semiconductor device is disclosed. A method and system for sealing exposed fuses on a semiconductor device is disclosed which allows the sealing step to be performed either prior to or following singulation of the semiconductor device into individual dice.

Abstract: A method and apparatus for a thermal stratification test providing cyclical and steady-state stratified environments. In order to test an electronic device, for example one having one or more levels of ball-grid-array interconnections, e.g., connecting a chip to a flip-chip substrate and connecting the flip-chip substrate to a printed circuit board of a device, an apparatus and method are provided to heat one side of the device while cooling the second side. In some embodiments, the process is then reversed to cool the first side and heat the second. Some embodiments repeat the cycle of heat-cool-heat-cool several times, and then perform functional tests of the electronic circuitry. In some embodiments, the functional tests are performed in one or more thermal-stratification configurations after cycling at more extreme thermal stratification setups. In some embodiments, a test that emphasizes solder creep is employed.

Abstract: Provided is a power supply noise resistance testing circuit, in which a test pattern is applied to a data input portion of a functional block formed on a semiconductor chip and a voltage on which a power supply noise is superimposed is supplied to a power supply portion of the functional block, thereby testing a power supply noise resistance of the functional block. In the power supply noise resistance testing circuit, a power supply noise generating circuit for generating the power supply noise is provided around or inside the functional block. A power supply of the power supply noise generating circuit is connected with a power supply of the functional block through a connection path to transmit the power supply noise.

Abstract: The present invention relates to a finely programmable Josephson voltage standard device employing microwave driving of multiple frequencies. To this end, the programmable Josephson voltage standard device includes a first element group 10a having the plurality of Josephson junctions 2 connected in series and applied with a first frequency f1; a second element group 20a having a plurality of Josephson junctions 2 connected in series and applied with a second frequency f2 different from the first frequency f1; and current bias meant for selectively applying positive (+) current or negative (?) current to the Josephson junctions 2 of the element groups 10a, 20a or stopping the supply of the current, in response to an input command. The first element group 10a and the second element group 20a are connected in series.

Abstract: Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

Abstract: A bidirectional current-mode transceiver is provided for improving transmission rates on a transmission line in a manner of current signal transmission, and for reducing the swing of the voltage signal on the transmission line by using a termination resistor, thus improving operating speed. Therefore, the provided transceiver can be applied to a long transmission line.

Abstract: A switch circuit includes first switches; and second switches. The first switches and the second switches are alternately arranged one by one, and a semiconductor substrate is of a first conductive type. Each of the first switches comprises a first transistor of a second conductive type which is opposite to that of the semiconductor substrate, and each of the second switches includes a second transistor of the second conductive type, surrounded by an outer well of the second conductive type.

Abstract: A signaling device is described. The signaling device may include a group of four signal nodes, four differential receivers and a logic circuit. The group of four signal nodes may receive a sequence of data bits during a sequence of bit times. A respective differential receiver of the four differential receivers may be coupled to two respective signal nodes in the group of four signal nodes. The logic circuit may extract common-mode data from signals on the group of four signal nodes using outputs from the four differential receivers such that three data bits are received on the group of four signal nodes during each bit time of the sequence of bit times.

Abstract: A power supply monitoring circuit is provided that utilises an adaptive internal control of the refresh rates of capacitors to reduce the power requirements of the circuit. The circuit provides at an output a signal indicative of the level of the supply voltage relative to a predetermined reference voltage.

Abstract: An integrated connecting device for coupling a communication link to a powered device (PD) in a system for supplying power to the PD over the communication link. The integrated connecting device has a housing configured for providing connection to the PD external with respect to the housing, communication interface circuitry coupled to the communication link for supporting data communication of the PD over the communication link, and power interface circuitry coupled to the communication interface circuitry for implementing a power supply protocol performed to supply power to the PD over the communication link. The communication interface circuitry and the power interface circuitry being held by the housing.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: In various embodiments, power multipliers and associated methods are provided that employ parametric excitation. In one embodiment, a ring power multiplier is provided that has a ring. A parametric reactance is associated with the ring that negates at least a portion of a physical resistance of the ring.

Abstract: A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (1216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).

Abstract: The present invention provides a charge pump in a phase lock loop circuit. The phase lock loop circuit comprises a voltage controlled oscillator (VCO) for producing a variable frequency output signal in response to a VCO control voltage. The charge pump comprises a current generating module for providing a first current, a second circuit for providing a bias current according to a bias control signal, a current mirror circuit that comprises a first current generating unit for generating a third current proportional to a sum of the first current and the second current, and a second current generating unit for generating a fourth current proportional to the sum of the first current and the second current, a first switch for sourcing the third current according to a first control signal and a second switch for sinking the fourth current according to a second control signal.

Abstract: A delay locked loop circuit and signal delay locking method are provided. First, the start-up circuit minimizes the delay time between an output signal and a reference signal during an initial period. Secondly, the phase correction circuit increases the delay time during an correction period. The present invention ensures that the phase difference between the output signal and the reference signal is correctly detected by the delay locked loop circuit, so that harmonic lock and phase ambiguity can be avoided.

Abstract: A delay amount variable circuit (8) adapted to change a delay amount according to a ZQ calibration result is inserted in a path of a DQ replica system. The delay amount of the path of the DQ replica system is variable and is adjusted so as to make constant a timing skew difference between a DQ buffer system and the DQ replica system. The ZQ calibration result changes depending on variations in temperature, voltage, and manufacture. Therefore, by obtaining the delay amount corresponding to these variations, there are obtained a DLL circuit with high accuracy that can make the skew difference constant, and a semiconductor device incorporating such a DLL circuit.

Abstract: A duty cycle correction amplification circuit is disclosed and comprises a first amplifier comprising dual first MOS differential input transistors gated respectively by first and second reference signals, and adapted to generate first and second preliminary signals, a second amplifier comprising dual second MOS differential input transistors respectively gated by first and second preliminary signals and adapted to generate first and second internal signals, and a duty cycle corrector adapted to correct a duty cycle associated with the first and second internal signals, wherein one of the first and second internal signals comprises an amplified output signal having a corrected duty cycle.

Abstract: A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit having low sub-threshold leakage current is provided. More particularly, a latch circuit and flip-flop that can be applied in the deep sub-micron era and that are entirely configured of only CMOS using a combination of a high threshold device and a low threshold device and a low-threshold-voltage stack structure, without using a power gating technique such as multi-threshold CMOS (MTCMOS) and a back bias voltage control technique such as variable threshold CMOS (VTCMOS), are provided.

Abstract: Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.

Abstract: Delay line circuits include a plurality of delay cells connected in series. The delay cells respectively include a first to a third logic gate. The first logic gate, in response to a selection signal, generates a first signal based on an input signal. The second logic gate generates a second signal based on the input signal in response to the selection signal.

Abstract: A current mirror circuit 30 comprises PMOS's 31 to 34. The current which was flowing when the input voltage was “H” is interrupted, when the node N34 goes from “L” to “H,” a cascode-connected PMOS 31 is automatically turned OFF. The gates of PMOS's 31 and 33 are connected by a signal line (SL) directly to a node N34. The rise time of the output voltage of a current mirror circuit and the consumption current can be reduced.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.

Abstract: A MOSFET-based, multi signal-switching circuit controllably passes analog/audio signals and digital signals through a common terminal to a single connector. Analog/audio signals are coupled through a single N-channel MOSFET analog signal switch which, when turned-ON, minimizes distortion of the analog/audio signal and capacitive loading to an adjacent, MOS-based or CMOS-based digital data signal switch. A respective turn-OFF circuit maintains its associated switch MOSFET turned OFF.

Abstract: Method for limiting the power dissipation of a power semiconductor switch (1) with a control input (20) which is connected to a controller (2), wherein a measuring device (3) generates an analog power signal (8), the signal amplitude of which corresponds to the current power dissipation in the power semiconductor switch, a comparator circuit (23) in which a comparison of the signal amplitude of the current power dissipation with a signal amplitude of a reference signal (9) is carried out and which generates a shut-off signal (10) if the signal amplitude of the analog power signal is greater than the signal amplitude of the reference signal, and the shut-off signal (10) is supplied to the control input (20) of the power semiconductor switch (1).

Abstract: A method and apparatus are provided for incorporating guided network cable Move/Add/Change (MAC) work order capability into a power patch panel. MAC work orders may be controlled and monitored using in-band signaling using, e.g., standard RJ-45 patch cords. Cable detection is performed at a port level on a real-time basis. Coordination of guided MAC operations may be performed by the patch panel, independently, or in conjunction with, or under the control of, a remote Network Management System. The patch panel may be in either an interconnect or cross-connect configuration.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: In a reference voltage generation circuit, a bandgap reference circuit (BGR circuit) 1 includes diode element D1 and D2 having different current densities, three resistive elements R1, R2 and R3, a P-type first transistor Tr1 for supplying a current to a reference voltage output terminal O, a P-type second transistor Tr2 for determining a drain current flowing through the first transistor Tr1 by a current mirror structure, and a feedback type control circuit 11. The BGR circuit 1 is connected to a pull-down circuit 2. The pull-down circuit 2 includes a resistive element R4 and a P-type transistor Tr4 which are connected in series. The resistive element R4 is connected to a drain terminal of the second P-type transistor Tr2. The P-type transistor Tr4 has a gate terminal connected to the reference voltage output terminal O and a grounded drain terminal.

Abstract: Disclosed is a reference voltage generating circuit which includes resistors R0, R0 and R3, a differential amplifier A1 and transistors Q1, Q2 and Q3. The collectors of the transistors Q1 and Q2 are connected to differential input terminals of the differential amplifier, while one ends of the R0, R0 and R3 are connected in common to an output of the differential amplifier A1. The other ends of the two resistors R0 are connected in common to the collectors of the transistors Q1 and Q2, while the other end of the resistor R1 is connected to the collector and the base of the transistor Q3, which transistor Q3 has the base connected to the bases of the transistors Q1 and Q2. The emitter size ratio of the transistors Q1 and Q2 is set to 1:N. A current of a value approximately equal to that of the collector current of the transistor Q1 or Q2 and a current with a positive temperature coefficient larger than the first-stated current are caused to flow through the resistor R1.

Abstract: A low pass filter includes a switchable resistor bank, a gain stage, and a capacitor bank. The resistors and capacitors switched into the circuit determine the cutoff frequency of the low pass filter. The frequency programmability may be obtained using the switchable resistor bank and may be implemented as a parallel bank of binary weighted resistors. Further programmability may be obtained using the switchable capacitor bank in conjunction with the switchable resistor bank. The resistor and capacitor processes in a semiconductor wafer are sufficiently accurate and repeatable so as to minimize any necessary calibration.

Abstract: In one embodiment, a power supply controller is configured to use a plurality of ramp signals to generate a plurality of PWM control signals.

Abstract: A class D amplifier is provided that is capable of reducing distortion of a specific sampling frequency, and frequencies that are multiples of this frequency to a level where an LPF is not required and small-scale control circuit. Class D amplifier 100 is provided with H (full) bridge output section 120, output control section 110 that is configured with random number generator 103 that takes individual random numbers that do not depend on input values as output values, and PWM control signal generating circuit 104 that generates a final PWM control signal from the input values and output values of random number generator 103. Output control section 110 divides a pulse signal outputted at a reference point between sampling frequencies into a plurality of pulse signals with random widths that do not include the reference point, and outputs the pulse signals with random widths.

Abstract: An amplifier circuit (100) includes a driver stage (120) with active devices (140) for pre-amplification and output of a pre-amplified signal; and an output stage (160) with active devices (180) for further amplification of the pre-amplified signal and output of an amplified signal. A detector (190) measures levels of forward and reflected parts of the amplified signal, and a control circuit (145) independently and selectively controls turning on and off of the active devices (140, 180) of the driver and output stages (120, 160) as a function of the levels of the forward and reflected signals to substantially maintain linearity of the amplifier circuit (100) with load variations.

Abstract: The present invention relates to a method and circuit arrangement for adjusting a gain, wherein said circuit arrangement comprises at least a first output branch connected to a first load and a second output branch connected to a second load. The gain control function is realized based on a current splitting, wherein a non-operated output branch is used as a kind of dummy branch for receiving a part of the output current. Thus, only as many output branches as there are outputs are required to implement a gain control based on splitting. Thereby, a complexity of the layout design is reduced and control and biasing of dummy branches is not required.

Abstract: A variable gain amplifier is provided that scarcely suffers disturbance or interference such as carrier leak from other circuit blocks even when a plurality of circuits are constructed on the same semiconductor substrate, and that has low output impedance fluctuation. For the purpose of this, in a variable gain amplifier, the ground terminal of a signal amplifying transistor is connected to a dedicated grounding pad to which the other circuit blocks are not connected, so that disturbance or interference such as carrier leak from other circuit blocks is reduced. Further, the ground terminal of an output impedance compensation circuit is also connected to the same grounding pad described above, so that further disturbance or interference is avoided. As a result, the circuit scarcely suffers disturbance or interference such as carrier leak from other circuit blocks, so that output impedance fluctuation is reduced.