Abstract: A data output circuit of a semiconductor memory device and an operation method thereof, in which global I/O lines are selectively used according to a selected output data width. The data output circuit includes an I/O sense amplifier unit that selectively senses and amplifies a part or all of read data received from a memory bank through a Local Input and Output (LIO) lines and outputs amplified data to a part of all of Global I/O (GIO) lines, respectively, in response to a data width selection signal, a pipeline latch unit that latches the amplified data received through a part or all of the GIO lines and outputs latched data, in response to latch control signals, and an output driver circuit unit that outputs output data in response to the latched data. The number of the output data is changed according to an output data width selected by the data width selection signal.

Abstract: A dual data rate (DDR) output circuit has first and second data paths therein that are asymmetric. The first data path is provided through a single-stage latch unit and the second data path is provided through a dual-stage flip-flop device containing a cascaded arrangement of two latch units. The DDR output circuit includes a latch unit, a flip-flop and a buffer circuit. The latch unit is configured to latch-in first data in-sync with a first edge of a clock signal and the flip-flop is configured to latch-in second data in-sync with the first edge of the clock signal. A buffer circuit is also provided. The buffer circuit is electrically coupled to an output of the latch unit and an output of the flip-flop. The buffer circuit is configured to generate the first data at an output terminal of the DDR output circuit in-sync with one edge (e.g. rising or falling) of the clock signal and further configured to generate the second data at the output terminal in-sync with another edge (e.g.

Abstract: A dynamic random access memory device having reduced power consumption and a refresh cycle method. The memory device includes a monitoring address storage unit storing multiple monitoring addresses, an error correction code (ECC) engine detecting whether or not an error occurs in monitoring bits corresponding to the monitoring addresses, and a refresh cycle determining circuit adjusting a self refresh cycle depending on whether or not an error occurs in the monitoring bits.

Abstract: A semiconductor integrated circuit device includes a charge transfer transistor provided between a bit line and a sense amplifier, and a bit line clamp voltage generating circuit which generates bit line clamp voltage to be applied to the gate of the charge transfer transistor. The bit line clamp voltage generating circuit includes a current mirror circuit, a resistive dividing circuit provided between the input stage of the current mirror circuit and a reference potential node, a potential setting circuit provided between the output node of the resistive dividing circuit and the output stage of the current mirror circuit, and an operational amplifier which compares potential of the input stage of the current mirror circuit with reference potential to control the current mirror circuit. The operational amplifier is configured by transistors other than intrinsic transistors. The bit line clamp voltage is derived from the output stage of the current mirror circuit.

Abstract: Methods and circuits to reduce power consumption of DRAM local word-line drivers are disclosed. A first voltage converter provides a voltage VPP1, which is lower than the voltage VPP required to operate a word-line of a DRAM cell array. A voltage detector monitors the voltage level of the local word-line driver. Once the voltage level VPP1 is reached on the local word-linedriver switching means as e.g. tri-state drivers put the final VPP voltage on the word line. This VPP voltage is the output of a second voltage boost converter. Putting the voltage in two stages on the word-line reduces the overall power consumption. The voltage level VPP1 has to be carefully selected to find a compromised solution between current consumption and performance.

Abstract: A circuit and method of driving a sub-word line of a semiconductor memory device capable of reducing power consumption is disclosed. The sub-word line driving circuit includes a first transistor, a second transistor and a third transistor. The first transistor pre-charges a boost node to a first voltage in response to a main word line driving signal. The second transistor boosts the boost node to a second voltage in response to a sub-word line driving signal, and provides the sub-word line driving signal to a sub-word line. The third transistor provides the main word line driving signal to the sub-word line in response to a third voltage that has a lower level than a logic “high” state of the sub-word line driving signal.

Abstract: A reference cell outputs a reference current of a data reading current of a memory cell. A trimming data in accordance with the reference current is memorized in a non-volatile memory cell. A standard current generator outputs a standard current whose current quantity is adjusted in accordance with the trimming data. A current comparator compares the standard current to the reference current. The output of the reference current from the reference cell is adjusted through a reference cell adjuster based on a result of the comparison by the current comparator.

Abstract: A voltage boosting circuit of a semiconductor memory device for decreasing power consumption can include a first precharge circuit, a second precharge circuit, a first capacitive element, a second capacitive element and a coupling circuit. The first precharge circuit precharges a first node using a first supply voltage and the second precharge circuit precharges a second node using a second supply voltage. The first capacitive element boosts a voltage level of the first node in response to a first pulse signal and the second capacitive element boosts a voltage level of the second node in response to a second pulse signal. The coupling circuit electrically couples the first node to the second node in response to a boosting enable signal and a self-refresh control signal.

Abstract: Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the present invention to sense the signal delay and utilize adjustable input or output delays to correct the signal timing relationships such that correctly timed communication signals are received by the internal circuitry of the device. In one embodiment of the present invention, a register is utilized to adjust the timing delay of individual input and/or output signals for the device. This increases the robustness of the device and its resistance to communication or data corruption, allowing larger ranges of environmental conditions and input capacitances of systems or communication busses to be tolerated.

Abstract: A method for improving the reliability of a memory having a used memory region and an unused memory region, wherein defect memory elements in the used memory region can be substituted by functional memory elements in the unused memory region, having the steps of providing the used memory region with a first stress sequence; and providing the unused memory region with a second stress sequence.

Abstract: A repair circuit and a method of repairing defects in a semiconductor memory device are disclosed. The repair circuit of a semiconductor memory device includes an address generating unit, an address electrical fuse (e-fuse) box unit, a row/column selecting e-fuse unit, a row repair control unit, and a column repair control unit. The address generating unit generates a row address or a column address in response to a control signal, the address e-fuse box unit stores a defective address after packaging, and the row/column selecting e-fuse unit generates a select signal for determining whether the defective address corresponds to a row defect or a column defect. The row repair control unit compares the defective address after packaging with the row address in response to a first state of the select signal, and the column repair control unit compares the defective address after packaging with the column address in response to a second state of the select signal.

Abstract: A semiconductor device is provided for outputting data read from a read only storage device. The semiconductor device includes a read only storage device including memory cells, an address signal line for transmitting an address signal to each read only storage device, and a switching device to which the address signal is inputted. The address signal indicates an address of memory cells storing data to be read. The switching device includes an address storage circuit, a bit storage circuit and a switching storage circuit. The address storage circuit stores address information of a defective memory cell of the read only storage devices and detects whether or not memory cells storing data selected by an address signal includes a defective memory cell. The bit storage circuit stores bit information indicating which bit of data stored in memory cells including a defective memory cell is defective, and outputs a controlling signal.

Abstract: A semiconductor memory device includes an array having memory cells arranged in rows and columns; a clock-to-address converter for counting an external clock signal to generate an address for accessing the array based on the counted value, during a test operation mode; and a redundancy circuit for storing the address generated by the clock-to-address converter.

Abstract: A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.

Abstract: An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, a multiplexer, and a sense amplifier. The first pre-charge circuit pre-charges the voltage of a target readout bit line to the logic high level according to a pre-charge signal. The multiplexer selects the target readout bit line from multiple readout bit lines according to a selecting signal. The sense amplifier detects the voltage of the target readout bit line after the target memory cell is selected to be readout.

Abstract: A ferroelectric memory device includes: a memory cell having a transistor and a ferroelectric capacitor connected in series between a bit line and a plate line, and a connecting section below the ferroelectric capacitor; a dummy cell having a transistor, a ferroelectric capacitor and a connecting section, wherein the dummy cell has an electrically disconnected section among the bit line, the transistor, the ferroelectric capacitor, the connecting section and the plate line.

Abstract: An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.

Abstract: The disclosure concerns a semiconductor memory device includes a memory cell array including memory cells; word lines; bit lines; a counter cell array including counter cells provided corresponding to the word lines and storing the number of times of activating the word lines; an adder incrementing the number of times of activating the word lines which is read out from the counter cell array, when data is read or written in the memory cell; a counter buffer circuit temporarily storing the number of times of activating the word lines, and writing back the incremented number of times of activating the word lines into the counter cell array; and a sense amplifier executing a refresh operation during a data read cycle or a data write cycle, when the number of times of activating one of the word lines has reached a predetermined value.

Abstract: I claim a device and method for reducing current consumption. The device including a memory cell array having a first region to store normal data and a second region to store both normal data and parity data associated with error correction functionality, and a refresh control unit to perform refresh operations on the memory cell array, the refresh control unit adapted to adjust a cycle associated with the performance of the refresh operations responsive to the storage of normal data in the second region.

Abstract: A semiconductor memory apparatus which can restrict a refresh operation for a period when an internal clock is synchronized with an external clock. The semiconductor memory apparatus includes a refresh control unit that disables a refresh command signal which is applied during a period when an enable signal is enabled but a lock-completion signal is not enabled in response to the enable signal outputted from a mode register, the lock-completion signal outputted from a clock synchronizing unit, and the refresh command signal outputted from a command decoder. The clock synchronizing unit can stably complete a locking operation within a predetermined time regardless of power-supply noise and so on.

Abstract: An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

Abstract: Memory cells comprising an SRAM and an OTP memory unit are disclosed that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. Disclosed concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of disclosed memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

Abstract: A programmable resistor is an e-fuse connecting to a source/drain of a MOS transistor. According to the method, a voltage is provided to the gate of the MOS transistor to partially blow the programmable resistor. Following that, a resistance comparator is used to compare the resistance of the programmable resistor to a predetermined resistance. If the resistance of the programmable resistor conforms to the predetermined resistance, then the programmable resistor is set. If it does not conform to the predetermined resistance, then it is determined whether partially blowing it again would make it exceed the predetermined resistance. If it will exceed the predetermined resistance, then it is not blown again. If it will not exceed the predetermined resistance, then the resistor is partially blown again so as to approach the predetermined resistance.

Abstract: The present invention is related to a semiconductor memory device improving refresh performance by reliably generating an internal voltage. The internal voltage generator for use in the semiconductor memory device includes a cell plate voltage generator, a driving voltage generator, and a bit line precharge voltage generator. The bit line precharge voltage generator includes a half driving voltage generator for receiving the driving voltage to thereby generate the bit line precharge voltage, a second reference voltage generator for generating the second reference voltage, and a bit line precharge voltage releasing device for discharging a surplus voltage.

Abstract: A semiconductor storage device has a first transistor of first conductive type which control data writing, a second transistor of second conductive type which controls data read-out, a third transistor which amplifies a current corresponding to data to be read out, a first semiconductor layer which is disposed in a predetermined direction, in which a gate of the first transistor is formed, a second semiconductor layer which is disposed separately from the first semiconductor layer in the predetermined direction, in which source and drain of the second transistor and source and drain of the third transistor are formed, a write transistor forming region which is disposed in a direction intersecting the first and second semiconductor layers, in which source and drain of the first transistor, a gate of the third transistor and an electric charge storing region storing electric charge in accordance with data to be written are formed, and a read-out transistor gate region which is disposed in a direction intersecti

Abstract: A method of inputting data to an integrated circuit is disclosed. A plurality of data signals are serially received from a source external to the integrated circuit. A strobe signal is derived from the plurality of data signals. The deriving is done by circuitry within the integrated circuit. The data signals can be latched at an input of the integrated circuit using the strobe signal that was derived within the integrated circuit.

Abstract: Disclosed is a data interface device for accessing a memory that operates in synchronization with a clock. A board clock and selective data capturing are used to improve an operating rate of a memory interface and to match a point of time that data outputted from the memory is inputted to a memory controller with a internal clock produced by the memory controller, or to match a point of time that data is outputted from the memory controller with the board clock. The board clock is used to synchronize a point of time that the memory inputs or outputs the data. The internal clock is passed through a sequential path of an output pad of the memory controller, the memory, and an input pad of the memory controller and then re-inputted into the memory controller thereby the feedback clock is generated. The selective data capturing uses a register part for storing data inputted into the memory controller.

Abstract: An automatic ATD control circuit operates with a first delay circuit accepting a system clock pulse as an input and producing a delayed version of the system clock pulse as an output. The delay to the system clock is performed to allow a frequency comparison in a later part of the circuit. An edge detection circuit operates when the delayed system clock is received and senses an edge of the delayed system clock pulse. A pulse output from the edge detection circuit feeds into a second delay circuit; the second delay circuit produces an output pulse where a period of the pulse is determined by delay characteristics of the sense amplifier and is thus independent of system clock frequency. The pulse is compared to the system clock frequency. If the system clock frequency is above a determined frequency, the automatic ATD control circuit is disabled.

Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

Abstract: A hand-held electric blender or mixer has an electric motor that is accommodated in a housing and that serves for selectively driving different attachments, such as a whisk or kneading hook or an immersion blender. The hand-held blender or mixer has an actuating element that opens and closes a switch for switching the electric motor on and off. The switch can be operated in a temporary mode or in a continuous mode, depending on the respective attachment coupled to the appliance. An interlocking means is provided for the actuating element and is either engaged with a counterpart to the interlocking means or not, depending on the type of attachment coupled to the appliance.

Abstract: A blender, for producing ice-cream and similar, has a box-shaped outer casing; a substantially cylindrical tubular bowl having a horizontal axis and extending from the surface of, and inwards of, the box-shaped casing; and a hatch fitted movably to the box-shaped casing so as to be positioned closing the inlet of the bowl. The hatch is defined by a substantially porthole-like cover designed to close the inlet of the bowl in fluidtight manner, and hinged to the box-shaped casing so as to be positioned closing the inlet of the bowl; by a hopper projecting from the body of the cover and communicating with a central through opening formed in the cover; and by a safety grille fixed removably to the body of the cover and designed to partly occupy the inlet of the hopper. The cover has a number of parallel, aligned, projecting pins projecting from the body of the cover.

Abstract: The invention relates to a household appliance with an electric control system (20), which is connected to an accessory part (12) for the household appliance in a signal-transmitting fashion, wherein the accessory part (12) can be moved back and forth between an active position and a resting position on the household appliance and, in the switched-on state of the household appliance, exchanges signals for controlling the household appliance with the electric control system (20), at least in the active position.

Abstract: the present invention provides an agitation device, comprising a motor for supplying rotational power, an outer shaft operatively connected to the motor, an extendible inner shaft positioned within the outer shaft and operatively connected thereto, an agitator positioned on the extendible inner shaft, and a floatation device positioned on the extendible inner shaft distal to the agitator from the motor for providing a buoyant force to the extendible inner shaft and the agitator for immersing the agitator at a predetermined level in a liquid. The present invention also provides a device for agitating and heating a liquid.

Abstract: A method of mixing chemical into a process stream of thin stock pipe in a papermaking process is disclosed and claimed. Chemical is added to a portion of a process stream drawn from the thin stock pipe. This mixture is then fed to the thin stock pipe to mix with said process stream.

Abstract: A kitchen appliance 12, especially a blender, has a base unit 12 having an electric motor 20 for driving the appliance. The motor 20 has a high suction/high volume fan 50 attached to a lower end of the motor shaft 36 and a wind guide 52 disposed between the fan 50 and the stator core 46 so that the fan 50 draws air predominantly through the stator to cool the motor to avoid thermal overload.

Abstract: A riddling machine for intensification of depositing lees in wine is provided. One embodiment comprises a first and a second row of struts respectively supporting pivotable gearboxes and supporting boxes, between which inclined shafts are disposed, and rotatable by a revolving motor through a common shaft, extending through the gearboxes, and by gears contained in the gearboxes. The inclined shafts' tilt is variable by an angular motor driving an angle-transmitting disk and the common shaft, further turning the gearboxes fixedly securing lateral bearings that support the inclined shafts from first ends. Second ends of the inclined shafts are supported by lateral bearings fixedly mounted in the supporting boxes, which are optionally attached to the second row struts by flexible suspension members. Each pair of the inclined shafts supports and revolves at least one bottle of wine. Most embodiments include control means to actuate said motors. Some embodiments comprise vibrating means.

Abstract: A fuel processing device has a magnetic coupling that transfers rotational energy from a motor to a fuel homogenizer. The magnetic coupling has magnetic members that may be isolated from contact with fuel.

Abstract: Methods and apparatus determine if an intruder passes into a security zone that is associated with a waterfront asset. An embodiment of the invention provides a harbor fence system that is designed to be deployed in water around ships or other waterfront assets to serve as a line-of-demarcation in order to provide protection. The harbor fence system comprises a series of spars that protrude above the water surface and that are connected with an electrical computer with a telemetry subsystem. Each spar contains electronic sensors, e.g. water immersion sensors and accelerometers, and circuitry to detect an intrusion and to communicate the location of the intrusion to a computer control station. The embodiment also facilitates deploying and retrieving the harbor fence system. Additionally, the embodiment may also determine whether an underwater intruder is passing under a protective boundary, in which the harbor fence system interfaces to an underwater sonar sensor subsystem.

Abstract: The invention is a system for acquiring and mapping the location of a human target within a targeted zone defined by boundaries. The system includes a remote sound detection component, which may be a laser vibrometer, capable of placement at a remote safe distance without physical attachment at the targeted zone which detects sound from within the targeted zone, thereby generating a sound signal accurately representing characteristics of the detected sound. Further, a sound processing computer receives and analyzes the sound signal to determine the location of the sound relative to the targeted zone and generates a location signal representing the location of the sound. A target display is provided for receiving the location signal and outputting an accurate visual representation at the location of the target relative to the boundaries of the targeted zone.

Abstract: Provided are a system and method for position awareness that can be used indoors in a large-scale environment and can minimize generation of radio frequency (RF) and ultrasonic waves in a wireless sensor network including low-priced sensor nodes capable of precise position measurement, thus improving energy efficiency by reducing unnecessary power consumption. The method includes the steps of: (a) calculating initial position coordinates using beacon information received from adjacent beacons through a broadcast beacon solicitation signal, sending a synchronization signal to the beacons, and synchronizing the beacons; (b) receiving ultrasonic waves generated from the adjacent beacons activated by a broadcast start message, and calculating position coordinates; and (c) when the calculated position coordinates correspond to a predetermined hand-off threshold position, transmitting a hand-off process message to a newly activated beacon, and executing a hand-off process routine.

Abstract: A pressure control apparatus according to the present invention is comprised of a magnetostrictive element section disposed between respective one ends of rotating rods which have the one ends thereof arranged on the same axis in a state connected to each other such that they are unrotatable relative to each other but at the same time are movable toward and away from each other, the rotating rods being rotatable about the axis in unison with each other, an urging means for urging the rotating rods to cause them to be closer to each other to thereby bring the respective one ends of the rotating rods into intimate contact with ends of the magnetostrictive element section, respectively, a magnetic field-applying means for generating a magnetic field for use in adjusting the length of the magnetostrictive element section to apply the magnetic field to the magnetostrictive element section, a pressure-detecting means for detecting pressure generated in the rotating rods in the direction of the axis, and a control s

Abstract: This invention relates in general to vibroseis and, more specifically, but not by way of limitation, to the enhancement and/or signal strength optimization of low frequency content of seismic signals for use in surveying boreholes and/or subsurface earth formations. In embodiments of the present invention, physical properties of a seismic vibrator may be analyzed and used to provide for determination of a driving force necessary to drive a reaction mass to produce a sweep signal with enhanced low frequency content for injection into the ground for vibroseis. In certain aspects, the physical properties may be considered independent of any geophysical properties related to operation of the seismic vibrator.

Abstract: [Object] To provide a timepiece spring whereby it is possible to ensure high precision and stable operation of precision mechanisms such as timepieces, and to provide a timepiece spring, a mainspring, a hairspring, and a timepiece wherein long-term operation can be ensured when the spring is used as a power source. [Means] A mainspring used as a source to power a drive source is formed from a special titanium alloy and has an S-shape when freely spread out, wherein the inflection point at which the curving direction of the freely spread-out shape changes is formed farther inward than the midpoint of an inner end at the end of the winding side and an outer end at the end opposite the inner end. The titanium alloy constituting the present invention has high tensile stress and a low average Young's modulus, making it possible to increase the mechanical energy accumulated in the mainspring 31.

Abstract: An alarm system is formed of a network of alarm units that interact with each other to form a neighborhood watch type of alarm network. Each alarm unit transmits its own alarm condition and separately transmits its own user data to other alarm units in the network and in turn receives data from other alarm units in the network representative of their user data and alarm condition. Preferably, the data is transmitted through modulated radio frequency signals. The units in the network rebroadcast their data to maintain the database in each unit up to date. Units may be automatically added and removed without assistance from other users.

Abstract: An audio player apparatus (1) and method (2). The audio player apparatus comprises input means (10), such as buttons (11, 12, 13, 14) or soft-buttons on a touch screen, for inputting the presence of at least one user at a location of said audio player apparatus. The player apparatus (1) further has input means (20) for preferred audio-preferences. Thus audio being reproduced by said audio player apparatus (1) is adapted to the current audio taste and/or mood of users present at the location of the audio player apparatus (1).

Abstract: A data read/write device according to an example of the present invention includes a recording layer, and means for applying a voltage to the recording layer, generating a resistance change in the recording layer, and recording data. The recording layer is composed of a composite compound having at least two types of cation elements, at least one type of the cation element is a transition element having a “d” orbit in which electrons have been incompletely filled, and the shortest distance between the adjacent cation elements is 0.32 nm or less.

Abstract: An optical disc (3) for storing data is provided with a label material layer (8) on a laser entry side of the disc (3). The label material layer (8) does not impede reading data from or writing data onto the disc (3). Reflection or absorption of light in the visual spectrum by the label material in the label material layer (8) is affectable by illuminating the label material according to a label pattern. Changing the reflection or absorption results in a local change of color. The contrast that is herewith applied to the label material layer (8) can be used for creating visual information, such as text or images for forming a label. Furthermore a device (52) is provided for applying a label to the laser entry side of an optical disc (3). The device (52) comprises means for producing a laser beam (21) for illuminating the label material layer (8) according to a label pattern.

Abstract: A data search system for searching a data sync pattern stored in an optical disc by using a physical address is disclosed. The data search system comprises a physical address decoder, a data start indicator and a data sync pattern search circuit. The physical address decoder decodes a physical address signal read from the optical disc to obtain the physical address of a current position. The data start indicator generates a start search signal when the pickup head indicates a predetermined physical address to decide a start position. The data sync pattern search circuit searches the data sync pattern of the data from the start position to determine a cluster area of the data following the data sync pattern. The data search system further comprises a window generator, generating a window interval starting from the start position to search the data sync pattern therein.

Abstract: A removable medium recording/reproduction device capable of preventing expelling of a removable medium (101) by avoiding cancellation of an expelling prohibiting state even during power-down of the device.

Abstract: Application program interfaces for controlling an external media changer from a computer are provided. The application program interfaces allow for loading and identification of discs in a media changer. The application program interfaces can further allow for control of media changer functions such as locking of media changer elements and playback of disc content for discs in the media changer.