Abstract: An LED (light emitting diode) illumination device that can generate a non-circular light output illumination intensity pattern. The illumination source including a reflector with a conic or conic-like shape. Further, an LED is positioned at approximately 90° with respect to a central axis of the reflector.

Abstract: A scuff plate of the invention is a scuff plate which has a luminous unit of which a side surface of side surfaces forms a luminous surface, a light source unit which emits light to the luminous unit, and a light guiding unit which is disposed in such a manner that a side surface thereof faces the luminous surface, wherein the light guiding unit has a luminous surface portion which expands in an intersecting direction relative to a front surface thereof. The scuff plate of the invention provides a scuff plate which has superior design properties without increasing the thickness of the whole thereof.

Abstract: A light fixture or troffer for directing light emitted from a light source toward an area to be illuminated, including a reflector assembly within which the light source is positioned and a lens assembly detachably secured to a portion of the reflector assembly such that a lens of the lens assembly overlies the light source and such that substantially all of the light emitted from the light source passes through the lens assembly. The reflector assembly including at least one longitudinally extending hollow that extends inwardly to a central portion between respective first and second hollow edges. Each hollow has a plurality of longitudinally extending male ridges.

Abstract: In accordance with one embodiment, the present technique relates to a system including a truss fabrication table, a plurality of lights disposed at coordinates on the truss fabrication table, and a light alignable puck disposed on the truss fabrication table. The light alignable puck is configured to align with an illuminated one of the plurality of lights at selected coordinates.

Abstract: An overhead storage bin comprises a storage bin bezel, a door movable in relation to the storage bin bezel between a closed position and an opened position, a storage compartment accessible by a vehicle passenger when the door is in the opened position, and a lamp carried by the storage bin bezel, the lamp being focused to the storage compartment when the door is in the open position.

Abstract: A structure for mounting a high-mounted stop lamp. An upper housing and a lower housing are not provided. A stop lamp having a reflector and a lens is placed in a space defined by a cover part of a tailgate trim which is formed to have a configuration for receiving the stop lamp therein. A pair of mounting sections protrudes from left and right portions of a rear wall of the reflector. By the medium of the pair of mounting sections, the reflector is locked by bolts to a tailgate inner panel which is positioned above the reflector and is coupled by clips to the cover part of the tailgate trim which is positioned below the reflector.

Abstract: A vehicle interior light assembly having a conventional interior light such as a dome, courtesy or map light, as well as a detachable and rechargeable flashlight all in an integrated assembly. The vehicle interior light assembly preferably includes a plastic housing unit with first and second elongated cavities, a stationary illumination device located in the first cavity, a removable illumination device or flashlight detachably installed in the second cavity, and electrical connections for connecting the assembly to a vehicle electrical system. The stationary illumination device operates as a standard vehicle interior light, while the flashlight can be operated according to one of at least two separate lighting modes, where one of the lighting modes uses less energy than the other.

Abstract: A vehicle lighting device with a lamp compartment having a light source unit disposed therein. The light source unit includes a light emitting device as a light source and a projection lens as a light distribution control member for distributing light. A face bearing portion at a distal end of a lens mounting portion of the light emitting device corresponds to a rear surface of a collar portion disposed along an outer circumference of the projection lens. Complimentary extending projections and stepped portions on the collar portion and lens mounting portion are ultrasonically welded together, and burrs formed during the welding process are prevented from protruding toward the optical axis by an erect wall of the stepped portion.

Abstract: Systems for displaying images are provided. An embodiment of a system comprises a liquid crystal display module, and the liquid crystal display module comprises a backlight assembly. The backlight module primarily includes a circuit board and at least an LED disposed on a first planar side of the circuit board. The circuit board comprises at least a hole and a heat conductor extending through the hole. Heat from the LED on the first planar side is dissipated to a second planar side of the circuit board by the heat conductor through the hole.

Abstract: The present invention provides a liquid crystal display device having a backlight device which can fix an LED light source at an optimum position with respect to a light guide plate and also can effectively radiate heat.

Abstract: A device and method for optimizing lighting for a display (108) in a multi-display electronic device (100), is disclosed. The method includes emitting light waves (302) from at least one light source (244), to a back surface (122, 132) of each display in a plurality of displays (108, 110), thereby back-lighting the plurality of displays (108, 110). At least one display of the plurality of displays is selectively back-lighted.

Abstract: Light emitting panel assemblies include a light guide having a pattern of individual deformities of well defined shape that are projections or depressions on or in at least one side of the light guide. At least some of the deformities are quite small in relation to the width and length of the light guide and have two or more surfaces that come together to form ridges. At least some of the ridges are nonlinear over a majority of their length and have opposite end points that intersect the light guide or other deformities where the ridges end.

Abstract: A lighting unit includes a planar lighting component that emits illuminating light; a first light deflector having a prismatic face on one surface, the first light deflector being disposed on the planar lighting component; a second light deflector having a prismatic face on one surface, the second light deflector being disposed on the first light deflector, wherein the one surface of the first light deflector is opposite the one surface of the second light deflector, and the direction of tilt of the prismatic face of the first light deflector is perpendicular to the direction of tilt of the prismatic face of the second light deflector.

Abstract: This invention relates to a light redirecting article that redirects light toward a target angle, the light redirecting article having an input surface for accepting incident illumination over a first range of incident angles when in a first position and over a second range of incident angles when in a second position: the output surface having a number of light redirecting structures, each having a first exit surface sloping away from normal in one direction as defined by a first base angle ?1, wherein the first exit surface redirects illumination with the light redirecting article in the first position, and a second exit surface sloping away from normal, in the opposite direction relative to the first exit surface, wherein the second exit surface redirects illumination with the light redirecting article in the second position and wherein first and second base angles ?1 and ?2 are unequal.

Abstract: A backlight module is disclosed for reducing the occurrence of corner dark space. In the backlight module, two tightly adjacent light-emitting diodes (LEDs) are disposed near a light-guide plate, and each of the LEDs is tilted outwards with a predetermined angle, wherein an outer angle extending from two respective light-emitting surfaces of the LEDs is about between 90 degrees and 180 degrees.

Abstract: A back light module having a light-guiding plate and a linear light source is provided. The light-guiding plate includes a light-guiding body with a light incident surface formed thereon and an optical-path-adjusting groove disposed on the light incident surface of the light-guiding body. The linear light source is disposed beside the light incident surface. The linear light source is suitable for providing light beams to the light incident surface. Furthermore, the optical path of the light beam is adjusted by the optical-path-adjusting groove before the light entering through the light incident surface into the light-guiding body. As a result, the back light module provides illumination with a higher degree of uniformity.

Abstract: An exemplary backlight module (2) includes a metal frame (27), and a light source (21). The metal frame includes inner side and a containing space. The light source is received in the containing space. The inner side includes microstructures (271) configured to optimize absorption of heat thereat.

Abstract: Multiphase voltage sources are used in driving an AC_LED; different light timing is achieved by changing the relative phase or frequency of the voltage sources. Different light color mixing is also achieved when more than one AC_LED with different colors are combined to use.

Abstract: A control circuit for detecting the reflected voltage of a transformer is provided. A detection circuit is developed for sampling the reflected voltage. Because the pulse width of the reflected voltage is narrower at light load, a bias circuit is utilized for producing a bias signal to help the reflected voltage detection. Furthermore, a blanking circuit ensures a minimum pulse width of the reflected voltage.

Abstract: A two-stage converter including a buck converter and a DC-DC converter that receives power from the buck converter. The DC-DC converter generates an output voltage of the two-stage converter. A buck control circuit generates a control signal for the buck converter. The control signal is based on a first signal representing the output voltage, a second signal representing load applied to the buck converter, and a compensation signal. A characteristic of the compensation signal varies based on the output voltage.

Abstract: A method and apparatus for circuit conditioning, such as for providing power factor correction, is provided, using existing or minimal additional circuitry, at minimal or no additional cost to the manufacture of the circuit. The circuit conditioning is implemented by controlling an output side of the circuit based on a value sensed on the output side of the circuit and a relationship between the output side and an input side of the circuit.

Abstract: A primary side controlled power converter having a voltage sensing means coupled to a transformer of the power converter and configured to provide a voltage feedback waveform representative of an output of the transformer is provided. A primary switching circuit operates to control energy storage of a primary side of the transformer. The primary switching circuit is operable during an on time and inoperable during an off time. The on and off time is switched at a system frequency. A feedback amplifier generates an error signal indicative of a difference between the voltage feedback waveform and a reference voltage. A sample and hold circuit samples the error signal at a periodic frequency during the off time. An error signal amplifier is configured to provide the sampled value to the primary switching circuit wherein the primary switching circuit controls the transformer and thereby regulates an output of the power converter.

Abstract: A power conversion apparatus is formed by connecting unit communication-assisting means in series between an alternating-current terminal incorporated in a conventional current-type power conversion apparatus, and an alternating-current load. The communication-assisting means includes reverse-blocking-type self-commutated devices and a capacitor. By controlling the switching of the reverse-blocking-type self-commutated devices, a voltage is generated at the capacitor and additionally used for a power supply commutation operation or load commutation operation. By virtue of this structure, the power conversion apparatus can easily provide a large capacity (high voltage, large current), and can be improved in power factor. Further, the structure enables the number of required fundamental elements to be reduced, and hence enables the power conversion apparatus to be produced easily at low cost.

Abstract: A DC-DC converter for overvoltage protection is provided with a primary control circuit 12 which comprises an impedance controller 31 and a protective circuit 41 for ceasing operation of primary control circuit 12 when power source voltage VCC on primary control circuit 12 exceeds a predetermined voltage level. Impedance controller 31 comprises a potential detector 32 for picking out power source voltage VCC to primary control circuit 12 to produce a detection signal; and an impedance adjuster 33 for adjusting power input impedance Z in primary control circuit 12 in response to the detection signal from potential detector 32 to repress rapid rise in power source voltage on primary control circuit 12.

Abstract: In this power converter, a first capacitor for stepping down of voltage, a first diode for half-wave rectification, and a second capacitor for smoothing are interposed between first and second input connections for input of AC voltage; and a second diode for discharge of the first capacitor is interposed between the second input connection and an input end of the first diode. AC voltage supplied from an AC power supply is divided (stepped down) by the first and second capacitors, rectified to DC voltage by the first diode, smoothed by the second capacitor, and supplied, as an output voltage defined by Zener diodes, to the load side through the first and second output connections.

Abstract: A power supply system for providing power to a powered device over a communication link includes a power supply device capable of supporting an AC disconnect-detect function. The power supply device has a controller, an output port coupled to the communication link, and a bipolar junction transistor (BJT) controlled by the controller to provide power to the output port. The BJT may be turned off to present a high impedance required to support the AC disconnect-detection function.

Abstract: A switching power supply unit is provided, in which a DC input voltage can be detected even if switching operation of the power supply unit is stopped. A switching power supply unit includes: a power supply main section switching a DC input voltage inputted from a first power supply to convert the DC input voltage into an AC voltage, and outputting a DC output voltage into a second power supply, the DC output voltage being obtained by transforming and rectifying the AC voltage; and a voltage detection section having a voltage detection transformer, one or more switching elements, and detection signal lines. The voltage detection transformer includes a first transformer coil as a primary winding being intermittently applied with the DC input voltage in response to on/off of the switching element, and a second transformer coil as a secondary winding being connected to the detection signal lines.

Abstract: An up-converter (100) comprises: an inductor (5) and a diode (6) connected in series with an output (3); a capacitor (8) connected in parallel to said output; a controllable switch (7) having one switch terminal coupled to a node between the inductor and the diode. A control method comprises the steps of feeding the inductor with a rectified AC voltage (Vi); and generating a switch control signal (SC) having a pulse width (TH), for switching the switch open and closed; wherein the switch control signal is generated on the basis of the output voltage (Vo) at said output (3). According to the invention, the up-converter comprises a digital processor (110) which samples the output voltage (Vo), and digitally processes the sampled output voltage (Vo) to calculate the pulse width (TH) of the switch control signal (SC) such that the output voltage (Vo) remains substantially constant.

Abstract: This invention is generally concerned with power supply circuits, and more particularly, with circuits to supply power to a mains supply, such as domestic grid mains, from a photovoltaic device. A photovoltaic power conditioning circuit for providing power from a photovoltaic device to an alternating current mains power supply line, the circuit comprising: a DC input to receive DC power from said photovoltaic device; an AC output configured for direct connection to said AC mains power supply line; a DC-to-AC converter coupled to said DC input and to said AC output to convert DC power from said photovoltaic device to AC power for output onto said power supply line; and an electronic controller directly coupled to said power supply line to measure a voltage of said power supply line and a current in said supply line and to control said DC-to-AC converter responsive to said measuring.

Abstract: Methods and apparatus are provided for modifying a pulse width modulation signal controlling a voltage source inverter. The method comprises the steps of determining a duty cycle of the signal, clipping the duty cycle when a modulation index is greater than a minimum modulation index and less than a maximum modulation index, clipping the duty cycle when the modulation index is greater than or equal to the maximum modulation index, and transmitting the duty cycle to the voltage source inverter. The minimum modulation index indicates a distortion range.

Abstract: A content addressable memory is realized, wherein capacitor stores data and diode controls to store data “1” or “0”, which diode has four terminals, first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourth terminal serves as bit line. The plate of capacitor couples to second terminal, but it does not couple to first, third and fourth terminal. With no coupling, the plate can swing ground to high level, which can realize to remove internal negative voltage for memory operation and by turning off word line during standby no holding current is required to sustain data. In this manner, active current is dramatically reduced and standby current is only leakage current. The match line has compare circuits which include series MOS transistors for each memory cell, wherein the storage node is connected to the gate of first MOS transistor, and the comparand data is connected to the gate of second MOS transistor.

Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

Abstract: A memory array can be optimized for SPICE simulation by modeling the memory array as a collection of boundary elements that track the cell states of memory cells connected to a particular array terminal. By maintaining a cell state distribution for each boundary element, the simulation behavior at the array terminal associated with that boundary element can be accurately determined by modeling each unique cell state, multiplying the results by the corresponding quantities from the cell state distribution, and then adding the results to obtain final values for the array terminal. This allows accurate simulation results to be achieved without needing to simulate each cell independently. Furthermore, by removing any references to unoccupied cell states (e.g., by removing such states from the cell state distribution and/or eliminating model equations for such states), the memory and cpu usage requirements during the simulation can be minimized.

Abstract: A semiconductor memory that includes a row decoder part, a first cell array placed on either side of the row decoder part, a second cell array placed on the other side of the row decoder part, and a wiring layer that short-circuits word lines corresponding to a specified row address on the first cell array with word lines corresponding to a specified row address on the second cell array.

Abstract: A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract: A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs reinforcing data that adjusts the threshold level of the cell to the appropriate level for the desired data.

Abstract: Phase change memory including diode access device is realized, wherein includes a chalcogenide storage element and a diode access device instead of MOS device, the diode has four terminals, the first terminal is connected to a word line, the second terminal is connected to one side of the storage element, the third terminal is floating, the fourth terminal is connected to a bit line, and the other side of the storage element is connected to a resistor line which has floating state just before the word line is asserted to establish the current path of the memory cell. Replica delay circuit controls the read path, which minimizes the read current pulse, induces less current disturbance to the stored data, makes the read access time fast and reduces the current consumption. And the word line cuts off the holding current during standby. Additionally, planar and vertical cell structures are devised on the bulk and SOI wafer.

Abstract: A Magnetic Random Access Memory (MRAM) cell and array for storing data. The MRAM array includes a memory cell having a magnetic pinned layer, a magnetic free layer and a non-magnetic spacer or barrier layer sandwiched between the pinned and free layer. The pinned layer has magnetization that is pinned, and the free layer has a magnetization that is free to rotate but is stable in directions that are parallel or antiparallel with the magnetization of the pinned layer. The free layer has a magnetic anisotropy the maintains the stability of the free layer magnetization. The free layer anisotropy is induced by a surface roughness either in the surface of the free layer itself, or in the surface of the underling barrier/spacer layer. This anisotropic roughness is induced by an angled direct ion milling.

Abstract: A ferroelectric memory device includes memory cells using ferroelectric capacitors provided at intersections of local bit lines associated with a main bit line and word lines. The ferroelectric memory device includes: first and second local bit lines associated with a first main bit line; first and second connection transistors for connecting the first and second local bit lines to the first main bit line; first and second grounding transistors for grounding the first and second local bit lines; a first selection line that is commonly connected to gates of the first grounding transistor and the second connection transistor; and a second selection line that is commonly connected to gates of the first connection transistor and the second grounding transistor.

Abstract: A test mode control device using a nonvolatile ferroelectric memory enables a precise test of characteristics of a memory cell array by changing a reference voltage and timing regulated for a memory cell test in a software system without extra processes. In an embodiment, test modes and arrangement of data pins are programmed using a nonvolatile ferroelectric memory, and addresses, control signals and arrangement of data pins are regulated in a software system depending on a programmed code. As a result, characteristics of a cell array can be precisely tested without extra processes.

Abstract: A test mode control device using a nonvolatile ferroelectric memory enables a precise test of characteristics of a memory cell array by changing a reference voltage and timing regulated for a memory cell test in a software system without extra processes. In an embodiment, test modes and arrangement of data pins are programmed using a nonvolatile ferroelectric memory, and addresses, control signals and arrangement of data pins are regulated in a software system depending on a programmed code. As a result, characteristics of a cell array can be precisely tested without extra processes.

Abstract: A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking device and a charge storing element. As the switchable current blocking device blocks current flow through the variable resistance memory cell, the charge storing element charges. When the switchable current blocking device is not blocking current, the charge storing element discharges through the variable resistance memory cell, generating a write current sufficient to write high resistance variable resistance memory cells.

Abstract: An integrated circuit -comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not connected to the volatile memory elements and comprising first, second, and possibly third separate power supplies, the first power supply being connected to the volatile memory elements, the second power supply being connected to the interface circuits with the memory elements, and the third power supply being connected to other logic circuits.

Abstract: Diode-based capacitor memory uses relatively small capacitor, and uses a diode as an access device instead of MOS transistor, wherein the diode has four terminals, the first terminal is connected to a word line, the second terminal is connected to the first plate of capacitor which serves as a storage node, the third terminal is floating, the fourth terminal is connected to a bit line, wherein the capacitor is formed between the first plate and the second plate, and a plate line is connected to the second plate, during write the storage node is coupled or not, depending on the state of the diode by changing the plate line, during read the diode serves as a sense amplifier as well to detect the storage node voltage whether it is forward bias or not, in this manner the capacitor does not drive heavily loaded bit line directly, instead, it drives lightly loaded second terminal, and then the diode sends binary results to a data latch including a current mirror which repeats the amount of current that the memory c

Abstract: Floating plate memory includes a diode as an access device, wherein the diode has four terminals, the first terminal serves as a word line, the second terminal serves as a storage node, the third terminal is floating, and the fourth terminal serves as a bit line; a floating plate capacitor serves as a storage device, wherein the capacitor includes three plates, the first plate is connected to the storage node, the second plate is floating and the third plate is connected to a plate line; when write, the diode determines whether the storage node is coupled or not by raising the plate line; when read, the diode serves as a sense amplifier to detect the storage node voltage whether it is forward bias or not, and the diode sends binary results to a data latch including a current mirror; and the memory is formed on the bulk and SOI wafer.

Abstract: In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate of the capacitor, the third terminal is floating, and the fourth terminal is connected to a bit line, and the capacitor includes two electrodes, wherein one of the capacitor plate serves as a storage node which is connected to the second terminal of the diode, and another plate of the capacitor is connected to a plate line, and the plate line is asserted to programming voltage which is higher than the regular supply voltage of the decoders and data latches, in order to breakdown the insulator of the capacitor when programming, but the plate line is connected to the regular supply voltage when read.

Abstract: A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd? higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

Abstract: A semiconductor storage device such as a memory cell, a latch, etc. provides a memory cell or other such memory device that has a high immunity to soft errors. The device includes an inverter composed of a paired N-type transistors and a paired P-type transistor, and each of transistor is disposed on a separate well. The device also includes four such transistor pairs coupled to each other, and a gate-to-node connection device for connecting to a gate of each P-type transistor and each N-type transistor a connection node for connection of the P-type transistor to the N-type transistor in each pair of transistors in such a direction so as to prevent a potential inversion of a node caused by a soft error from propagating to another node.

Abstract: Each memory cell of an MRAM that uses toggle writing is written by applying to the memory cell a first field, then a combination of the first field and the second field, then the second field. The removal of the second field ultimately completes the writing of the memory cell. The combination of the first field and the second field is known to saturate a portion, the synthetic antiferromagnet (SAF), of the MRAM cell being written. This can result in not knowing which logic state is ultimately written. This is known to be worsened at higher temperatures. To avoid this deleterious saturation, the magnetic field is reduced during the time when both fields are applied. This is achieved by reducing the current that provides these fields from the current that is applied when only one of the fields is applied.