Abstract: A magnetic memory 1 having a wire 5 extended in a direction of arbitrary decision, an electro-resistivity effect element 4 disposed adjacently to the wire 5, and a counter element side yoke 20B disposed adjacently on the side opposite the magneto-resistivity effect element 4 in the wire 5 and having the thickness of the counter element side yoke 20B so set as to be larger than 50 nm and smaller than 150 nm. Owing to conformity with this invention, this magnetic memory is enabled to homogenize the magnetization property during the course of writing operation and perform the writing work with a low electric current.

Abstract: A storage element includes a storage layer for holding information by use of a magnetization state of a magnetic material, with a pinned magnetization layer provided on one side of the storage layer, with an intermediate layer, to form a laminate film, and with the direction of magnetization of the storage layer being changed by passing a current in the lamination direction so as to record information in the storage layer, wherein the radius of curvature, R, at end portions of a major axis of a plan-view pattern of at least the storage layer, in the laminate film constituting the storage element, satisfies the condition, R?100 nm.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells storing data; a write current line arranged near the memory cells or electrically connected to the memory cells; a first constant current generating circuit providing an output current having a temperature dependence; a second constant current generating circuit providing an output current having a temperature dependence different from that of the output current of the first constant current generating circuit; a mixing circuit mixing the output currents of the constant current generating circuits together to provide a composite current at a variable mixing rate; and a write current electrically connected to the write current line and writing data into the memory cell by passing a write circuit through the write current line based on the composite current provided by the mixing circuit.

Abstract: Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

Abstract: A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

Abstract: A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

Abstract: In one aspect, a non-volatile memory includes a phase-change memory cell array which includes a plurality of normal phase-change memory cells and a plurality of pseudo one-time-programmable (OTP) phase-change memory cells, a write driver which writes data into the normal and pseudo OTP phase-change memory cells of the phase-change memory cell array, and an OTP controller which selectively disables the write driver.

Abstract: A phase-change random access memory device may include a phase-change pattern, a first electrode structure connected to the phase-change pattern, and a second electrode structure spaced apart from the first electrode structure and connected to the phase-change pattern, wherein at least one of the first electrode structure and the second electrode structure includes a plurality of resistor patterns connected to the phase-change pattern in parallel.

Abstract: Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

Abstract: Provided is a phase change memory device including: a phase change memory unit comprising a phase change layer pattern; a laser beam focusing unit locally focusing a laser beam on the phase change layer pattern of the phase change memory unit; and a semiconductor laser unit generating and emitting the laser beam towards the laser beam focusing unit. Thus set or reset operations in the phase change memory device uses laser beams locally applied, thereby reducing the consumption power and preventing destruction or change in information stored in neighboring cell during the operations of unit cell.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A low-power reading reference circuit for split-gate flash memory includes at least a pair of first reference cell and a second reference cell, which provides a reading reference current to regular cells of the split-gate flash memory. A first floating gate of the first reference cell and a second floating gate of the second reference cell are connected to an output of a logic circuit. The logic circuit receives at least one external state signal to determine whether the split-gate flash memory is ready to switch to reading mode or not, and then switches the first floating gate and the second floating gate between the state of activated and deactivated, so as to activate the first reference cell or the second reference cell to provide the reference current.

Abstract: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

Abstract: A memory cell transistor array is composed of a plurality of memory cells having three or more threshold voltage distribution states in a single electric charge accumulation portion. A program sequence control circuit associates each piece of data included in a data set composed of a plurality of data values with any threshold voltage distribution of the three or more threshold voltage distributions, to store the data in the memory cell, and when rewriting the data stored in the memory cell, shifting threshold voltage distributions used for data storage in one direction to perform the data rewrite operation.

Abstract: Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.

Abstract: Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics.

Abstract: A flash memory is provided with a protect area PA in which reading of a specific block is prohibited. A RAM to be used as a work area of a program is provided with a protect area PA1 in which reading of a specific block is prohibited. A bus state controller 3 compares a value of a program counter and a value of an address signal to prohibit reading in areas other than the protect area PA in the flash memory and to prohibit reading of data of protect area PA1 in the RAM other than reading from the protect area PA of the flash memory. For instance, when a user reads data of the protect area PA from a user access area to which the user can access, senseless data such as H'FFFF are output from the bus state controller 3 via a data bus.

Abstract: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.

Abstract: A memory cell array has a unit formed from one memory cell and two select transistor sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one gate. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Abstract: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Abstract: A flash memory includes memory cell array having memory cells divided into sectors, a page buffer block having groups of page buffers corresponding to the sectors, and a page buffer controller configured to control the groups of page buffers individually. In some embodiments, multiple groups of page buffers may be activated simultaneously to access multiple sectors, while page buffer groups for unselected sectors are deactivated.

Abstract: A memory circuit and a method is provided for programming a dual-gate memory cell without program disturb in other dual-gate memory cells in the memory circuit coupled by common word lines. In one embodiment, the method uses a self-boosting technique on unselected memory cells having source and drain regions in the shared semiconductor layer between their memory devices and their access devices brought to a predetermined voltage close to the threshold voltage of their access devices, thereby rendering the source and drain regions substantially floating. In some embodiments, the source and drain regions are brought to the predetermined voltage via one or more select gates and intervening access gates. In some embodiments, the select gates are overdriven.

Abstract: A threshold voltage read method of a nonvolatile semiconductor memory device is disclosed. The threshold voltage read method applies a first threshold voltage measuring read voltage to the word line with a selection gate kept in a nonconductive state and then makes the selection gate conductive to read out a threshold voltage of the first data at the time of reading out the threshold voltage of the first data. Then, it applies a second threshold voltage measuring read voltage to the word line with the selection gate kept in the conductive state to read out a threshold voltage of the second data at the time of reading out the threshold voltage of the second data.

Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

Abstract: The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. The devices of the present invention also include a high voltage PMOS placed on top of a deep N-well and NMOS placed above a triple P-well inside the deep N-well in the peripheral area to pass both positive and negative high voltage of around +20V and ?20V to the cell area. In one embodiment, the cell array, source lines and bit lines are all placed on top of the P-substrate without a deep N-well or Triple P-well. In other embodiments, the cell array, source lines and bit lines are placed on top of the deep N-well and triple P-well.

Abstract: A device includes first and second memory cell arrays, first and second decoders, first and second sense amplifiers, and first and second switch circuits. The first switch circuit switches the supply of writing and erasing voltages or a reading voltage to the first memory cell array, and switches the supply of writing and erasing addresses or a reading address to the first decoder, and switches the connection of a data line connected to the first memory cell array to the first sense amplifier. The second switch circuit switches the supply of writing and easing voltages or a reading voltage to one of the second memory cell arrays, and switches the supply of writing and erasing addresses or a reading address to one of the second decoders, and switches the connection of a data line connected to the second memory cell arrays to the second sense amplifier.

Abstract: A nonvolatile semiconductor memory device of the present invention is characterized in that, when data is written to a flag cell area, every other flag cell in the direction of one bit line BL among a plurality of flag cells 15 connected to the bit line BL is written with data and every other flag cell in the direction of one word line WL among a plurality of flag cells 15 connected to the word line WL is written with data. The arrangement as described above prevents a flag cell 15 from being influenced by the capacitive coupling of a neighboring flag cell 15 adjacent to the flag cell 15 in the direction of the word line WL. Thus, data (flag data) memorized by the flag cell 15 can have improved reliability.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A non-volatile memory device includes at least one current source coupled to a bit line, along which at least two memory cells sharing a common source line are connected, for generating a programming current on the bit line when one of the memory cells is selected for programming operation. At least one voltage regulator is coupled to the bit line between the current source and the memory cells for allowing the programming current to flow between the current source and the selected memory cell when a voltage level on the bit line is higher than a predetermined reference voltage, and blocking the programming current flowing between the current source and the selected memory cell when the voltage level on the bit line is lower than the predetermined reference voltage, thereby preventing a punch-through across the unselected memory cell from occurring.

Abstract: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

Abstract: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

Abstract: A method for operating a nonvolatile memory and related circuit are applied to a nonvolatile memory of an RFID tag. The operating method is for repeatedly performing a program procedure on the nonvolatile memory at least twice, and then performing an verification procedure on the nonvolatile memory.

Abstract: Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and consequently, lowering the sensed conduction current of a memory cell. The read process for a selected memory cell takes into account the state of one or more adjacent memory cells. If an adjacent memory cell is in one or more of a predetermined set of programmed states, a compensation current can be provided to increase the apparent conduction current of the selected memory cell. An initialization voltage is provided to the bit line of the programmed adjacent memory cell to induce a compensation current between the bit line of the programmed adjacent memory cell and the bit line of the selected memory cell.

Abstract: Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and consequently, lowering the sensed conduction current of a memory cell. The read process for a selected memory cell takes into account the state of one or more adjacent memory cells. If an adjacent memory cell is in one or more of a predetermined set of programmed states, a compensation current can be provided to increase the apparent conduction current of the selected memory cell. An initialization voltage is provided to the bit line of the programmed adjacent memory cell to induce a compensation current between the bit line of the programmed adjacent memory cell and the bit line of the selected memory cell.

Abstract: A non-volatile memory storage device with functions of boosting supply voltage and signal level can adopt a non-volatile memory having an operating voltage higher than the supply voltage provided by the host device as a storage medium. The non-volatile memory storage device includes a supply voltage booster, a non-volatile memory storage unit and a controller. The supply voltage booster boosts the lower supply voltage provided by the host device up to the higher operating voltage of the non-volatile memory. The controller adjusts the interface signal to a proper interface signal level by cooperating with the supply voltage and the operating voltage so as to avoid the interface from damage owing to an over high signal level or avoid the non-volatile memory unit from not correctly receiving signal due to an over low signal level.

Abstract: A high voltage switching circuit that has a depletion mode NMOS transistor, an enhancement mode PMOS transistor and an, enhancement mode NMOS transistor. A control circuit generates first and second control signals. A first control signal controls the enhancement mode NMOS transistor and a logical combination of both control signals provides a bias to control the PMOS transistor. The bias on the PMOS transistor provides a gate voltage greater than ground potential after the high voltage has been switched to the circuit output.

Abstract: The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.

Abstract: A memory cell array circuit of a non-volatile memory selects the drain electrodes of the memory cells, interconnected to word lines and bit lines, by two drain selectors, adapted for selecting the drain electrodes in two selection routes, so that the memory cell array circuit will select the drain electrodes in four selection routes. In writing in the memory cells, the drain electrodes of the memory cells are selected at a rate of one out of four drain electrodes and the voltage CDV is applied to the so selected drain electrode. This decreases the potential difference between the drain and source electrodes of the non-selected memory cells to prevent the erroneous writing in the non-selected memory cells. A method for writing in the memory is also provided.

Abstract: Nonvolatile evaluation memory cells are programmed to be a plurality of different values in advance, respectively. An internal voltage generating circuit can change the value of an internal voltage according to adjusting signals. To make the internal voltage close to its expected value,- a voltage adjusting circuit outputs adjusting signals in accordance with cell currents that flow through the evaluation memory cells, respectively, in a read operation on the evaluation memory cells. As a result, the interval voltage that is shifted from its expected value due to variations in manufacturing conditions can automatically be set to the expected value by using the adjusting signals. Since an internal circuit operates on a correct internal voltage, operation margins can be increased. The yield of a nonvolatile semiconductor memory can thus be increased.

Abstract: A method of automatically determining a sensing timing in a page buffer of a NAND flash memory device is disclosed, which includes the steps of discharging a first reference bit line, discharging a second reference bit line, determining a first control signal and determining a second control signal. To perform the method, an apparatus of automatically determining a sensing timing in a page buffer of a NAND flash memory device is also disclosed. The apparatus includes a first reference bit line, a first current sink, a first reference page buffer, the second reference bit line, a second current sink and a second reference page buffer. The first reference bit line is coupled to the first current sink and the first reference page buffer at both ends thereof. The second reference bit line is coupled to the second current sink and the second reference page buffer at both ends thereof.

Abstract: A method of erasing data in a nonvolatile semiconductor memory device including applying an erase voltage to a substrate of the semiconductor memory device, applying a ground voltage to wordlines of a selected memory cell string formed in the substrate, and applying a control voltage to at least one of a string selection line and a ground selection line of the selected memory cell string.

Abstract: An erasing method for a non-volatile memory is provided. The method includes the following two major steps. (a) A first voltage is applied to the odd-numbered select gates of each memory row and a second voltage is applied to the even-numbered select gates of each memory row such that the voltage difference between the first voltage and the second voltage is large enough for the electrons injected into the floating gate of the memory cells to be removed via the select gate. (b) A switchover operation is performed so that the first voltage is applied to the even-numbered select gates of each memory row and the second voltage is applied to the odd-numbered select gates of each memory row such that the electrons injected into the floating gates of the memory cells are pulled away via the select gates to turn the memory cells into an erased state.

Abstract: A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A dynamic random access memory (DRAM) comprising memory cells distributed in rows and in columns, each memory cell comprising a MOS transistor with a floating body, the memory comprising circuitry for writing a datum into a determined (i.e. selected) memory cell belonging to a determined (i.e. selected) row and to a determined (i.e. selected) column, wherein the write circuitry comprises circuitry capable of bringing the drains of the memory cells of the determined column to a voltage V1; circuitry capable of bringing the sources of the memory cells of the determined row to a voltage V2; and circuitry capable of bringing the drains of the memory cells of the columns other than the determined column and the sources of the memory cells of the rows other than the determined row to a voltage V3, voltages V1, V2, and V3 being such that |V1?V2|>|V3?V2| and (V1?V2)×(V3?V2)>0.

Abstract: An integrated circuit digital device is coupled to a memory with a single-node data, address and control bus. The memory may be a non-volatile memory and/or volatile memory. The memory may be packaged in a low pin count integrated circuit package. The memory integrated circuit package may have a ground terminal, VSS; a power terminal, VDD or VCC; and a bidirectional serial input-output (I/O) terminal, SCIO. Memory block address set-up may be performed via software instructions through the SCIO terminal. In addition, hardwired memory block address selection terminals A0 and A1 may be used when more then three terminals are available on the memory integrated circuit package. The memory may have active pull-up and pull-down drivers coupled to the single-node data, address and control bus.

Abstract: A memory system with a flexible serial interface and a memory accessing method thereof are provided. The memory system includes at least one of memories and a memory controller. The memory controller flexibly sets up serial link connection with each of the memories through serial ports regardless of a physical location and an order of the serial ports. The memory controller also transmits and receives memory data in a serial mode through the serial link connection.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires a predetermined number of clock cycles. The non-volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data.