Abstract: The process for producing a semiconductor device according to the invention comprises a pre-sticking/fixing step of pre-sticking/fixing a semiconductor element through an adhesive sheet to an object to which the semiconductor element is to be stuck/fixed, and a wire bonding step of performing wire bonding without heating step, wherein the shear adhesive force of the adhesive sheet to the object is 0.2 MPa or more at the time of the pre-sticking/fixing. This makes it possible to a semiconductor device producing process wherein a drop in the yield of semiconductor devices is suppressed and steps therein are made simple; an adhesive sheet used in this process; and a semiconductor device obtained by the process.

Abstract: A cascaded die mounting device and method using spring contacts for die attachment, with or without metallic bonds between the contacts and the dies, is disclosed. One embodiment is for the direct refrigerant cooling of an inverter/converter carrying higher power levels than most of the low power circuits previously taught, and does not require using a heat sink.

Abstract: An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.

Abstract: A CMOS image sensor and a method for fabricating the same is disclosed, to decrease a darkcurrent generated in the boundary between a diffusion area of a photodiode and a device isolation layer, which includes a first conductive type semiconductor substrate having an active area and a device isolation area, the active area including a photodiode and a transistor; a device isolation layer formed in the device isolation area of the semiconductor substrate; a second conductive type diffusion area formed in the photodiode of the semiconductor substrate at a predetermined interval from the device isolation layer; a gate insulating layer and a gate electrode formed in the transistor of the semiconductor substrate; and a first conductive type first diffusion area formed in the semiconductor substrate of the boundary between the second conductive type diffusion area and the device isolation layer.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: A semiconductor device having a display unit, which is small in size, suppresses the defect caused by the mounting of IC chips and the like on the substrate, and operates at a high speed. A semiconductor display unit and other circuit blocks are integrally formed on the substrate having an insulating surface by using a process for fabricating TFTs that realize a high degree of mobility. Concretely, there is employed a process for crystallizing a semiconductor active layer by using a continuously oscillating laser. Further, the process for crystallization relying upon the continuously oscillating laser is selectively effected for only those circuit blocks that must be operated at high speeds, thereby to realize a high production efficiency.

Abstract: A technique to control segregation of impurities when reforming crystallinity and crystallization of a semiconductor film by using a laser beam irradiation is provided. The present invention is to irradiate the substrate with applying ultrasonic vibration while keeping the end portion of the substrate in space. The substrate on which a semiconductor film is formed is kept onto the stage provided with opening pores, and floated by spouting gas from opening pores. Supersonic vibration can be efficiently provided to the substrate by irradiating with a laser beam with ultrasonic vibration while keeping the end portion of the substrate.

Abstract: The average film thickness of an amorphous silicon film formed on a substrate is measured. Then, the amorphous silicon film is irradiated with a laser beam to form a polysilicon film, and the grain size distribution of the polysilicon film is measured. An optimum value of energy density of laser beam irradiation is calculated on the basis of grain size values measured at two points A and B of the polysilicon film. Then, the average film thickness of an amorphous silicon film formed on a subsequent substrate is measured. A value of energy density of laser beam irradiation for the subsequent amorphous silicon film is calculated on the basis of the two average film thicknesses. Accordingly, a uniform polysilicon film of large grain sizes is formed on the whole surface of a large-size substrate to provide polysilicon TFTs in a large area.

Abstract: A method of forming a non-volatile DRAM includes, in part: forming p-well and an n-well between two trench isolation regions formed in a semiconductor substrate, forming a polysilicon control gate of the non-volatile device disposed in the non-volatile DRAM, forming a first oxide spacer above portions of the body region and adjacent said first control gate, forming gate oxide layers of varying thicknesses above the body region, forming the guiding gate of the non-volatile device and the gate of an associated passgate transistor, forming LDD implant regions of the non-volatile device and the associated pass-gate transistor, forming source/drain regions of the non-volatile device and the associated pass-gate transistor, depositing a dielectric layer over the polysilicon guiding gate of the non-volatile device and the polysilicon gate of the associated passgate transistor, forming polysilicon landing pads, and forming polysilicon vertical walls defining capacitor plates of the non-volatile DRAM capacitor.

Abstract: A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited in the deep trench, and etched back to expose parts of the doped silicate film. Then, an etching process is performed to remove the exposed doped silicate film and parts of the pad oxide for forming a recess. The sacrificial layer is removed. A silicon nitride layer is deposited to fill the recess and to cover the doped silicate film. Finally, a thermal oxidation process is performed to form a doped ion region. The silicon nitride layer is removed. The doped silicate film is removed.

Abstract: A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.

Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

Abstract: The present invention relates to a method of making a multibit non-volatile memory and especially to a method of making a flash memory such as a fast-programmable Flash EEPROM (Electrically Erasable Programmable Read-Only Memory) device relying on hot-electron injection for programming which is particularly suited for high density low-voltage low-power applications and employs only two polysilicon layers.

Abstract: There is provided a method of fabricating a semiconductor device comprising the steps of applying resist to a polysilicon film formed across the surface of a substrate and forming a plurality of openings in a resist pattern, for determining a spacing between floating gates adjacent to each other, causing the openings of the resist pattern to undergo uniform contraction by use of, for example, deformation due to thermal flow to thereby form other openings, and etching portions of the polysilicon film, in the openings as contracted to thereby form the floating gate on both sides of the respective openings as contracted. With the method described, it becomes possible to reduce the spacing between the floating gates adjacent to each other above the resolution limit of an exposure system, thereby enlarging a floating gate width.

Abstract: Methods are disclosed for fabricating multi-bit SONOS flash memory cells, comprising forming a first dielectric layer and a charge trapping layer over a substrate of a wafer and selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening, then implanting a dopant ion species into the substrate associated with the bitline opening in a bitline region. A radical oxidation process is then used to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and to fill the bitline opening in the bitline regions of the wafer. Finally, a wordline structure is then formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer.

Abstract: A split gate memory device and fabricating method thereof, wherein gate insulating and polysilicon layers are sequentially formed on a substrate. The polysilicon layer is patterned and a capping insulating layer is formed on portions thereof. A pair of self-aligned control gates having identical bottom widths are formed with a tunnel insulating layer interposed between the control gates and sidewalls of the polysilicon layer pattern and capping insulating layer. The tunnel insulating layer, patterned polysilicon layer and gate insulating layer are selectively etched to expose a portion of the substrate thereby forming a pair of floating gates. Ions are implanted into the exposed substrate and portions of the substrate adjoining the control gates to form a common source region and a drain region, respectively. The capping insulating layer on the floating gate protects an acute section of the tunnel insulating layer from attack during the etching and ion implantation.

Abstract: Consistent with an example embodiment a trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate provided below the trenched gate is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove into the semiconductor body for receiving the gate, and etching a second groove into the top major surface of the semiconductor body, the second groove extending from the first groove and being narrower than the first groove. The invention enables better control of the vertical extent of the gate below the top major surface of the semiconductor body.

Abstract: Disclosed is a method for fabricating a semiconductor device with a plurality of recessed channel regions. This method includes the steps of: forming a plurality of device isolation layers in a substrate; forming a hard mask nitride layer, a hard mask oxide layer and a hard mask polysilicon layer on the device isolation and the substrate, thereby obtaining a hard mask pattern; forming a plurality of trenches in the predetermined regions of the substrate with use of the hard mask pattern to expose a plurality of recessed channel regions; selectively removing the hard mask pattern; and forming a plurality of gate structures in the plurality of trenches.

Abstract: This invention improves the quality of gate oxide dielectric layers using a two-pronged approach, thus permitting the use of much thinner silicon dioxide gate dielectric layers required for lower-voltage, ultra-dense integrated circuits. In order to eliminate defects caused by imperfections in bulk silicon, an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride islands used for masking during the field oxidation process. By growing an epitaxial silicon layer prior to gate dielectric layer formation, defects in the bulk silicon substrate are covered over and, hence, isolated from the oxide growth step. In order to maintain the integrity of the selective epitaxial growth step, the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished.

Abstract: The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep more heavily doped region, disposed laterally within the shallow heavily doped region and vertically within and below the shallow heavily doped region. In an optional feature of the present invention, the method further comprises selectively implanting a second impurity, wherein the doping profile of the deep more heavily doped region is graded.

Abstract: A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.

Abstract: A method for fabricating a transistor of semiconductor is disclosed.

Abstract: Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer. An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Feature sizes are determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated.

Abstract: A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region, and forming a doped region between the heavily doped region and the oppositely doped well. The doped region has a doping concentration profile less than a doping concentration profile of the heavily doped region. The method of forming the integrated circuit also includes forming a driver switch of a driver on the semiconductor substrate.

Abstract: Radiation-emitting semiconductor device and method of manufacturing such a device. The invention relates to a radiation-emitting semiconductor device (10) comprising a silicon-containing semiconductor body (1) and a substrate (2), which semiconductor body (1) comprises a lateral semiconductor diode positioned on an insulating layer (7) which separates the diode from the substrate (2).

Abstract: A semiconductor device according to the present invention includes a cylindrical capacitor. An amorphous silicon layer serving as a lower electrode of the cylindrical capacitor has a two-layer structure including a lower high-concentration impurity sublayer and an upper low-concentration impurity sublayer. The blockage of a cylinder is prevented by etching the upper low-concentration impurity sublayer in a lower region of the cylinder and thereby reducing the crystal grain size of hemispherical silicon grains formed in the lower region.

Abstract: Semiconductor devices with copper interconnections and MIM capacitors and methods of fabricating the same are provided. The device includes a lower electrode composed of a first copper layer. A first insulation layer covers a lower electrode. A window is formed in the first insulation layer to expose a portion of the lower electrode. A capacitor includes a lower barrier electrode, a dielectric layer, and an upper barrier electrode, which are sequentially formed to cover a sidewall and a bottom of the window. An intermediate electrode composed of a second copper layer fills a remaining space of an inside of the capacitor. A second insulation layer is formed on the intermediate electrode. A connection hole is formed in the second insulation layer to expose a portion of the intermediate electrode. A connection contact plug composed of a third copper layer fills the connection hole.

Abstract: A method of forming a structure that includes a removed layer taken from a donor wafer donor wafer that includes a first layer of Si1-xGex and a second layer of Si1-yGey. The method includes implanting atomic species into the donor wafer to form a zone of weakness in the first layer; bonding the donor wafer to a receiver wafer; detaching the second layer and a portion of the first layer from the donor wafer by supplying energy sufficient to cause cleavage and form an intermediate structure thereof conducting a rapid thermal anneal of the intermediate structure at a temperature of about 1000° C. or more for less than 5 minutes; and removing by selective etching any remaining portions of the first layer of the intermediate structure to provide a semiconductor structure that has the second layer on the receiving wafer.

Abstract: A method is presented for cutting an assembly that includes two layers of material having a first surface and a second surface. The method includes providing a weakened interface between the two layers that defines an interface ring about the periphery of the assembly, providing a high-pressure zone at the interface ring, and providing at least one controllable low-pressure zone in the vicinity of at least one of the first surface and the second surface. The technique also includes supplying the high-pressure zone with a controllable high-pressure force, and attacking the interface ring with at least one mechanical force in combination with the high-pressure force to cut the assembly.

Abstract: Methods are provided for producing a transfer layer of a semiconductor material on a final substrate. In some embodiments, the transfer layer is produced on the final substrate by forming a layer of semiconductor material on an initial support, assembling that layer and a final substrate by metal bonding, and mechanically separating the initial support from the layer at a weak interface that initially attached the layer to the initial support. An intermediate substrate can be obtained which can be used to fabricate a variety of components such as light-emitting diodes or laser diodes. These techniques can produce a transfer layer on a final substrate and a recyclable initial support that can be detached from the transfer layer for recycling by a non-destructive mechanical release.

Abstract: Method of making a bumped thinned circuit wafer includes providing a silicon circuit wafer, and providing a conductive layer on it. Then, a first temporary support, such as a handle wafer, may be attached by an acrylic bond. The circuit wafer may then be thinned to a desired thickness, and the thinned circuit attached to a second temporary support, such as a transfer wafer. The handle wafer is removed, the thinned circuit wafer is bumped, and further processing steps may be carried out while the bumped thinned circuit wafer is still attached to the transfer wafer. When the desired processing steps are complete, the transfer wafer is removed, and the thinned circuit wafer with relatively thick solder bumps results.

Abstract: A method of dividing a wafer along predetermined dividing lines, comprising the steps of a deteriorated layer forming step for applying a pulse laser beam capable of passing through the wafer along the dividing lines to form deteriorated layers in the inside of the wafer along the dividing lines; an extensible protective tape affixing step for affixing an extensible protective tape to one side of the wafer before or after the deteriorated layer forming step; and a dividing step for dividing the wafer along the deteriorated layers by expanding the protective tape affixed to the wafer after the deteriorated layer forming step.

Abstract: In a method of crystallizing a semiconductor film by introducing a metallic element that promotes crystallization, a gettering thereafter is effectively performed. A material film having a high tensile stress, typically a silicon nitride film, is formed in contact with the semiconductor film or heated after the formation thereof, thereby the metallic element in a crystalline semiconductor film is gettered to the material film having a high tensile stress. Thus, the metallic Interstitial silicon density element is removed or reduced to thereby form a gettered region.

Abstract: A method for fabricating a semiconductor structure having a high-strained crystalline layer with a low crystal defect density is disclosed. The structure includes a substrate having a first material comprising germanium or a Group(III)-Group(V)-semiconductor or alloy thereof. In addition, a crystalline epitaxial first layer, comprising a graded buffer layer and a substantially relaxed layer, is provided. The buffer layer is sufficiently relaxed to provide relaxation of the substantially relaxed layer deposited thereon. A further layer may be provided on the first layer, and the transfer of at least the further layer is facilitated by providing a weakened zone in the first layer.

Abstract: The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate (310) located on or over an implant platen (305) about an axis in a first direction with respect to an implant source (320) and implanting a portion of an implant dose within the substrate (310) tilted in the first direction. The method further includes tilting the substrate (310) having already been tilted in the first direction about the axis in a second opposite direction, and implanting at least a portion of the implant dose within the substrate (310) tilted in the second opposite direction.

Abstract: A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

Abstract: A method for forming a dual damascene interconnection in a semiconductor device, which is capable of preventing a lower metal film from being corroded. The method includes the steps of forming an etch stop film and an intermetal insulating film sequentially on a lower metal film to be interconnected, forming a via hole for exposing a portion of a surface of the etch stop film through the intermetal insulating film, and forming a trench having a width wider than that of the via hole on the intermetal insulating film. The method also includes the steps of exposing the lower metal film by removing the etch stop film by performing an etching process using an etching equipment of a dual plasma source, performing a nitrogen passivation process for the exposed lower metal film, and forming a barrier metal film and an upper metal film sequentially within the trench and the via hole.

Abstract: A method of bumping a wafer for facilitating bonding of bond wires to elevate the bond location above the passivation layer. The wafer is bumped by disposing the wafer in at least one electroless bath having a nickel-containing solution therein, wherein bumps having a nickel-containing material are formed simultaneously on the exposed bond pads to an elevation sufficient to prevent damage to a passivation layer surrounding the bond pads by contact of a wire bonding capillary. A gold or palladium cap may optionally be formed over the nickel-containing material of the bumps. A method of forming a semiconductor device assembly is also disclosed.

Abstract: A BARC or other sacrificial fill layer etch comprises a selective etch chemistry of Ar/O2/CO. The BARC etch may be used in a via-first dual damascene method. After via (116) pattern and etch, a BARC/sacrificial fill layer (120) is deposited to fill the via (116) and coat the IMD (110). The excess sacrificial fill layer (120) material over the IMD (110) is removed using the Ar/O2/CO etch. A trench resist pattern (125) is formed over the BARC layer (120). During the main trench etch, portions of sacrificial fill layer (120) remain in the via to protect the etch-stop (104) at the bottom of the via (116).

Abstract: An integrated circuit inductance and the fabrication method thereof are disclosed. The manufacture process provided by the present invention fabricates an integrated circuit inductance having a simple production process, low cost, a near equal loop size and good performance, due to making the order of the planarization processes of the inductance loops substantially perpendicular to the wafer and the direction of the current of the inductance substantially in parallel with the wafer, by way of the manufacture process of the plugs and the conductive wires of the integrated-circuit process.

Abstract: Methods for improving memory retention properties of a polymer memory cell are disclosed. The methods include forming a first electrode, depositing a passive layer over the first electrode, forming a semiconducting polymer layer containing at least one semiconducting polymer with at least one charge carrier-binding group over the passive layer, and forming a second electrode. The charge carrier-binding groups can be incorporated into semiconducting polymers either as side groups or into the main chain of semiconducting polymers.

Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.

Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

Abstract: A method of fabricating a semiconductor device, provide a simplification of the fabricating process by removing a step of forming an oxide film, and vapor depositing a nitride film, after forming a gate. The method of fabricating the semiconductor device includes the steps of forming a trench, a gate insulating film, and a poly gate on a substrate; forming a nitride film on the substrate; forming an LDD region by ion implantation using the gate as a mask; forming an oxide film on the substrate; forming a sidewall by etching the oxide film; forming a source/drain by ion implantation using the gate and the sidewall as masks; vapor depositing PMD over the substrate, and then planarizing the substrate; forming a contact hole by etching the PMD; and vapor depositing a barrier metal on the PMD, treating with heat, and filling up the contact hole.

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

Abstract: A process for fabricating a pad frame for an integrated circuit package includes building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material, depositing a metal seed layer on an exposed side of the contact pads and the dielectric material, applying a second metal layer on the metal seed layer, selectively etching the second metal layer and the metal seed layer to provide pad frame circuitry, and building up metal on selective portions of the pad frame circuitry to define a plurality of die connect pads separated by a second layer of dielectric material, the die connect pads being electrically connected to the contact pads by the pad frame circuitry.

Abstract: Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.

Abstract: Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.

Abstract: A method of correcting a lithographic process is provided. A physical vapor deposition process (PVD) is performed to deposit a film on a wafer. The asymmetrical deposition of the film on the sidewalls of an opening is related to the change of target consumption in the PVD process. Therefore, the positional shift in an overlay mark may change each time. However, a formula relating target consumption with the degree of positional shift can be derived. The formula is recorded by a controller system. A compensation value can be obtained from the controller system and fed back in a subsequent lithographic process. Thereafter, a photoresist layer is formed on the film and a lithographic process is performed to pattern the photoresist. Since the compensation value can be fed back in the lithographic process via the controller system to correct for the positional shift in the overlay mark resulting from target consumption in the PVD process, errors in measuring the overlay mark can be reduced.