Abstract: A method of generation of exposure data for charged particle beam exposure using a block mask, in which a first transmission beam is formed by transmission of a charged particle beam through a rectangular first transmission aperture; a second transmission beam is formed by causing the first transmission beam to be transmitted through a block mask having a plurality of discrete patterns; and the second transmission beam irradiates an object for exposure. This exposure data generation method has a step of generating irradiation position data of the first transmission beam on the block mask, such that the Y-direction or X-direction edge of the first transmission beam is positioned in a common isolated area in the X direction or Y direction of the plurality of discrete patterns in the block mask.

Abstract: A flexible radiation source. The flexible radiation source has a layer of flexible material with at least one radionuclide dispersed therein to form a flexible, radioactive matrix. A layer of flexible nonradioactive material is also provided to which the flexible, radioactive matrix is permanently attached. The flexible radiation source can be folded or rolled from an extended or planar configuration to a folded or rolled configuration without causing the at least one radionuclide from becoming separated therefrom. The flexible matrix material is free from encapsulation by any rigid structure when in use. A storage and shielding container with a compact form factor is provided. The form factor of the storage and shielding container accommodates the flexible radiation source when the flexible radiation source is in its rolled or folded configuration, but does not accommodate the flexible radiation source when it is in fully extended or planar configuration.

Abstract: In a radiation source for the generation of short-wavelength radiation, it is the object of the invention to effectively increase the protection of the collimator optics by a buffer gas without substantially reducing the radiation transmission. A vacuum chamber which encloses a radiation-emitting plasma and is outfitted with at least one feed line and one outlet line for a buffer gas in order to ensure protection against debris for at least one optical element which directs the radiation to a radiation outlet opening in the vacuum chamber has chamber areas with particle deceleration of varying magnitude by the buffer gas. The particle deceleration is greater at least in a first chamber area in which the optical element is arranged than in any other chamber area.

Abstract: A medium detection apparatus is provided with: a light emitting section adapted to emit light; a light receiving section adapted to detect reflected light and output an output value in accordance with an amount of the reflected light; a medium supporting section adapted to support a medium and having a diffusing section adapted to diffuse the light emitted from the light emitting section; and a controller adapted to detect an edge of the medium based on a difference between the output value of the light receiving section when the light receiving section detects light reflected from the medium and the output value of the light receiving section when the light receiving section detects light reflected from the medium supporting section.

Abstract: A system for detecting liquid flow from a nozzle in a semiconductor processing device includes a first fiber optic sensor, a second fiber optic sensor, and an amp. The first fiber optic sensor and second fiber optic sensor are located on opposite sides of at least one nozzle. The first fiber optic sensor transmits light, and the second fiber optic sensor receives more of the light when the nozzle is not dispensing liquid than when the nozzle is dispensing liquid. The amp is coupled to the first fiber optic sensor and second fiber optic sensor. The amp indicates whether the nozzle is dispensing liquid according to an amount of the light received at the second fiber optic sensor.

Abstract: A method of acquiring at least one image from an image recording medium using a pulsed radiation source is provided. In one aspect, a method of scanning an image recording medium that has been exposed to X-ray radiation comprises providing first radiation along a plurality of scan traces over a surface of the image recording medium such that the first radiation does not impinge on the image recording over at least one interval along each of the plurality of scan traces. The pulsed laser source may reduce and/or eliminate cross-influence artifacts in images resulting from pulsed radiation image acquisition.

Abstract: A multibit phase change memory device structured such that a plurality of individual phase change memory devices are aligned in a plan area or vertically, and a method of driving the same are provided. The multibit phase change memory device includes a phase change material layer having a plurality of contact portions being in contact with a heating electrode, and having a plurality of active regions, each active region forming a unit phase change memory device. The phase change material layer may be composed of one material layer in which the plurality of active regions are aligned in plural arrays. Alternatively, the phase change material layer may be composed of a plurality of phase change material layers in which one or plural active regions are respectively aligned in one array. The plurality of phase change material layers may be disposed in a same level of a plan area, or the plurality of phase change material layers may be respectively disposed on different plan areas in a same vertical line.

Abstract: Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

Abstract: This invention relates to electroluminescent silylated pyrene compounds. It also relates to electronic devices in which the active layer includes an electroluminescent silylated pyrene compound.

Abstract: An organic light-emitting display has a first pattern overlapping with one first electrode portion which overlaps with the via-hole. The first pattern is protruded upward as compared with the first electrode. The other first electrode portion on which the first pattern is not formed is exposed. An emission layer is located on the first electrode. A second pattern may be further formed around the first pattern. The second pattern is spaced apart from the first electrode and protruded upward as compared with the first electrode extended onto the via-hole insulating layer. The first pattern and the second pattern may be connected to each other. With this structure, deterioration of the organic emission layer can be prevented.

Abstract: An electromagnetic detector includes an insulating substrate, whereon a charge storage capacitor, a charge collection electrode connected to the charge storage capacitor, and a semiconductor film having electromagnetic conductivity are laminated in this order. The charge collection electrode has an uneven section composed of at least a concave or convex part, dedicated for use in reinforcing a bonding strength between the semiconductor film and the charge collection electrode. With this structure, a peeling of the semiconductor film can be prevented.

Abstract: In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent to the first heat conduction film, the second heat conduction film having a lower thermal conductivity than the first heat conduction film, a polysilicon film on the second heat conduction film and the first heat conduction film adjacent to the second heat conduction film, and a gate stack on the polysilicon film. The second heat conduction film may either be on the first heat conduction film or, alternatively, the first heat conduction film may be non-contiguous and the second heat conduction film may be interposed between portions of the non-contiguous first heat conduction film.

Abstract: To prevent an electrostatic discharge in transistors constituting a driving circuit built in a substrate. The shift register and the level shifter constituting a scanning line driving circuit include TFT elements respectively which employing the polysilicon layer formed on the element substrate as a semiconductor layer. Each TFT element constituting the level shifter has a gate electrode opposing the channel region of the polysilicon layer with an insulating layer interposed therebetween. Each polysilicon layer is shared by a plurality of TFT elements with being separated from each other. The total area ‘S’ of each polysilicon layer which opposes the gate electrode of the TFT element is 3000 ?m2 or less.

Abstract: A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

Abstract: A VCSEL die is packaged so that its optical axis is at a predetermined non-perpendicular and nonparallel angle relative to the plane of a PCB to which the packaged die will be mounted. The die is packaged to form an emitting component which is shaped to orient the VCSEL optical axis at the predetermined angle when the component is placed onto a PCB. The component can be used in combination with a flip-chip sensor IC located on an opposite side of a PCB from the emitting component. The component can also be used in combination with a CSP sensor IC on the same side of a PCB. A VCSEL die and sensor IC can be contained in a single package. The optical axis of the VCSEL die packaged with a sensor IC may or may not be perpendicular to a plane of an array in the sensor IC.

Abstract: A method of reducing the internal reflected light in an OLED device comprising the step of either scattering light emitted from the OLED or removing light emitted from the OLED. An OLED device comprising a color changing medium film, a transparent substrate, and either a means for scattering light emitted from the OLED or a means for removing light emitted from the OLED such that the internal reflected light is reduced.

Abstract: The invention relates to an arrangement comprising at least two different electronic semiconductor circuits (HS) in which each of the semiconductor circuits (HS) is a component made of semiconductor material and which has an electrically active surface and electronic contacts, and corresponding contacts of the semiconductor circuits are connected to one another in an electrically conductive manner. In order to simplify production, the semiconductor circuits (HS) are produced in a common support (12) made of semiconductor material and are connected to one another in an electrically conductive manner. Electrically conductive contacts (18) that are connected to the semiconductor circuits (HS) are produced on the surface of the support (12) by metallizing the support. Said support (12) has an expansion (13), which is made of the same material, forming a unit with the same, and which is provided for accommodating additional switching elements or components.

Abstract: The invention provides gallium nitride material devices, structures and methods of forming the same. The devices include a gallium nitride material formed over a substrate, such as silicon. Exemplary devices include light emitting devices (e.g., LED's, lasers), light detecting devices (such as detectors and sensors), power rectifier diodes and FETs (e.g., HFETs), amongst others.

Abstract: An optical functional film comprises a multilayer film formed by stacking a plurality of films. The plurality of films are formed by a same material and refractive indices of adjacent films are different.

Abstract: A device transfer method includes the steps of: covering a plurality of devices, which have been formed on a substrate, with a resin layer; forming electrodes in the resin layer in such a manner that the electrodes are connected to the devices; cutting the resin layer, to obtain resin buried devices each containing at least one of the devices; and peeling the resin buried devices from the substrate and transferring them to a device transfer body. This device transfer method is advantageous in easily, smoothly separating devices from each other, and facilitating handling of the devices in a transfer step and ensuring good electric connection between the devices and external wiring, even if the devices are fine devices.

Abstract: A vertical power semiconductor component, e.g. a diode or an IGBT, in which there are formed, on the rear side of a substrate, a rear side emitter or a cathode emitter and, over that, a rear side metal layer that at least partly covers the latter, is defined by the fact that, in the edge region of the component, provision is made of injection attenuation means for reducing the charge carrier injection from the rear side emitter or the cathode emitter into said edge section.

Abstract: A static random access memory (SRAM) device including a substrate and an SRAM unit cell. The substrate includes an n-doped region interposing first and second p-doped regions. The SRAM unit cell includes: (1) a first pass-gate transistor and a first pull-down transistor located at least partially over the first p-doped region; (2) first and second pull-up transistors located at least partially over the n-doped region; and (3) a second pass-gate transistor, a second pull-down transistor, and first and second read port transistors, all located at least partially over the second p-doped region. A boundary of the SRAM unit cell comprises first and second primary dimensions having an aspect ratio of at least about 3.2.

Abstract: A small semiconductor display device of low power consumption and with high definition/high resolution/high image quality is provided. The semiconductor display device according to the present invention includes a pixel matrix circuit, a data line driver circuit and scanning line driver circuits, and these components are formed on the same substrate using a polycrystalline TFT. The fabricating method of the device which includes a process for promoting crystallization by a catalytic element and a process for gettering the catalytic element provides the semiconductor display device with high definition/high resolution/high image quality while it is small in size.

Abstract: A protective coating for a surface comprising a layer permeable to hydrogen, said coating being deposited on a catalyst layer; wherein the catalytic activity of the catalyst layer is preserved.

Abstract: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.

Abstract: A double-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is fabricated from a silicon-on-insulator (SOI) substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A photodiode set is formed in the SOI substrate, including a first and second photodiode formed as a double-junction structure in the Si substrate. A third photodiode is formed in the Si top layer. A (imager sensing) transistor set is formed in the top Si layer. The transistor set is connected to the photodiode set and detects an independent output signal for each photodiode. The transistor set may be an eight-transistor (8T), a nine-transistor (9T), or an eleven-transistor (11T) cell.

Abstract: A solid-state imaging device including a photoelectric conversion portion and a charge transfer portion equipped with charge transfer electrodes to transfer the charge generated in the photoelectric conversion portion, wherein the charge transfer portion is provided with a charge transfer electrodes having a first electrode including a first layer electric conductive film, and a second electrode having a second layer electric conductive film provided contiguously to the first electrode with an electrode insulating film therebetween, and the first electrode is coated with a silicon oxide film that is the electrode insulating film formed by side wall oxidation in the state that the upside is coated with an antioxidizing film so as to coat the side wall.

Abstract: A method of implanting, for example, a phosphorous plug over a charge collection region and a method of forming a contact over the phosphorous plug implant and charge collection region. The method allows implantation of phosphorous or other materials without contamination of other contact regions. The method further allows implantation of a material with only one step and without an extra masking step.

Abstract: A method and system for providing a magnetic element is disclosed. The method and system include providing a free layer, a spacer layer, and a pinned layer. The free layer is ferromagnetic and has a free layer magnetization. The spacer layer is nonmagnetic and resides between the pinned and free layers. The pinned layer includes first and second ferromagnetic layers having first and second magnetizations, a nonmagnetic spacer layer, and a spin depolarization layer. Residing between the first and second ferromagnetic layers, the nonmagnetic spacer layer is conductive and promotes antiparallel orientations between the first and second magnetizations. The spin depolarization layer is configured to depolarize at least a portion of a plurality of electrons passing through it. The magnetic element is also configured to allow the free layer magnetization to change direction due to spin transfer when a write current is passed through the magnetic element.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate and including a film which contains Pb, Sr, Zr, Ti, Ru and O and a dielectric film which contains Pb, Zr, Ti and O and which is provided on the film containing Pb, Sr, Zr, Ti, Ru and O.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a layer of doped polysilicon within a container in an insulative layer disposed on a substrate; forming a barrier layer over the polysilicon layer within the container; removing the insulative layer to expose the polysilicon layer outside the container; nitridizing the exposed polysilicon layer at a low temperature, preferably by remote plasma nitridation; removing the barrier layer to expose the inner surface of the polysilicon layer within the container; and forming HSG polysilicon over the inner surface of the polysilicon layer. The capacitor can be completed by forming a dielectric layer over the lower electrode, and an upper electrode over the dielectric layer. The cup-shaped bottom electrode formed within the container defines an interior surface comprising HSG polysilicon, and an exterior surface comprising smooth polysilicon.

Abstract: A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of the way down the mesa, leaving a portion of the drain abutting the trench. The body region in the second mesa includes a channel region adjacent a wall of the trench. The area where the drain abuts the trench is thus relatively restricted and the drain-gate capacitance of the device is reduced. Moreover, the drain-gate capacitance is made independent of the depth and width of the trenches, allowing greater freedom in the design of the MOSFET.

Abstract: A MOS transistor, and a method for producing the same, is provided with a source region, a gate-region, a drain region, and a drift region in an SOI wafer. The SOI-wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region. Whereby, the active semiconductor layer, at least in a portion of the drift region, is thicker than in the source region. The MOS transistor is characterized in that the active semiconductor layer, in a vertical direction, is completely separated by the insulating intermediate layer from the carrier layer.

Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.

Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.

Abstract: An improved surface P-channel transistor includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting the gate oxide layer to a remote plasma nitrogen hardening treatment followed by an oxidative anneal, and forming a polysilicon layer over the resulting gate oxide layer. Significantly, the present invention does not require nitrogen implantation through the polysilicon layer overlying the gate oxide and provides a surface P-channel transistor having a polysilicon electrode free of nitrogen and a hardened gate oxide layer characterized by a large concentration of nitrogen at the polysilicon electrode/gate oxide interface and a small concentration of nitrogen at the gate oxide/semiconductor substrate interface.

Abstract: A method for forming through hole vias in a substrate uses a partially exposed seed layer to plate the bottom of a blind trench formed in the front side of a substrate. Thereafter, the plating proceeds substantially uniformly from the bottom of the blind hole to the top. To form the through hole, the rear face of the substrate is ground or etched away to remove material up to and including the dead-end wall of the blind hole.

Abstract: The prevent invention is to provide a solid-state imaging device having a electrode configuration applicable to a progressive scan, and able to reduce a obstruction of incident light at the periphery of a light receiving portion, a method of producing the same, a camera including the same. A first transfer electrode, a second transfer electrode, and a third transfer electrode which have a single layer transfer electrode configuration are repeatedly arranged in a vertical direction. The first transfer electrodes are connected in a horizontal direction by an inter-pixel interconnection formed in the same layer. Shunt interconnections are formed in the horizontal direction and in the vertical direction above the transfer layers. The shunt interconnection connected to the second transfer interconnection is formed on the inter-pixel interconnection. The shunt interconnection connected to the third transfer electrode is formed above the transfer electrodes.

Abstract: A method is disclosed for forming at least one image sensor with improved sensitivity along with at least one transistor device. The method comprises forming at least a portion of the transistor device on a substrate, forming the image sensor by doping a predetermined area separated from the transistor device by a minimum predetermined distance, forming an etch stop layer for covering a contact area of the transistor device, removing at least a portion of the etch stop layer in the predetermined area for exposing the image sensor, and covering the image sensor and the transistor device by at least one transparent protection layer.

Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.

Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

Abstract: To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer (6) is deposited on a first electrode (2, 3, 5). This auxiliary layer (6) is then opened up (15) via the first electrode. Then, a dielectric layer (7) is produced, and the metal track stack (8, 9, 10) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

Abstract: The present invention provides a phase change memory cell comprising (GeASbBTeC)1-X(RaSbTeC)X solid solution, the solid solution being formed from a Ge—Sb—Te based alloy and a ternary metal alloy R—S—Te sharing same crystal structure as the Ge—Sb—Te based alloy. A nonvolatile phase change memory cell in accordance with the present invention provides many advantages such as high speed, high data retention, and multi-bit operation.

Abstract: A chip circuit comprising a chip which comprises a semiconductor substrate and substantially plane components formed on the said substrate, among which there are an emitting component capable of emitting electromagnetic radiation and an inductor sensitive to the incident electromagnetic radiation. At least one shield, external to the chip, is placed opposite the inductor at a distance of less than 500 microns. The shield thus makes it possible to shield the sensitive inductor from the emitting component, while maintaining the quality factor of the inductor.

Abstract: A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member that is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Semiconductor dice are bonded to the paddles by, e.g., conventional semiconductor die attachment methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.

Abstract: The invention relates to an integrated circuit package, in particular an integrated chip size package or an integrated chip scale package, comprising a substrate carrying a die, and connection elements, interconnection elements, connecting pins of said die with said connection elements, and a mold encapsulating said die on said substrate. To increase reliability and to reduce failure due to deformation stress, the invention provides said mold with reduced stiffness at areas located substantially at one of said interconnection elements providing increased flexibility of said package at said areas compared to other areas of said package.

Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.

Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

Abstract: A module card structure includes a structure, a first chip, a second chip, an adhesive layer, and a compound layer. The substrate has an upper surface on which a plurality of golden fingers are formed, and a lower surface. The first chip is mounted on the upper surface of the substrate and is electrically connected to the golden fingers by first wires. The second chip is adhered to the upper surface of the substrate by the adhesive layer, which includes glue and filling elements, and is electrically connected to the golden fingers by second wires. The compound layer is encapsulated on the first chip and the second chip.