Abstract: A receive circuit having a sampling circuit and a threshold generating circuit. The sampling circuit generates a first sample value having either a first state or a second state according whether an incoming signal exceeds a first threshold level, the first threshold level corresponding to a first threshold value. The threshold generating circuit combines a first control value and a second control value to generate the first threshold value and provides the first threshold value to the sampling circuit.

Abstract: A differential output driver capable for selectively switching from an emphasis mode, a non-emphasis mode, and an idle state uses one pull-up device and two pull-down devices per output lead. The pull-up device is preferably always activated, and one or the other or both or neither of the pull-down devices are selectively activated to provide a desired behavior. Neither pull-down device is strong enough to singularly overcome the pull-up device and fully pull down an output lead to an emphasis logic low level. One of the pull-down devices is singularly strong enough to bring an output lead to a non-emphasis logic low level, which is higher than an emphasis logic low level. The other pull-down device is singularly strong enough to pull an output line from an emphasis logic high level to a non-emphasis logic high level. Working together, however, both devices can pull-down an output lead to an emphasis logic low level.

Abstract: Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in response to a select signal.

Abstract: An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.

Abstract: Methods of setting and/or resetting a lookup table (LUT) programmable to operate in shift register mode. The LUT is configured to operate as a shift register, and the final bit of the shift register is implemented using a memory element associated with the LUT. The shift register is reset (or set) by applying a reset (set) signal to the memory element, while providing a low (high) value from the memory element to a shift-in input terminal of the LUT; and shifting the low (high) value through the bits of the shift register. To perform this task, a write enable signal is provided that is independent from the reset (set) signal of the memory element and enables a shift clock signal. The shift clock signal is then repeatedly toggled to shift the low (high) value from the memory element successively through each bit of the shift register, while the value stored in the memory element is held constant by means of the independent reset (set) signal.

Abstract: Bidirectional register segmented data busing and addressing for such busing is described. A segmented databus includes data register segments coupled to one another via respective databus segments. Bidirectional drivers are coupled between the data register segments and the databus segments associated therewith. The bidirectional drivers are configurable for driving information along the segmented databus, wherein the databus segments are for both read and write busing.

Abstract: Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an N×1 MUX. The N×1 MUX is controlled by the skew controller. The output of the N×1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.

Abstract: A transconductance stage is provided. The transconductance stage includes a tail current source, a differential pair, and two current mirrors. The input to each of the current mirrors is connected to the drain of a separate one of the transistors in the differential pair. The two current mirrors each have two outputs so that one of the outputs can be used to determine whether the output current exceeds a threshold (e.g. nine-tenths of the tail current). If the source current exceeds the threshold, extra source current is switched in to the output so that output source current is increased. Similarly, if the sink current exceeds the threshold, extra sink current is switched in to the output so that the output sink current is increased. This way, the transconductance stage can supply large output currents in response to a large signal input but maintains low quiescent current for small input signals.

Abstract: A differential amplifier circuit has a latch unit and a differential input portion. A minute current is kept to flow through the differential input portion. Therefore, the differential amplifier circuit can accurately amplify even a signal high in speed and small in amplitude.

Abstract: A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.

Abstract: A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings.

Abstract: An amplitude limiting value can be set to an intended value of a designer and the dependence of the amplitude limiting value on the temperature can be avoided.

Abstract: A CMOS input buffer supporting multiple I/O standards and having a pair of NMOS and PMOS differential receivers, each having a first input connected to an input pad and a second input connected to a reference voltage, a first multiplexer connected to the control terminal of the current sink of the NMOS differential receiver and having one input connected to the positive supply terminal, and a second multiplexer connected to the control terminal of the current source of the PMOS differential receiver and having one input connected to the negative supply terminal or ground. The buffer further includes an inverter connected to a combined output of the PMOS and NMOS differential receivers and having an output connected to the second input of the first and second multiplexer, and a configuration storage bit for selecting the desired inputs of the first and second multiplexer, thereby supporting high speed standards as well as general purpose standards while reducing static power dissipation.

Abstract: The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.

Abstract: Techniques to avoid crowbar current are provided. An integrated circuit according to an embodiment of the present invention includes a first node having a first supply voltage level. A first level shift circuit is connected between the first node and a first path. A second level shift circuit is connected between the first node and a second path. The first path includes an even number of inverter stages, while the second path includes an odd number of inverter stages. The first and second level shift circuits are configured to output a signal at the second supply voltage level. The integrated circuit also includes a PMOS transistor and an NMOS transistor connected in series between a second node having the second supply voltage level and a reference voltage. A gate of the PMOS transistor is connected to the first path, and a gate of the NMOS transistor connected to the second path.

Abstract: An output stage interface circuit (1) comprises a main bipolar transistor (Q1) coupling a data output terminal (5) to a first rail (2) to which the positive of the power supply voltage (VDD) is applied, and a substrate diffusion isolated main NMOS transistor (MN1) coupling the data output terminal (5) to a second rail (3) which is held at ground. Control signals from a data control circuit (6) selectively operate the main bipolar transistor (Q1) and the main MOS transistor (MN1) for determining the logic high and low states of the data output terminal (5) during data output.

Abstract: A memory device has refresh cycles to refresh memory cells of the memory device. The time interval between one refresh cycle to the next refresh cycle is a refresh interval. The refresh interval depends on a frequency of an oscillating signal. A refresh timer adjusts the frequency of the oscillating signal based on changes in the temperature to adjust the refresh interval.

Abstract: A prescaler circuit includes: a frequency number switching part including first to sixth D-type flip-flop circuits, first and second AND circuits and first and second OR circuits; and a frequency division switching control part including a third AND circuit, a third OR circuit and first and second NOR circuits. The frequency number switching part has a function of controlling the frequency division among frequency division numbers of 1/N, 1/(N+1) and 1/(N+2) via the first and the second AND circuits by controlling modulus signals input to the first and the second NOR circuits. The frequency division switching control part has a function of controlling the frequency division between ?-frequency-division and 1/16-frequency-division by controlling a modulus signal input to the third AND circuit. A margin for a delay time that causes misoperation at the time of the switching of frequency division numbers can be increased.

Abstract: A delay-locked loop (DLL) acquires correct lock when the delay line on the DLL delays a reference signal by one clock period. False lock occurs when the delay line delays the reference signal by more than one clock period. False lock may be detected by a false lock detector. The false lock detector may include (1) flip-flops to take samples of the delay line outputs and (2) combinational logic for detecting patterns in the samples that may indicate false lock. Once false lock has been detected, a hold circuit may ensure that false lock persists for at least the amount of time required by the DLL to acquire lock (i.e., to prevent reset of the DLL before it has acquired lock). After this determination is made, a reset generator may produce a reset signal for resetting the DLL.

Abstract: In one embodiment of the present invention, a phase generator, comprising a plurality of delay blocks, is coupled in a feedback loop with a phase detector. When in an open loop mode, the phase generator is operable as a voltage controlled delay line. The phase detector compares an input signal with a first output signal of the phase generator and generates a first control signal based thereon. The phase generator is also coupled in a feedback loop with a phase-frequency detector. When in a closed loop mode, the phase generator is operable as a voltage controlled oscillator and the phase-frequency detector compares the input signal with a second output signal of the phase generator. The phase-frequency detector then generates a second control signal based thereon.

Abstract: A configurable latch comprises a dual master stages arranged in parallel to share a single output node. The configurable latch provides a single slave stage at the single output node to be shared between the two master stages. Pass gates controlled by various phases of an input clock, controls access to the slave stage by the two master stages. Additional control is added to configure the latch for positive edge triggered and negative edge triggered flip-flop functionality as well as level sensitive functionality. Chip enable, set, and reset are also provided for additional control.

Abstract: A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.

Abstract: A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.

Abstract: A pulse generator electrical circuit capable of operating as both a clock-based pulse generator and a delay-based pulse generator while minimizing the limitations of these two types of pulse generators is disclosed. When the pulse generator operates in “delay mode,” the smallest output pulse width possible corresponds to the minimum set point delay between the two delay circuits. The largest possible output pulse width corresponds to the difference between the maximum and minimum of the delay circuits. When the pulse generator operates in “clock mode,” the output of one of the delay circuits is blocked so that the output of the gate depends solely on the output of other delay circuit. This limits the lower pulse width interval to that of the retimer clock, but allows for an arbitrarily long (wide) pulse.

Abstract: Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.

Abstract: Signal transmission circuitry on an integrated circuit ameliorates the effects of possible inequality in rise and fall times of buffer circuits along the transmission circuitry by providing at least one of the buffer circuits as an inverting buffer circuit and at least one other of the buffer circuits as a non-inverting buffer circuit. The invention may be of particular interest for use in clock signal distribution networks on integrated circuits such as programmable logic devices.

Abstract: A voltage subtracting circuit includes a conversion circuit, a holding circuit, and a differential voltage generator. The conversion circuit converts a first voltage input during a first period into a first current proportional to the first voltage. The conversion circuit further converts a second voltage input during a second period following the first period into a second current proportional to the second voltage. The holding circuit holds the first current during the first period as a third voltage. The holding circuit further outputs the first current during the second period on the basis of the third voltage. The differential voltage generator outputs a differential voltage between the second voltage and the first voltage during the second period on the basis of the second current output by the conversion circuit and the first current output by the holding circuit.

Abstract: To turn on a JFET, a two-stage turn-on current control is employed in a JFET driver circuit and a JFET driving method, by which a shortly pulsed high sourcing current is provided to turn on the JFET rapidly and efficiently, and a continuous low sourcing current is provided after the JFET turns on for reducing the power dissipation. After the JFET turns off, a negative charge pump is also employed to promise the JFET at a turn-off state. A special power sequence is further employed to ensure the JFET could be turned off during the power supply coupled to the JFET starts up.

Abstract: A method includes controlling the connection of a charge pump output to a load capacitor as a function of activation control signals to an oscillator controlling the charge pump. A charge pump system includes a charge pump, an oscillator, a switching element and an enable signal generator. The switching element connects and disconnects the charge pump from a load capacitor. The enable signal generator is connected to the oscillator and to the switching element and enables and disables the oscillator and the switching element as a function of the output of the charge pump.

Abstract: A high voltage switching circuit of a NAND type flash memory device that includes a clock level shifter for increasing an amplitude of a clock signal, a pass voltage generator for outputting a pass voltage by pumping a power source voltage in response to a clock signal with an increased amplitude, and a high voltage pass transistor for transferring a high voltage according to the pass voltage.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

Abstract: A reference voltage and reference current generator supplies a reference voltage and a reference current, both having stable levels regardless of temperature variation. The reference voltage and reference current generator includes a reference voltage generating unit, a first current mirror, a temperature compensation MOS transistor and a second current mirror. The reference voltage generating unit outputs a reference voltage having a stable level regardless of temperature variation and process variation by using junction voltage characteristic and thermal voltage characteristic of a bipolar transistor, and supplies an inner current corresponding to the thermal voltage characteristic. The first current mirror supplies a first current by mirroring the inner current. The temperature compensation MOS transistor supplies a second current corresponding to the reference voltage through the source-drain stage.

Abstract: An electrical circuit is disclosed that is capable of improving the power supply rejection ratio of a standard bandgap reference while maintaining the temperature coefficient of the standard design. One embodiment of the circuit comprises a bandgap reference voltage generator, an operational amplifier, a transistor, a voltage divider, a startup network, and a self-biasing network that provide a voltage reference with improved characteristics.

Abstract: Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.

Abstract: A circuit architecture (200) for implementation of compensation based on Miller capacitors in multi-stage chopped amplifiers includes insertion of an additional chopper (206) in the compensation feedback (118, 120) pathway. Such compensation is more area efficient than parallel compensation and allows higher bandwidth in multistage amplifiers. The insertion of a chopper in the Miller capacitance feedback loop provides a means to selectively adjust the phase of the feedback by 180 degrees.

Abstract: A method and apparatus is used to provide DC stabilization and noise reduction in a multistage power amplifier. The invention uses various feedback techniques to stabilize DC levels, which helps to reduce noise. The invention also uses other techniques to reduce noise, and to reduce the noise transfer function in a power amplifier.

Abstract: The present invention relates to an AGC circuit, a AGC circuit gain control method, and a program for the AGC circuit gain control method, and may be applied to IC recorders, for example, as a portable recording/reproducing device, in order to ameliorate problems of listening to talk, music and the like during playback from IC recorders. In the invention, a signal level L1cyc is detected in units of the period of an input signal, and a recovery time constant r is switched on the basis of a decision as to the signal level L1cyc based on an average shift Lavg of the signal level L1cyc.

Abstract: A differential pair of transistors includes a first transistor and a second transistor having their sources coupled together. Their sources are further coupled to ground via a pull-down network. A single-ended output is coupled to the drain of the second of the pair of differential transistors. A differential current adjust circuit is coupled to a drain of the first of the pair of differential transistors, and the current adjust circuit is configured so that the second side of the differential output driver circuit conducts approximately the same current as the first side of the differential output driver circuit.

Abstract: An amplifier with increased bandwidth by current injection and a method thereof. The amplifier includes an input stage for receiving a first input signal, a load stage coupled to the input stage for generating a first output signal, a first current source coupled to the input stage for allowing a predetermined current to flow, and a second current source, coupled to the input stage, for injecting a first current into the input stage for outputting the first output signal.

Abstract: A differential amplifier comprises an operational amplifier, comprising a positive output terminal, a negative output terminal, and a feedback terminal; a common mode sensing circuit coupled to the positive output terminal and the negative output terminal, for generating a sensed common mode voltage of the positive output terminal and the negative output terminal of the operational amplifier; and a feedback circuit comprising a common mode input terminal for receiving the sensed common mode voltage, a reference input terminal for receiving a reference voltage, and a first resistive component coupled between the common mode input terminal and the reference input terminal, the feedback circuit generating a feedback signal according to the common mode voltage and the reference voltage; wherein the feedback terminal of the operational amplifier receives the feedback signal of the feedback circuit.

Abstract: Provided is a method of acquiring a high linear characteristic and a low distortion in a transconductor (operational transconductance amplifier), especially, in a triode region type transconductor among CMOS transconductors. A resistance is inserted in a source or a drain of an input triode transistor. The transconductor has a simple circuit structure, and has a large linear region, constant transconductance and low total harmonic distortion (THD) characteristic within an error region.

Abstract: A differential amplifier can include input transistors for receiving a differential input signal and an inductor connected to the input transistors. The inductor can protect a voltage supply from radio frequency in the differential input signal. The accuracy of this differential amplifier can be significantly improved by including a bias network. This bias network advantageously allows a bias current in the input transistors to be set independently of a voltage drop across the inductor.

Abstract: As the gain control amplifiers for amplifying the reception signal, the step amplifiers are used. Two sets of these step amplifiers are provided and are then controlled to be used alternately. When switching of the gain occurs, after the gain is switched with the step amplifier not operated and offset is cancelled, the amplifier to which the reception signal is inputted is switched. Accordingly, the step amplifier can be used as the gain control amplifier for amplifying the reception signal to provide almost constant power consumption even when the gain is changed depending on the intensity of reception signal in the semiconductor integrated circuit device for communication to form a wireless communication system of dual-mode or more modes including the W-CDMA system. As a result, the operation life of battery, namely, the reception waiting period and communication period by single charging process can be expanded.

Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections (102, 104, 106, and 108) and a plurality of drivers (110, 112, 114, and 116). Each of the plurality of drivers receives a common transmit signal (118) and an individual control signal (120, 122, 124, and 126). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal (128, 130, 132, and 134) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

Abstract: An electronic circuit contains a controller integrated circuit and a power amplifier MMIC connected to the controller IC. The power amplifier MMIC contains a radio frequency power amplifier. The RF power amplifier is a double heterojunction bipolar transistor. The controller IC has an operational amplifier that supplies a DC bias to the base of the RF power amplifier through a ballast resistor. The operational amplifier has an output slope that compensates either partially or entirely for the voltage drop across the ballast resistor. A reference circuit in the power amplifier is disposed close enough to the power amplifier to mirror fluctuations in the base-emitter voltage caused by temperature fluctuations.

Abstract: An integrated preamplifier circuit for detecting a signal current from a photodiode and converting the signal current into an output voltage is provided. The circuit includes a signal amplifier and a dummy amplifier, the dummy amplifier being matched to the signal amplifier. Each of these amplifiers includes an input transistor and an output transistor, the input transistor of the signal amplifier receiving an input signal derived from the signal current and the input transistor of the dummy amplifier receiving no input signal. The signal and dummy amplifiers provide the desired differential output signal. The input transistors of the signal and dummy amplifiers each have a biasing current source forced to follow a reference current source implemented within the integrated circuit.

Abstract: A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generated by a pattern generator. The pattern generator output forms an input to a digitally controllable delay line which receives the lower frequency clock signal. The pattern generator causes the digital delay line to vary a frequency of the lowered frequency clock signal between selected boundaries. The varying frequency clock signal is then raised up again such that a final clock has a varying frequency, and will exhibit less EMI spiking during switching of an associated, synchronous digital data device. The solid state nature of the generator allows for simple fabrication, inexpensive manufacture and ready integration into digital circuitry, such as multifunction integrated circuits.

Abstract: A divider for a local oscillator (LO) generator system of a phase locked loop (PLL) in a transceiver chip. The divider includes at least one divider unit. Each divider unit includes a frequency divider unit for receiving an input signal having an input frequency and for outputting an output signal having an output frequency which is approximately one half of the input frequency. Each divider unit also includes a resistor bank coupled between a voltage source and the frequency divider unit, and a current stirring unit for supplying current to the frequency divider unit. The resistance of the resistor bank and a magnitude of the current supplied by the current stirring unit are variable depending on the input frequency.

Abstract: A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.

Abstract: An oscillator of a semiconductor memory device, wherein a reference voltage that flexibly shifts according to the shift in a power supply voltage is generated, and a reference clock is generated using the reference voltage. It is thus possible to generate the reference clock having a constant cycle regardless of the shift in the power supply voltage which can keep constant the duration period of internal control signals of devices, such as a timer and a pump circuit, which are synchronized to the reference clock.