Abstract: The present invention relates to isolated polypeptides having beta-glucosidase activity and isolated polynucleotides encoding the polypeptides. The invention also relates to nucleic acid constructs, vectors, and host cells comprising the polynucleotides as well as methods for producing and using the polypeptides.

Abstract: The present invention relates to recombinant human BACE polypeptides. More particularly, the invention relates to recombinant human BACE polypeptides that have a modified amino acid sequence at position 33 of the BACE sequence, as well as to polynucleotides, expression vectors, host cells, and methods for producing the modified recombinant human BACE polypeptides.

Abstract: Chromobacterium suttsuga sp. nov., a new species of the genus Chromobacterium which possesses insecticidal activity, is described. The invention also relates to insecticidally-active metabolites obtained from the strain and to insecticidal compositions comprising cultures of the strain and/or supernatants, filtrates, and extracts obtained from the strain, and use thereof to control insect pests.

Abstract: The present invention relates to a novel microorganism, Corynebacterium ammoniagenes strain CJIP009 having Accession No. KCCM-10226, which is capable of producing 5?-inosinic acid and a process for producing 5?-inosinic acid using the same.

Abstract: The invention relates to a new series of bacterial plasmid vectors which are fully devoid of CpG and which can express synthetic genes which do not contain CpG in the bacteria Escherichia coli.

Abstract: Methods of increasing yields of succinate using aerobic culture methods and a multi-mutant E. coli strain are provided. Also provided is a mutant strain of E. coli that produces high amounts of succinic acid.

Abstract: An apparatus and method for performing hybridization or binding assays under thermophoretic conditions is provided.

Abstract: The invention is a method for the development of assays for the simultaneous detection of multiple bacteria. A bacteria of interest is selected. A host bacteria containing plasmid DNA from a T even bacteriophage that infects the bacteria of interest is infected with T4 reporter bacteriophage. After infection, the progeny bacteriophage are plating onto the bacteria of interest. The invention also includes single-tube, fast and sensitive assays which utilize the novel method.

Abstract: The invention concerns recombinant vectors replicated in mycobacteria, a set of sequences coding for exported polypeptides detected by fusion with alkaline phosphatase, in particular one polypeptide, called DP428, of about 12 kD corresponding to an exported protein found in mycobacteria belonging to the Mycobacterium tuberculosis complex. The invention also concerns methods and kits for detecting in vitro the presence of a mycobacterium and in particular a mycobacterium belonging to the Mycobacterium tuberculosis complex in a biological sample using said polypeptides, their fragments or polynucleotides coding for the latter. The invention also concerns immunogenic or vaccine compositions for preventing and/or treating infections caused by mycobacteria and in particular a mycobacterium belonging to said complex, particularly tuberculosis.

Abstract: The present invention provides novel recombinant fusion proteins for detecting binding of a molecule of interest containing a detection domain, a first and optionally a second localization domain, and a binding domain. The invention also provides recombinant nucleic acid molecules and recombinant expression vectors encoding these novel fusion proteins, genetically engineered host cells containing these expression vectors, and kits for the use of these fusion proteins, nucleic acid molecules, expression vectors, and host cells. Additionally, the present invention provides methods for identifying compounds that alter the binding of a molecule of interest in a cell.

Abstract: CDR-grafted antibody heavy and light chains comprise acceptor framework and donor antigen binding regions, the heavy chains comprising donor residues at at least one of positions (6, 23) and/or (24, 48) and/or (49, 71) and/or (73, 75) and/or (76) and/or (78) and (88) and/or (91). The CDR-grafted light chains comprise donor residues at at least one of positions (1) and/or (3) and (46) and/or (47) or at at least one of positons (46, 48, 58) and (71). The CDR-grafted antibodies are preferably humanized antibodies, having non human, e.g. rodent, donor and human acceptor frameworks, and may be used for in vivo therapy and diagnosis. A generally applicable protocol is disclosed for obtaining CDR-grafted antibodies.

Abstract: The present invention relates to a method for increased production of a secreted, recombinant protein product through the introduction of molecular chaperones in a mammalian host cell. The present invention also relates to a mammalian host cell with enhanced expression of a secreted recombinant protein product by coexpressing at least one chaperone protein.

Abstract: The present invention provides viral vectors that have been engineered to contain a synthetic promoter that controls at least one essential gene. The synthetic promoter is induced by a specific gene product not normally produced in the cells in which the viral vector is to be transferred. The vectors are propagated in producer or helper cells that express the inducing factor, thereby permitting the virus to replicate to high titer. The lack of the inducing factor in the target cells precludes viral replication, however, meaning that no vector toxicity or immunogenicity arises. Where the virus carries a gene of interest, this should provide for higher level expression for longer periods of time than with current vectors. Methods for making the vectors, helper cells, and their use in protein production, vaccines and gene therapy are disclosed.

Abstract: The invention describes materials useful for calibrating methods, and standards, calibration verification, linearity, and quality control materials for any method used to detect lipids and/or lipoproteins. This invention describes methods for producing, and compositions produced thereby, stable lipid controls, standards, and reagents including a stabilizing amount of TDPA, and further including a known amount of a substantially pure constituent of interest, including total cholesterol (CHOL), triglycerides (TRIG), high density lipoprotein (HDL), APO lipoprotein A (APO-A), APO Lipoprotein B (APO-B), low density lipoprotein (LDL), apolipoprotein a Lp(a) and other lipoprotein moieties useful for calibrating, standardizing, verifying, quality control, and the like, relating to use of an instrument for assessing the level of such constituents in a sample.

Abstract: The invention provides methods and kits to detect liver fibrosis or a change in the gradation of liver fibrosis in mammals. The diagnostic marker is based on the profiling and identification of diagnostic carbohydrates present in a body fluid such as blood serum.

Abstract: The present invention provides a method for quantitatively determining a reducing substance, which comprises reacting a reducing substance in a test specimen with iron (III) ions, reacting iron (II) ions formed by reduction of the iron (III) ions or residual iron (III) ions with a metal indicator which is capable of reacting specifically with the iron (II) ions or the residual iron (III) ions to undergo color development, and carrying out quantitative determination by measuring the degree of color development, wherein a chelating agent which is specific to copper ions is added to the test specimen before the reaction of the reducing substance with the iron (III) ions; and a reagent used for it.

Abstract: A method for interpreting data that is produced after a group of amino acids and acylcarnitines are derivatized from blood spots taken from newborn babies and scanned by a tandem mass spectrometer. Concentration levels of each metabolite, which are directly proportional to the butyl ester fragment after derivatization, are compared to threshold flags for determining a significance of any deviation of the metabolite relative to the flag threshold. The threshold flags are diagnostic limits to the data retrieved from each blood spot. The data includes metabolite concentrations and molar ratios of metabolites with other metabolites. Samples are labeled normal for a disease if the concentration of any of the metabolite concentrations or molar ratio concentration do not deviate from the flag threshold, but, in contrast, the sample must be further evaluated if a value is elevated or deficient to some degree.

Abstract: The invention is directed to a method and device for simultaneously testing a sample for the presence, absence, and/or amounts of one or more of a plurality of selected analytes. The invention includes, in one aspect, a device for detecting or quantitating a plurality of different analytes in a liquid sample. Each chamber may include an analyte-specific reagent effective to react with a selected analyte that may be present in the sample, and detection means for detecting the signal. Also disclosed are methods utilizing the device.

Abstract: A method of manufacturing a semiconductor device and an apparatus of automatically adjusting a semiconductor pattern can precisely correct a difference in the shape or position of a pattern exposed or formed in two exposure steps. A pattern measuring unit measures an offset between the first pattern and the second pattern in a pattern measuring step. Based on the information on the offset thus detected, the first pattern is adjusted in a first patterning step with a high degree of freedom in the next manufacturing step cycle of a semiconductor device to precisely align the shape or position of the first pattern with the second pattern in a second patterning step with a low degree of freedom.

Abstract: When plasma ashing is performed on a resist on a wafer, deposit gas containing at least one type of deposit component to be generated from a resist by ashing is added to a gas for plasma generation supplied from a gas supply system for plasma generation, by a deposit gas supply system. By this, the deposit component is actively deposited on the inner surface of a wafer processing chamber so as to protect the inner face of the wafer processing chamber from plasma. As a result, damage of the wafer processing chamber during ashing and particle generation due to the damage are prevented.

Abstract: Two or more semiconductor devices (21 and 22) are formed on a substrate (20) and are each comprised of a plurality of printed components (23 and 24). At least one such printed component (25) is shared by both such semiconductor devices.

Abstract: A method for fabricating a liquid crystal display (LCD) device to improve picture quality by preventing defective rubbing, is disclosed. The method which includes preparing first and second substrates, forming a thin film transistor on the first substrate, forming a first orientation layer on the first substrate including the thin film transistor, performing rubbing and orientation direction alignment processes on the first orientation layer to provide a uniform alignment direction, and forming a liquid crystal layer between the first and second substrates.

Abstract: A method for fabricating semiconductor devices forms a semiconductor layer containing a positive layer on a mother substrate and then forms a metal layer on the semiconductor layer. After forming the metal layer, the method separates the mother substrate from the semiconductor layer and then removes a desired region of the metal layer from the exposed surface of the semiconductor layer from which the mother substrate has been separated to form a plurality of mutually separated semiconductor devices each containing the semiconductor layer.

Abstract: In a vertical cavity surface emitting laser diode manufactured on a non-off-angle substrate with a (100)-oriented plane or the like, anisotropic stress is applied to a central portion of an active layer by forming a asymmetrical oxidation structure in an Al high concentration portion in the mesa, so that polarization controllability of a device can be improved.

Abstract: To increase the lattice constant of AlInGaP LED layers to greater than the lattice constant of GaAs for reduced temperature sensitivity, an engineered growth layer is formed over a substrate, where the growth layer has a lattice constant equal to or approximately equal to that of the desired AlInGaP layers. In one embodiment, a graded InGaAs or InGaP layer is grown over a GaAs substrate. The amount of indium is increased during growth of the layer such that the final lattice constant is equal to that of the desired AlInGaP active layer. In another embodiment, a very thin InGaP, InGaAs, or AlInGaP layer is grown on a GaAs substrate, where the InGaP, InGaAs, or AlInGaP layer is strained (compressed). The InGaP, InGaAs, or AlInGaP thin layer is then delaminated from the GaAs and relaxed, causing the lattice constant of the thin layer to increase to the lattice constant of the desired overlying AlInGaP LED layers. The LED layers are then grown over the thin InGaP, InGaAs, or AlInGaP layer.

Abstract: In one embodiment, a method of treating a surface of a Micro-Electromechanical System (MEMS) device reduces or eliminates performance degradation due to charge migration and accumulation. Briefly, the method may include treating a dielectric surface of the MEMS device to replace hydroxyl groups with electrically neutral molecules, thereby converting the dielectric surface from a hydrophilic to a substantially hydrophobic nature. A MEMS device having a surface treated using the aforementioned method is also disclosed.

Abstract: A complementary metal oxide semiconductor image sensor and a method for fabricating the same are disclosed, wherein a width of a depletion area of a photodiode is varied by variably applying a back bias voltage to a semiconductor substrate without using any color filter, thereby preventing a back bias voltage from influencing a transistor formed on the outside of a photodiode in a CMOS image sensor sensing optical color sensitivity of light rays irradiated to the photodiode.

Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.

Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a solder bump that is disposed upon the lower surface. The stress-relief layer flows against the solder bump. A stress-compensation collar is formed on a board to which the substrate is mated and the SCC partially embeds the solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes a stress-relief layer and a stress-compensation collar is also included.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.

Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conductive-filled gel elastomer or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conductive-filled gel elastomer is applied between a die surface and the inside attachment surface of a crap-style heat sink to eliminate overpressure on the die/substrate interface.

Abstract: Final sections of the word lines are arranged in a staggered fashion to fan out and have larger lateral extensions than the word lines. Interspaces are filled with a dielectric material, and a mask is applied that partially covers the final sections and leaves contact areas in regions adjacent to the final sections and to the interspaces open. This mask is used to remove the dielectric material between the word line stacks. A second word line layer is applied and planarized to form second word lines between the first word lines, which have contact areas arranged in a staggered fashion to fan out like the final sections of the first word lines.

Abstract: A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ends of a cross bar of the T-shaped active region and a body contact region forms a leg of the T-shaped active region. A gate oxide layer is grown on the active region. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form a gate, where an end of the gate partially overlies the body contact region to complete formation of a Finfet device with body contact.

Abstract: A method of forming a thin gate insulator layer comprises forming an active region surrounded by STI regions; forming a first insulator layer on the active device region; forming a patterned photoresist layer over the first insulator layer and a at least a portion of the STI regions; etching the first insulator layer to expose a portion of the active device region, wherein the photoresist layer substantially protects the STI regions during etching; forming a thin gate insulator layer on the exposed portion of the active device region, wherein said first insulator layer located on a remaining portion of said active device region is converted to a thicker second insulator layer; and forming a conductive gate structure overlying a first portion of the thin gate insulator layer while a second portion of the thin gate insulator layer not covered by the conductive gate structure is removed.

Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).

Abstract: The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.

Abstract: Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer over the first stressed silicon nitride layer such that the sacrificial layer is thinner over substantially vertical surfaces than over substantially horizontal surfaces, forming a mask over a first one of the NFET and the PFET, removing the first stressed silicon nitride layer over a second one of the NFET and the PFET, and forming a second stressed silicon nitride layer over the second one of the NFET and the PFET. The sacrificial layer prevents undercutting and forming of an undesirable residual spacer during removal of the first-deposited stressed layer.

Abstract: Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.

Abstract: A CMOS imager with two adjacent pixel active area regions without the presence of an intervening trench isolation region that typically separates two adjacent pixels and their associated photodiodes is provided. The shared active area region isolates the two adjacent photodiodes and provides good substrate to surface pinned layer contact without the presence of n? type dopant ions and due to the presence of p-type dopant ions. As a result, the size of the imager can be reduced and the photodiodes of the two adjacent pixels have increased capacitance.

Abstract: An embedded capacitor structure in a circuit board and a method for fabricating the same are proposed. The circuit board is formed with a first circuit layer on at least one surface thereof, wherein the first circuit layer has at least one first electrode plate for the capacitor structure. Then, a dielectric layer is formed on the first circuit layer and made flush with the first circuit layer. The dielectric layer has a relatively low dielectric constant and good fluidity to effectively fill the spaces between patterned traces of the first circuit later. A capacitive material is deposited on the dielectric layer and the first circuit layer. Finally, a second circuit layer is formed on the capacitive material and has at least one second electrode plate corresponding to the first electrode plate, together with the capacitive material disposed in-between, to form the capacitor structure.

Abstract: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

Abstract: A method for manufacturing a capacitor is disclosed. An etch-stop layer or a polishing stop layer is employed to protect a storage electrode of the capacitor from being damaged by a chemical mechanical polishing process or an etch-back process during its fabrication.

Abstract: A transistor including a semiconductor substrate defined with an active region and a device isolation region, a gate formed on the semiconductor substrate, an insulating spacers formed on respective side walls of the gate, and source/drain junctions formed in the semiconductor substrate at opposite sides of the gate, the source/drain junctions having asymmetrical junction structures, respectively, wherein the gate has a lower portion arranged on the active region of the substrate, the lower gate portion having a stepped profile having a lower surface, an upper surface and a vertically-extending side surface. The invention also provides a method for manufacturing this transistor. In accordance with this transistor structure, an increase in the dopant concentration of a storage node is prevented. Accordingly, a reduction in the amount of leakage current is achieved, so that an improvement in the refresh characteristics of the transistor is achieved.

Abstract: The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.

Abstract: A method of forming an SPVG SONOS memory. First, a substrate having a well and a plurality of select gate structures is provided. Then, a plurality of sacrificial spacers are formed alongside each select gate structure, and an implantation process is performed to form a doped region in the well between any two adjacent select gate structures. Afterward, the sacrificial spacers are removed, and a composite dielectric layer is formed on the select gate structures and the substrate. Finally, a plurality of word lines are formed on the composite dielectric layer.

Abstract: A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, a second dielectric layer having a plurality of contact plugs is formed on the semiconductor structure, wherein the contact plug comprises a second dielectric layer and a first glue layer, furthermore; the first glue layer is placed on the side-wall and bottom of the contact plugs. In addition, the contact plugs filled with the first metal layer. Then, a second glue layer, a second metal layer and a pad layer having an opening pattern are respectively formed on the second dielectric layer and contact plug. Thus, the processes of the present invention can improve the stability and accuracy in the electricity of the mask ROM device.

Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle ? of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1(W2/T)<??tan?1(W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21). When the implant angle ? is controlled within that range, impurity ions (231, 232) are implanted into a second side surface (10A2) and a fifth side surface (10A5) through a silicon oxide film (13).

Abstract: The present invention relates to a thin film circuit board device having passive elements in wiring layers. The thin film circuit board device includes a base board (2) and a circuit part (3) including insulating layers (11) and (16) and pattern wiring (14) and (17) formed on a build-up forming surface (2a). On the first insulating layer (11), a receiving electrode part (21) is formed and the passive elements electrically connected to the receiving electrode part (21) are formed. In the circuit part (3), a substrate titanium film and a substrate film are laminated so as to cover the receiving electrode part (21) and the passive elements respectively. The substrate film and the substrate titanium film in areas in which a metallic film is not formed are etched through the metallic film serving as the first pattern wiring (14) formed on the substrate film as a mask. Thus, a substrate layer (23) and a substrate titanium layer (22) are formed.