Patents Issued in July 17, 2007
  • Patent number: 7244657
    Abstract: The present invention provides a zeolite sol which can be formed into a porous film that can be thinned to an intended thickness by a method used in the ordinary semiconductor process, that excels in dielectric properties, adhesion, film consistency and mechanical strength, and that can be easily thinned; a composition for film formation; a porous film and a method for forming the same; and a high-performing and highly reliable semiconductor device which contains this porous film inside. More specifically, the zeolite sol is prepared by hydrolyzing and decomposing a silane compound expressed by a general formula: Si(OR1)4 (wherein R1 represents a straight-chain or branched alkyl group having 1 to 4 carbons, and when there is more than one R1, the R1s can be independent and the same as or different from each other) in a conventional coating solution for forming a porous film in the presence of a structure-directing agent and a basic catalyst; and then by heating the silane compound at a temperature of 75° C.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: July 17, 2007
    Assignee: Shin-Etsu Chemical Co. Ltd.
    Inventors: Tsutomu Ogihara, Fujio Yagihashi, Hideo Nakagawa, Masaru Sasago
  • Patent number: 7244658
    Abstract: The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive stress STI films will generally exhibit a compressive stress of less than 180 MPa, and preferably less than about 170 MPa. In certain embodiment, the STI films of the invention will exhibit a compressive stress less than about 100 MPa. Further, in certain embodiments, the low compressive stress STI films of the invention will comprise between about 0.1 and 25 atomic % of the stress-lowering dopant.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: July 17, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Ellie Y Yieh, Lung-Tien Han, Anchuan Wang, Lin Zhang
  • Patent number: 7244659
    Abstract: Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller
  • Patent number: 7244660
    Abstract: A method for manufacturing a semiconductor component using a sacrificial masking structure. A semiconductor device is formed from a semiconductor substrate and a layer of dielectric material is formed over the semiconductor substrate and the semiconductor device. The layer of dielectric material may be formed directly on the semiconductor substrate or spaced apart from the semiconductor substrate by an interlayer. Posts or protrusions having sidewalls are formed from the layer of dielectric material. An electrically insulating material that is preferably different from the layer of dielectric material is formed adjacent the sidewalls of the posts. The electrically insulating material is planarized and the posts are removed to form openings that may expose a portion of the semiconductor device or a portion of the interlayer material. An electrically conductive material is formed in the openings.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: July 17, 2007
    Assignee: Spansion LLC
    Inventors: Kelley Kyle Higgins, Sr., Joseph William Wiseman
  • Patent number: 7244661
    Abstract: A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: July 17, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Cheng-Ming Yih, Huei-Huarng Chen, Hsuan-Ling Kao
  • Patent number: 7244662
    Abstract: A method for manufacturing a semiconductor integrated circuit includes steps of forming a semiconductor element on a semiconductor substrate and separating only a function layer including the semiconductor element, which is a surface layer of the semiconductor substrate, from the semiconductor substrate. The semiconductor element is preferably a compound semiconductor device including at least one of a light emitting diode, a vertical cavity surface emitting laserdiode, a photodiode, a high electron mobility transistor, an inductor, a capacitor, a resistor, and a heterojunction bipolar transistor.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: July 17, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Takayuki Kondo
  • Patent number: 7244663
    Abstract: A method of fabricating a thinned, reinforced semiconductor wafer is disclosed. Particularly, a semiconductor wafer may be provided and a plurality of separate semiconductor dice may be formed upon a surface thereof. At least one region of the semiconductor wafer may be thinned and at least one reinforcement structure for reinforcing the semiconductor wafer may be formed. A semiconductor wafer is disclosed comprising at least one thinned region and at least one reinforcement structure having a first portion and a second portion extending from respective thinned surfaces of the at least one thinned region. A method of designing a semiconductor wafer is disclosed wherein at least one region thereof is selected for thinning. Remaining unthinned regions of the semiconductor wafer may be selected for forming at least one reinforcement structure. At least one semiconductor die location may be selected within the at least one thinned region.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Kyle K. Kirby
  • Patent number: 7244664
    Abstract: The present invention provides, in one embodiment, a semiconductor wafer (100) dicing process. The dicing process comprises removing circuit features (120) from a street (115) located between dies (105) on a semiconductor substrate (102) using a first blade (135), such that the semiconductor substrate is exposed, and cutting through the exposed semiconductor substrate using a second blade (190). The first blade has a surface (140) coated with an abrasive material (145) comprising grit particles (150), having a median diameter (155) of at least about 25 microns. The grit particles are adhered to the first blade with a bonding agent (160) having a hardness of about 80 or less (Rockwell B Hardness scale). The grit particles have a concentration in the bonding agent ranging from about 25 to about 50 vol %. Another embodiment of the invention is a method of manufacturing a semiconductor device (200).
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: David B. Blair, Leon Stiborek
  • Patent number: 7244665
    Abstract: An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another embodiment, a wafer edge ring is formed with a spin coating apparatus provided with a wafer edge exposure (WEE) system. In further embodiments, a wafer edge ring is used to contain a liquid over a wafer active surface during a processing operation. In one embodiment, the wafer edge ring contains a liquid having a higher refractive index than air while exposing a photoresist on the wafer by immersion lithography. In another embodiment, the wafer edge ring contains a curable liquid material while forming a chip scale package (CSP) sealing layer on the wafer.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Peter A. Benson
  • Patent number: 7244666
    Abstract: For fabricating a multi-gate transistor, at least one active pattern having uniform critical dimension is formed. Epitaxy structures are grown from exposed portions of the active pattern. A channel region of the transistor is formed from at least two surfaces of the active pattern. Source and drain are formed using the epitaxy structures.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: July 17, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: You-Seung Jin
  • Patent number: 7244667
    Abstract: System for producing diffusion-inhibiting epitaxial semiconductor layers, by means of which thin diffusion-inhibiting, epitaxial semiconductor layers can be produced on large semiconductor substrates at a high throughput. The surfaces of the semiconductor substrates to be coated are first cleaned, and the substrates are then heated in a low pressure batch reactor to a first temperature (prebake temperature). The surfaces to be coated are next subjected to a hydrogen prebake operation at a first reactor pressure. In the next step the semiconductor substrates are heated in a low pressure hot or warm wall batch reactor to a second temperature (deposition temperature) lower than the first temperature, and after a condition of thermodynamic equilibrium is reached the diffusion-inhibiting semiconductor layers are deposited on the surfaces to be coated in a chemical gaseous deposition process (CVD) at a second reactor pressure higher than, equal to or lower than the first reactor pressure.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: July 17, 2007
    Inventors: Bernd Tillack, Dirk Wolansky, Georg Ritter, Thomas Grabolla
  • Patent number: 7244668
    Abstract: Methods for manufacturing semiconductor devices are disclosed. In one example, the semiconductor device has a gate and source/drain regions formed on a substrate. One example method includes introducing transition metal (Ti) source or precursor so that the introduced Ti source is chemisorbed onto the surface of the substrate and Ti mono-layer is formed; introducing semiconductor (Si) source so that the introduced Si source is chemisorbed onto the Ti mono-layer and Si mono-layer is formed; repeating the forming of the Ti and Si mono-layers; annealing the substrate to form a silicide layer (TiSi2) of C-54 phase; and patterning the C-54 phase TiSi2 layer to remain on the upper surfaces of the gate and source/drain regions.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 17, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Duk Soo Kim
  • Patent number: 7244669
    Abstract: A method for forming an organic or partly organic switching device, comprising: depositing layers of conducting, semiconducting, insulating, or surface modifying layers by solution processing and direct printing; and defining high-resolution patterns of these layers by exposure to a focused laser beam.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: July 17, 2007
    Assignee: Plastic Logic Limited
    Inventors: Henning Sirringhaus, Paul Alan Cain
  • Patent number: 7244670
    Abstract: A method and an apparatus for fabricating an integrated circuit entail directing a vapor flux toward a substrate surface from a plurality of directions associated with a plurality of azimuth angles, and selecting a deposition angle of the vapor flux, relative to a normal incidence, to obtain a substantially conformal film. The surface feature can be associated with, for example, one or more vias and/or one or more trenches.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: July 17, 2007
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Tansel Karabacak, Toh-Ming Lu, John Robert Barthel
  • Patent number: 7244671
    Abstract: Methods may be provided for forming an electronic device including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad. In particular, a conductive structure may be formed on the insulating layer and on the exposed portion of the conductive pad. The conductive structure may include a base layer of titanium-tungsten (TiW) and a conduction layer of at least one of aluminum and/or copper. Moreover, the base layer of the conductive structure may be between the conduction layer and the insulating layer. Related devices are also discussed.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: July 17, 2007
    Assignee: Unitive International Limited
    Inventors: J. Daniels Mis, Dean Zehnder
  • Patent number: 7244672
    Abstract: A method of selectively etching organosilicate layers in integrated circuit fabrication processes is disclosed. The organosilicate layers are selectively etched using a hydrogen-containing fluorocarbon gas. The hydrogen-containing fluorocarbon gas may be used to selectively etch an organosilicate layer formed on a silicon oxide stop etch layer when fabricating a damascene structure.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: July 17, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Huong Thanh Nguyen, Michael Scott Barnes, Li-Qun Xia, Mehul Naik
  • Patent number: 7244673
    Abstract: A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: July 17, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Hsiang Yao, Yih-Hsiung Lin, Tien-I Bao, Bi-Trong Chen, Yung-Cheng Lu
  • Patent number: 7244674
    Abstract: A method of forming a composite barrier layer comprising the following steps. A substrate having a dielectric layer formed thereover is provided. An opening exposing a first portion of the substrate is formed within the dielectric layer. A dielectric flash layer is formed within the opening and over the first exposed portion of the substrate. The dielectric flash layer lines the opening. The bottommost horizontal portion of the dielectric flash layer is removed to expose a second portion of the substrate. An aluminum layer is formed over the etched dielectric flash layer and over the second exposed portion of the substrate. A barrier metal layer is formed over the aluminum layer. The etched dielectric flash layer, the aluminum layer and the barrier metal layer comprise the composite barrier layer. A planarized metal plug is formed within the barrier metal layer lined opening.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: July 17, 2007
    Assignee: Agency for Science Technology and Research
    Inventors: Chaoyong Li, Siaw Suian Sabrina Su, Moitreyee Mukherjee-Roy, Ramana Murthy Badam
  • Patent number: 7244675
    Abstract: The present invention is to provide an electrical connection material through which an electrical connection via conductive particles can be performed reliably regardless of a little unevenness of an object. The electrical connection material is an electrical connection material 100 for electrically connecting an electrical connection portion of a first object 4 and an electrical connection portion of a second object 2. The electrical connection material 100 comprises a first film-like adhesive layer 6 which is a film-like adhesive layer arranged on the first object 4 and is composed of a plurality of conductive particles 7, a first binder 8 containing the conductive particles 7, and a first filler F1 and a second film-like adhesive layer 9 which is arranged on the first film-like adhesive layer 6 and is composed of a second binder 9A whose viscosity is lower than that of the first binder 8 and a second filler F2.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: July 17, 2007
    Assignee: Sony Corporation
    Inventors: Noriyuki Honda, Nobuhiro Hanai, Masakazu Nakada
  • Patent number: 7244676
    Abstract: The present invention provides a method for fabricating a semiconductor device capable of securing a bottom contact area of a storage node contact as well as of preventing losses of a bit line hard mask insulation layer. These effects are achieved by planarizing an inter-layer insulation layer, which is filled into etched portions formed between conductive patterns, with the bit line hard mask insulation layer through a CMP process. This planarization process decreases a thickness of an etch target to thereby provide more vertical etch profile compared to a typical etch profile that is tapered or inclined at a bottom contact area. As a result of the decreased thickness of the etch target and the more vertical etch profile, it is possible to obtain the wider bottom contact area and prevent losses of the bit line hard mask insulation layer.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: July 17, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Kwon Lee
  • Patent number: 7244677
    Abstract: A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: July 17, 2007
    Assignee: Semitool. Inc.
    Inventors: Thomas L. Ritzdorf, Lyndon W. Graham
  • Patent number: 7244678
    Abstract: A planarization method includes providing a second and/or third row Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes a complexing agent.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Rita J. Klein
  • Patent number: 7244679
    Abstract: Techiques for forming a silicon quantum dot, which can be applied to the formation of a semiconductor memory device, are disclosed. The techniques may include depositing a first dielectric layer on a semiconductor substrate, depositing a polysilicon layer on the first dielectric layer, forming a plurality of metal clusters on the polysilicon layer in regular distance, and etching the polysilicon layer using the plurality of metal clusters as a mask. As disclosed herein, it is possible to form the silicon quantum dots having the fineness and uniformity characteristic together with the single crystalline level characteristic.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: July 17, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kwan-Ju Koh
  • Patent number: 7244680
    Abstract: A method facilitates generally simultaneously fabricating a number of shallow trench isolation structures such that some selected ones of the shallow trench isolation structures have rounded corners and other selected ones of the shallow trench isolation structures do not have rounded corners. The method includes forming patterned photoresist over a hard mask so that portions of the hard mask are exposed over a portion of a cell region and over a portion of a periphery region, and then removing the exposed hard mask layer in the periphery region while removing a portion of the exposed hard mask layer in the cell region. A trench having rounded corners is then partially formed in the periphery region and more of the hard mask layer is removed in the cell region, before the trench in the periphery region is deepened while a trench in the cell region is formed.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: July 17, 2007
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsu-Sheng Yu
  • Patent number: 7244681
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Renee Zahorik, legal representative, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon, Russell C. Zahorik, deceased
  • Patent number: 7244682
    Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Niraj B. Rana
  • Patent number: 7244683
    Abstract: A method for processing substrates is provided. The method includes depositing and etching a low k dielectric layer on a substrate, pre-cleaning the substrate with a plasma, and depositing a barrier layer on the substrate. Pre-cleaning the substrate minimizes the diffusion of the barrier layer into the low k dielectric layer and/or enhances the deposition of the barrier layer.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: July 17, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Hua Chung, Nikolaos Bekiaris, Christophe Marcadal, Ling Chen
  • Patent number: 7244684
    Abstract: A thermal camouflage sheet for covering heat sources against identification in a thermal image, having a base textile with a glass filament, has a coating which contains aluminum powder on one side and has a coating which contains color pigments on the other side. The remission values of the color pigments are in a range which allows camouflaging in the visual-optical and near infrared. The coating which contains color pigments is in the form of a polyurethane coating or polyvinylidene fluoride coating.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: July 17, 2007
    Assignee: Texplorer GmbH
    Inventor: Gerd Hexels
  • Patent number: 7244685
    Abstract: A silicon carbide porous body of the present invention, comprising silicon carbide particles and metallic silicon bonded together in such a manner that pores are retained between the silicon carbide particles and/or between the silicon carbide particle and metallic silicon, wherein an oxide phase containing oxides of silicon, aluminum, and alkaline earth metal is buried in at least some of fine pore portions having a minimum distance of 10 ?m or less between the surfaces of the silicon carbide particles or between the surfaces of the silicon carbide particle and metallic silicon among the pores, and a ratio of a total volume of portions in which the oxide phase is not buried among the fine pore portions is 20% or less with respect to a total volume of portions in which the oxide phase is not buried among the pores including the fine pore portions.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: July 17, 2007
    Assignee: NGK Insulators, Ltd.
    Inventors: Masahiro Furukawa, Nobuyuki Tanahashi, Kenji Morimoto, Shinji Kawasaki
  • Patent number: 7244686
    Abstract: The present invention is directed to bearings produced from a silicon nitride material. The silicon nitride material consists of a sintering aid selected from the group consisting of Al2O3 and Y2O3, silicon dioxide, and optionally, up to 10 mole %, based on the amount of silicon nitride, of an additive that reacts with silicon nitride, said additive selected from the group consisting of TiO2, WO3, MoO3 and mixtures thereof.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: July 17, 2007
    Assignee: H.C. Starck Ceramics GmbH & Co. KG
    Inventors: Gerhard Wötting, Mathias Herrmann, Grit Michael, Stefan Siegel, Lutz Frassek
  • Patent number: 7244687
    Abstract: The invention relates to a composition for the production of a refractory ceramic moulded body, a non-fired or fired moulded body formed from the composition and a possibility for use.
    Type: Grant
    Filed: December 6, 2003
    Date of Patent: July 17, 2007
    Assignee: Refractory Intellectual Property GmbH & Co. KG
    Inventors: Johann Eder, Rainer Neuböck
  • Patent number: 7244688
    Abstract: The invention relates to heterogeneous catalysts which are particularly easy to produce. Said heterogeneous catalysts are generated by immobilizing preformed monometallic or multimetallic metal oxide particles in situ on an oxidic or non-oxidic carrier, wherefore metal oxide colloids which are stabilized by hydroxide ions and immobilized on carriers contained in the suspension are generated from conventional, water-soluble metal salts by means of hydrolysis and condensation. The inventive method makes it possible to produce fuel cell catalysts, for example.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: July 17, 2007
    Assignee: Studiengesellschaft Kohle mbH
    Inventors: Manfred T. Reetz, Marco Lopez
  • Patent number: 7244689
    Abstract: Alumina-silica catalyst supports having substantially high surfaces areas are formed by extrusion, drying and firing of a plasticized batch including an alumina-silica powder component, acid, organic binder and water. The alumina-silica powder component can be formed either by the mixing of alumina- and silica-source powders or by forming a slurry therefrom which is spray dried to form a particulate material prior to batching.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: July 17, 2007
    Assignee: Corning Incorporated
    Inventors: William P. Addiego, Kevin R. Brundage, Christopher R. Glose
  • Patent number: 7244690
    Abstract: It is an object of the invention to provide a thermal transfer image receiving sheet which can enhance sensitivity by low heat conductivity and can be easily manufactured at a low cost compared with the lamination of a foaming film. In a thermal transfer image receiving sheet 1 wherein a thermal insulation layer 5 and a dye receiving layer 8 are formed on a base material sheet 2, the thermal insulation layer 5 is formed by extrusion-molding a resin containing at least one of a foaming agent and hollow bodies. The resin extruded at the time of forming the thermal insulation layer 5 is inserted between the base material sheet 2 and the base material film 6, and the base material sheet 2 and the base material film 6 are bonded to each other via the thermal insulation layer 5. The dye receiving layer 8 is formed outside of the base material film 6.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: July 17, 2007
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Takenori Omata, Taro Suzuki, Masamitsu Suzuki, Yoji Orimo
  • Patent number: 7244691
    Abstract: A print assembly including a dye-donor element and a receiver element, wherein the print assembly has a donor having a dye-donor layer having a first glass transition temperature and at least one dye, and a receiver having a dye-receiving layer having a second glass transition temperature on a support, wherein the print assembly has a receiver/donor dye partition coefficient of at least 2.5 when the print assembly is heated above the higher of the first or second glass transition temperature for a time sufficient to achieve an equilibrium state of dye distribution between the dye-donor layer and dye-receiving layer. The print assembly can be used at fast print speeds of 2.0 msec/line or less.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: July 17, 2007
    Assignee: Eastman Kodak Company
    Inventors: Dennis J. Massa, Ramanuj Goswami, Walter H. Isaac, Christine J. Landry-Coltrain, David M. Teegarden
  • Patent number: 7244692
    Abstract: The invention relates to novel substituted benzoylcyclohexanediones of formula (I) in which A1 represents a single bond or represents alkanediyl (alkylene) having 1 to 3 carbon atoms, A2 represents alkanediyl (alkylene) having 1 to 3 carbon atoms, and R1, R2, R3, R4 and R5 are each as defined in the disclosure, and to novel intermediates, to processes for their preparation and to their use as herbicides.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: July 17, 2007
    Assignee: Bayer Aktiengesellschaft
    Inventors: Klaus-Helmut Müller, Hans-Georg Schwarz, Stefan Lehr, Otto Schallner, Dorothee Hoischen, Mark Wilhelm Drewes, Peter Dahmen, Dieter Feucht, Rolf Pontzen
  • Patent number: 7244693
    Abstract: A method for the treatment of a hydrocarbon well comprising administering down the well polymeric particles impregnated with a well treatment chemical or precursor or generator thereof. The particles have a pore volume of at least 20%, and are prepared by a process which comprises preparing an aqueous dispersion of polymer particles containing from 0.05 to 10 times by volume, based on the polymer, of one or more specific first material(s) adding a partly water-soluble second material having a water-solubility of at least ten times that of first material(s) under conditions which prevent or hinder transport of first material(s) through the aqueous phase, whereby second material diffuses into the polymer particles swelled with first material(s) and increases the volume of said particles by from 20 to 1000 times, based on the polymer.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: July 17, 2007
    Assignee: Statoil ASA
    Inventors: Hans Kristian Kotlar, Olav Martin Selle, Oddvar Arnfinn Aune, Lars Kilaas, Anne Dalager Dyrli
  • Patent number: 7244694
    Abstract: The present invention relates to viscoelastic fluids that contain nanotube structures that may be used advantageously as oilfield stimulation fluids in many different applications, most particularly as a fracturing fluid. Viscoelastic fluid compositions of the present invention include an aqueous medium, a viscoelastic surfactant, an organic or inorganic acids, or salt thereof, organic acid salts, inorganic salts, and a nanotube component. The invention is also called to a methods of treating a subterranean well bores in which the viscoelastic fluid is injected into the wellbore to perform operations such as fracturing, drilling, acid fracturing, gravel placement, removing scale, matrix acidizing, and removing mud cake. Further, a method of preparing a nanotube viscoelastic fluid comprising the steps of effectively mixing a carbon nanotube component into a viscoelastic fluid, and sonicating the mixture in order to incorporate the carbon nanotube component is claimed.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: July 17, 2007
    Assignee: Schlumberger Technology Corporation
    Inventors: Diankui Fu, Keith Dismuke, Stephen Davies, Ann Wattana
  • Patent number: 7244695
    Abstract: According to the invention there is provided a method of reducing wear of one or both of two steel elements having surfaces in sliding or sliding-rolling contact. The method involves applying an HPF friction control composition to one, or more than one contacting surface of one or both of the two steel elements. In a particular example, the HPF friction control composition comprises a rheological control agent, a lubricant, a friction modifier, and one, or more than one of a retentivity agent, an antioxidant, a consistency modifier, and a freezing point depressant.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: July 17, 2007
    Assignee: Kelsan Technologies Corp.
    Inventor: Don T. Eadie
  • Patent number: 7244696
    Abstract: An anti-seize composition which is non-flowable and dimensionally stable at temperatures greater than about 120° F. and dispensable at room temperature without the application of heat is provided. The composition includes a solid anti-seize lubricant, such as of metallic copper, metallic nickel, metallic aluminum, metallic lead, metallic zinc, graphite, calcium oxide, calcium carbonate, calcium fluoride, calcium stearate, lithium, molybdenum disulfide, boron nitride, barium sulfate, or combinations thereof. The anti-seize lubricant is dispersed in a carrier which is a solid at about room temperature. The carrier includes a grease with an ASTM D 217 penetration at 25° C. from about 200 to about 400 mm, a matrix material, and a naphthenic petroleum oil having a viscosity of less than about 300 SUS at 100° F. and having an API gravity at 60° F. from about 23 to about 25. The matrix material is a polymeric material. Optionally, a refined petroleum wax may also be included.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: July 17, 2007
    Assignee: Henkel Corporation
    Inventors: Prakash S. Patel, Shabbir Attarwala
  • Patent number: 7244697
    Abstract: AbtractProvided is a detergent composition comprising the following components (a), (b) and (c): (a) an anionic surfactant, (b) a water soluble cationized polymer having a weight average molecular weight of from 100,000 to 2,000,000 and a charge density of from 0.6 to 4 meq/g, and (c) a silicone derivative having a group containing both a hydroxy group and a nitrogen atom as a side chain thereof bonded to a silicon atom. The detergent composition provides rich foaming during washing and at the same time and is capable of giving excellent conditioning effects to the hair and the like.1 1.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: July 17, 2007
    Assignee: Kao Corporation
    Inventor: Eiji Terada
  • Patent number: 7244698
    Abstract: A viscoelastic surfactant composition having improved rheological performance comprising one or more quaternized amidoamine surfactants, one or more tertiary amine amides, one or more polymeric acids and one or more electrolytes, viscosified aqueous fluids comprising the surfactant composition and methods of making and using the viscosified aqueous fluid for treating subterranean formations.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: July 17, 2007
    Assignee: Nalco Company
    Inventors: Duane S. Treybig, Grahame N. Taylor, David Kelly Moss
  • Patent number: 7244699
    Abstract: A composition containing a silicone-containing polymer for cleaning fabric articles, especially articles of clothing, linen and drapery, with lipophilic fluid provides improved cleaning of soils while providing excellent garment care, especially for articles sensitive to water.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: July 17, 2007
    Assignee: The Procter & Gamble Company
    Inventors: John Christopher Deak, Eugene Paul Gosselink, Randall Thomas Reilman
  • Patent number: 7244700
    Abstract: An aqueous cleaning composition for the removal of mould and mildew is provided. The composition includes a water soluble source of chlorine, a surfactant, chitosan and water and has improved anti-fungal activity.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: July 17, 2007
    Assignee: Reckitt Benckiser (UK) Limited
    Inventor: Malcolm Tom McKechnie
  • Patent number: 7244701
    Abstract: Disclosed are a variety of peptide conjugates represented by the following general formula: R1-Z-X-Z?-R2 including methods of making and using such conjugates. Also provided are antibodies that specifically bind the peptide conjugates. The present invention has a wide spectrum of important applications including use in the treatment of disorders impacted by nociceptin and related opioid-like peptides.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: July 17, 2007
    Assignee: Zealand Phama A/S
    Inventors: Bjarne Due Larsen, Daniel R. Kapusta
  • Patent number: 7244702
    Abstract: The invention comprises a preparation of X-S-Cys-X, moiety, BRAUNMYCIN Î>>, where X maybe naturally linked peptide or glycan residues essential for iron-reductase activity, as well as methods of obtaining preparation from an iron-nitriloacetic acid iron binding jaw, BRAUNMYCIN8567, a component of a batch affinity column; and any interpretation derived from this outcome, like, but not limited to, detection of resistance, to iron-containing antibiotics, in DNA synthesizing cells.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: July 17, 2007
    Inventor: N. Robert Olisa, III
  • Patent number: 7244703
    Abstract: Compositions and methods for treating a patient with a pharmaceutically active peptide that combines a pharmaceutically active peptide, a permeation enhancer, and a carrier, are disclosed.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: July 17, 2007
    Assignee: Bentley Pharmaceuticals, Inc.
    Inventors: Robert J. Gyurik, Carl Reppucci
  • Patent number: 7244704
    Abstract: Compositions and methods of using compositions with a nuclear targeting peptide containing a nonclassical nuclear localization signal to deliver selected molecules to the nucleus of eukaryotic cells are provided. The compositions are particularly useful in gene transfer methods.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: July 17, 2007
    Assignee: Trustees of the University of Pennsylvania
    Inventor: Scott L. Diamond
  • Patent number: 7244705
    Abstract: Disclosed are derivatives of glycopeptides that are substituted at the C-terminus with a substituent that comprises two or more (e.g. 2, 3, 4, or 5) carboxy (CO2H) groups; and pharmaceutical compositions containing such glycopeptide derivatives. The disclosed glycopeptide derivatives are useful as antibacterial agents.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: July 17, 2007
    Assignee: Theravance, Inc.
    Inventors: Martin S. Linsell, J. Kevin Judice
  • Patent number: 7244706
    Abstract: The present invention provides a therapeutic method for treating or preventing a disease resulting from a microbial infection in an individual using an antimicrobial polypeptide. The present invention also provides a method of potentiating the therapeutic action of an antimicrobial drug in a patient. Further provided in the present invention are methods for neutralizing circulating endotoxin in a patient by administering the endotoxin-neutralizing polypeptide or functional variant thereof of the present invention to the patient.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: July 17, 2007
    Assignee: Agennix, Inc.
    Inventor: David M. Mann