Patents Issued in July 24, 2007
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Patent number: 7247922Abstract: An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current interrupters each extending into the substrate, wherein a first aggregate outer boundary of the plurality of current interrupters substantially encompasses a second aggregate outer boundary of the inductor coil.Type: GrantFiled: September 24, 2004Date of Patent: July 24, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Yeh, Alex Chang, Sung-Pi Tseng, Chang-Yun Chang, Hao-Yun Chen, Fu-Liang Yang
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Patent number: 7247923Abstract: A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.Type: GrantFiled: September 26, 2005Date of Patent: July 24, 2007Assignee: Fuji Electric Co., Ltd.Inventors: Kazuhiko Yoshida, Takeshi Ichimura, Tatsuhiko Fujihira, Naoki Kumagai
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Patent number: 7247924Abstract: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.Type: GrantFiled: October 28, 2003Date of Patent: July 24, 2007Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Joseph R. Greco, Richard S. Kontra, Emily Lanning
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Patent number: 7247925Abstract: A semiconductor device includes a semiconductor substrate of a first conductive type, a collector layer formed on the semiconductor substrate and made of a first semiconductor being of the first conductive type and having a higher resistance than that of the semiconductor substrate, an intrinsic base region having a junction surface with the collector layer and made of a second semiconductor of a second conductive type, and an emitter region having a junction surface with the intrinsic base region and made of a third semiconductor of the first conductive type. A periphery of the intrinsic base region is surrounded by an insulating region extending from the collector layer to the semiconductor substrate.Type: GrantFiled: September 24, 2004Date of Patent: July 24, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuyuki Toyoda, Shinichi Sonetaka
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Patent number: 7247926Abstract: A high-frequency switching transistor comprises a collector area, which has a first conductivity type, a first barrier area bordering on the collector area, which has a second conductivity type which differs from the first conductivity type, and a semiconductor area bordering on the first barrier area, which has a dopant concentration which is lower than a dopant concentration of the first barrier area. Further, the high-frequency switching transistor has a second barrier area bordering on the semiconductor area, which has a first conductivity type, as well as a base area bordering on the second barrier area, which has a second conductivity type. Additionally, the high-frequency switching transistor comprises a third barrier area bordering on the semiconductor area, which has the second conductivity type and a higher dopant concentration than the semiconductor area. Further, the high-frequency switching transistor has an emitter area bordering on the third barrier area, which has the first conductivity type.Type: GrantFiled: December 8, 2004Date of Patent: July 24, 2007Assignee: Infineon Technologies AGInventor: Reinhard Losehand
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Patent number: 7247927Abstract: A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The downset has an upward slope extending from the edge of the frame and levels off with the rest of the frame at a first transition point. The upward slope facilitates the upward flow of the molding compound entering from a bottom gate. Likewise, the leadframe also directs flow in a top gated mold by reversing the orientation of the leadframe or by forming a reverse downset on the leadframe.Type: GrantFiled: August 31, 2005Date of Patent: July 24, 2007Assignee: Micron Technology, Inc.Inventor: Stephen L. James
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Patent number: 7247928Abstract: Semiconductor device (1) and process for fabricating it, the device (1) including an electrical connection support plate (2), an integrated circuit chip placed at a certain location on the support plate (2) and placed at a certain distance from this support plate (2), a plurality of electrical connection balls connecting electrical connection regions (4) of the support plate (2) and corresponding electrical connection pads on the integrated circuit chip, and a fill material at least partly filling the space separating the chip from the plate, and in which the surface of the support plate (2), which has the electrical connection regions (4), is provided with an interlayer (6) made of an insulating material in which apertures (7) are provided above the electrical connection regions (4) and above complementary flow channels (9, 10).Type: GrantFiled: June 14, 2004Date of Patent: July 24, 2007Assignee: STMicroelectronics SAInventors: Patrick Laurent, Xavier Baraton
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Patent number: 7247929Abstract: A power element package includes a semiconductor chip, radiating members, a mold resin member, a lead terminal for control signals, and lead terminals for large electric current. On a heat accepting surface of the radiating member, an insulating layer and a conductive layer are disposed. The lead terminal for control signals is electrically connected with a gate of the semiconductor chip through the conductive layer. An emitter of the semiconductor chip is electrically connected through a solder connection member with a non-insulating portion of the heat accepting surface.Type: GrantFiled: March 25, 2004Date of Patent: July 24, 2007Assignee: DENSO CORPORATIONInventors: Shoji Miura, Yoshimi Nakase
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Patent number: 7247930Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.Type: GrantFiled: September 30, 2004Date of Patent: July 24, 2007Assignee: Intel CorporationInventors: Siva G. Narendra, James W. Tschantz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
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Patent number: 7247931Abstract: A leadframe for a semiconductor package is formed with an indentation on a bottom surface. A side of the indentation is used to form a mold-lock that assists in securing the leadframe to the encapsulation material of the semiconductor package.Type: GrantFiled: July 24, 2006Date of Patent: July 24, 2007Assignee: Semiconductor Components Industries, L.L.C.Inventors: Chuan Kiak Ng, Ein Sun Ng, Yeu Wen Lee
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Patent number: 7247932Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: GrantFiled: May 19, 2000Date of Patent: July 24, 2007Assignee: Megica CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Patent number: 7247933Abstract: A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (100) including a lead frame (10) having a plurality of leads (11) each having a down set portion (101) extending from (14). A semiconductor die (30) is disposed in a central region (12) of the lead frame (10) and is electrically connected (11). An encapsulant (50) is disposed in the central region (12) and covers to the semiconductor die (30) and a portion (11). The first surface (14) of the leads (11) and a first surface (34) of the semiconductor die (30) are substanial exposed from the encapsulant (50). The first surface (34) of the semiconductor die (30) and the down set portions (101) form a cavity (102).Type: GrantFiled: February 3, 2004Date of Patent: July 24, 2007Assignee: Advanced Interconnect Technologies LimitedInventors: Frank J. Juskey, Daniel K. Lau
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Patent number: 7247934Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.Type: GrantFiled: December 29, 2004Date of Patent: July 24, 2007Assignee: Siliconware Precision Industries Co., Ltd.Inventor: Han-Ping Pu
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Patent number: 7247935Abstract: A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical signal is suppressed a logic chip is directly connected to a DRAM, therefore, it is possible to suppress an increase of load capacitance caused by interconnects, and securing a wide bus width by a multiple pin connection. As a result, it becomes possible to enhance performance of the semiconductor device upon suppressing delay of information transmission from the logic chip to the DRAM.Type: GrantFiled: March 21, 2005Date of Patent: July 24, 2007Assignee: NEC Electronics CorporationInventor: Masaya Kawano
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Patent number: 7247936Abstract: A semiconductor chip package includes an IC chip and a tape circuit substrate. The tape circuit substrate has a base film and a plurality of beam leads formed on the base film. One end portion of each beam lead extends from the base film, and the extended portion has a widthwise wavy portion. The widthwise wavy portion may be, for example, semicircular shaped, S-shaped or zig-zag shaped. The IC chip has chip pads formed on a top surface thereof.Type: GrantFiled: December 17, 2003Date of Patent: July 24, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Woo Son, Jin-Hyuk Lee, Kwan-Jai Lee
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Patent number: 7247937Abstract: A chip package having a lead frame, a chip, a plurality of bonding wires, and an insulation material is provided. The lead frame comprises a die pad, a plurality of leads, a plurality of signal pads and a plurality of non-signal pads. The signal pads and non-signal pads are underneath the signal leads and non-signal leads respectively. The non-signal pad is directly connected to a non-signal plane in the circuit board through its own vias. The signal pad has a structure which extends toward its adjacent non-signal pads. With the signal pad size enlarged, the capacitance between the non-signal plane in the circuit board and the signal pad is increased. The increased capacitance compensates the inductance induced from the bonding wires and improves the response of the signal propagation path for RF applications.Type: GrantFiled: January 6, 2005Date of Patent: July 24, 2007Assignee: VIA Technologies, Inc.Inventors: Shin-Shing Jiang, Sheng-Yuan Lee
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Patent number: 7247938Abstract: The carrier (30) comprises a first etch mask (14), a first metal layer (11), an intermediate layer (12), a second metal layer (13) and a second etch mask (17). Both the first and the second etch mask (14, 17) can be provided in one step by means of electrochemical plating. After the first metal layer (11) and the intermediate layer (12) have been patterned through the first etch mask (14), an electric element (20) can be suitably attached to the carrier (30) using conductive means. In this patterning operation, the intermediate layer (12) is etched further so as to create underetching below the first metal layer (11). After the provision of an encapsulation (40), the second metal layer (13) is patterned through the second etch mask (17). In this manner, a solderable device (10) is obtained without a photolithographic step during the assembly process.Type: GrantFiled: April 10, 2003Date of Patent: July 24, 2007Assignee: NXP B.V.Inventors: Roelf Anco Jacob Groenhuis, Paul Dijkstra, Cornelis Gerardus Schriks, Peter Wilhelmus Maria Van De Water
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Patent number: 7247939Abstract: A method for forming a metal filled semiconductor feature with improved structural stability including a semiconductor wafer having an anisotropically etched opening formed through a plurality of dielectric insulating layers revealing a first etching resistant layer overlying a conductive area; a plurality of dielectric insulating layers sequentially stacked to have alternating etching rates to a preferential etching process; subjecting the anisotropically etched opening to the preferential etching process whereby the sidewalls of the anisotropically etched opening are preferentially etched to produce etched dielectric insulating layers to form roughened sidewall surfaces; anisotropically etching through the etching resistant layer to reveal the conductive area; and, filling the anisotropically etched opening with a metal to form a metal filled semiconductor feature.Type: GrantFiled: April 1, 2003Date of Patent: July 24, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chen Huang, Chao-Chen Chen
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Patent number: 7247940Abstract: An optoelectronic device, comprising a package body (57) and at least one semiconductor chip (50) arranged on the package body (57). The surface of the package body (57) has a metallized subregion (15) and a non-metallized subregion (20). The package body (57) includes at least two different plastics (53, 54), one of the plastics being non-metallizable (54) and this plastic determining the non-metallized subregion (20). A method for producing such components and a method for the patterned metallization of a plastic-containing body are also provided.Type: GrantFiled: March 1, 2004Date of Patent: July 24, 2007Assignee: Osram Opto Semiconductor GmbHInventors: Thomas Höfer, Herbert Brunner, Frank Möllmer, Günter Waitl, Rainer Sewald, Markus Zeiler
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Patent number: 7247941Abstract: A printed circuit board (PCB) assembly includes a PCB. An integrated circuit (IC) carrier defines a receiving zone to receive an IC. The carrier has a plurality of island portions about the receiving zone. Each island portion includes a solder member for contacting the PCB. A plurality of resilient serpentine members interconnect neighboring island portions so that at least some relative displacement of the PCB and the carrier is accommodated by the serpentine member, thereby alleviating strain imparted to the solder member.Type: GrantFiled: November 3, 2006Date of Patent: July 24, 2007Assignee: Silverbrook Research Pty LtdInventor: Kia Silverbrook
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Patent number: 7247942Abstract: The present invention provides a low cost device that has a true die to external fiber optic connection. Specifically, the present invention relates to an optical device package joined to a semiconductor device package. In some cases, the combination is joined using wirebond studs and an adhesive material. In other cases, the combination is joined using an anisotropic conductive film. Yet, in other cases, the combination is joined using solder material. Each of these joining mechanisms provides high levels of thermal, electrical and optical performance. The joining mechanisms can apply to optical sub-assembly and chip sub-assembly interfaces in transceivers, transmitters, as well as receivers for opto-electronic packages.Type: GrantFiled: December 15, 2004Date of Patent: July 24, 2007Assignee: National Semiconductor CorporationInventors: Luu Thanh Nguyen, Ken Pham, Peter Deane, William Paul Mazotti, Bruce Carlton Roberts, Jia Liu
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Patent number: 7247943Abstract: In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12) that has at least one aperture (13) through which a second contact pad (14) is electrically and mechanically connected to a first contact pad (9), wherein the second contact pad (14) is of a height of at least 15 ?m and projects laterally beyond the aperture (13) on all sides and is seated on the protective layer (12) by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 ?m and 15 ?m, and wherein at least one element of the signal-processing circuit (4), and preferably only one capacitor (5) of the signal-processing circuit (4), is provided opposite the first contact pad (9).Type: GrantFiled: October 31, 2003Date of Patent: July 24, 2007Assignee: NXP B.V.Inventor: Heimo Scheucher
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Patent number: 7247944Abstract: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternatively, a connector may contact a portion of the conductive trace to make contact therewith.Type: GrantFiled: April 5, 2005Date of Patent: July 24, 2007Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Patent number: 7247945Abstract: A semiconductor apparatus includes a printed circuit board, a peripheral type first semiconductor package which has a first group of ball electrodes arranged in a peripheral type first arrangement area and a first group of additional ball electrodes arranged inside the first arrangement area and which is arranged on a first surface of the printed circuit board, and a peripheral type second semiconductor package which has a second group of ball electrodes arranged in a second arrangement area and a second group of additional ball electrodes arranged inside the second arrangement area and which is arranged on a second surface of the printed circuit board. A ball electrode located at at least one corner of the first group of ball electrodes is arranged at a position to oppose a corner of the second arrangement area, and at least one ball electrode of the second group of ball electrodes is arranged at a position to oppose the second group of additional ball electrodes through the printed circuit board.Type: GrantFiled: December 13, 2005Date of Patent: July 24, 2007Assignee: Canon Kabushiki KaishaInventor: Yasuhiro Sawada
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Patent number: 7247946Abstract: Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.Type: GrantFiled: January 18, 2005Date of Patent: July 24, 2007Assignee: International Business Machines CorporationInventors: John Bruley, Roy A. Carruthers, Lynne Marie Gignac, Chao-Kun Hu, Eric Gerhard Liniger, Sandra Guy Malhotra, Stephen M. Rossnagel
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Patent number: 7247947Abstract: A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper layer insulating film is provided on the first semiconductor construct and insulating layer. Upper layer wiring lines are provided on the upper layer insulating film so that the upper layer wiring line is electrically connected to the external connection electrode. A second semiconductor construct is joined to and installed on connection pad portions. All jointing portions of the second semiconductor construct for the connection pad portions of the upper layer wiring lines are disposed in a region corresponding to the first semiconductor construct.Type: GrantFiled: September 20, 2006Date of Patent: July 24, 2007Assignee: Casio Computer Co., Ltd.Inventors: Takeshi Wakabayashi, Ichiro Mihara
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Patent number: 7247948Abstract: A semiconductor device has a semiconductor substrate, at least a first and second rewiring device on a first surface of the semiconductor substrate for the provision of an electrical contact-connection of the semiconductor substrate, and a tapering, continuous opening from a first surface to a second, opposite surface of the semiconductor substrate. At least a third and fourth rewiring device is disposed on the second surface of the semiconductor substrate and a patterned metallization on the side areas of the opening for the separate contact-connection of the first and at least the second rewiring device.Type: GrantFiled: April 30, 2004Date of Patent: July 24, 2007Assignee: Infineon Technologies AGInventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
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Patent number: 7247949Abstract: A method of manufacturing a semiconductor device which can solve a problem in which a wafer is warped by the influence of thermal contraction of a sealing resin due to a difference in thermal contraction between the wafer and the sealing resin. A second wafer on which electrodes are formed is stacked on a first wafer such that the electrodes of the second wafer are electrically connected to the electrodes formed on the first wafer, a portion between the first wafer and the second wafer is sealed with a resin, the second wafer and the sealing resin are half cut to expose the conductive posts from the sealing resin, conductive bumps for performing electric connection to an external circuit are formed on the exposed conductive posts, and the wafer is diced into independent semiconductor devices.Type: GrantFiled: December 30, 2004Date of Patent: July 24, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Hidenori Hasegawa
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Patent number: 7247950Abstract: A semiconductor device comprises a frame provided on a substrate to form a semiconductor-chip accommodating part on the substrate. A semiconductor chip is provided in the semiconductor-chip accommodating part. An organic insulating layer is provided to cover the semiconductor chip and the frame. A wiring layer is provided on the organic insulating layer. In the semiconductor device, the frame comprises gaps which are arranged in a longitudinal direction of the frame.Type: GrantFiled: November 5, 2004Date of Patent: July 24, 2007Assignee: Fujitsu LimitedInventors: Tetsuya Fujisawa, Masamitsu Ikumo
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Patent number: 7247951Abstract: A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by deploying a simple, fast film-coating technique. Therefore, there is no need to plate a Ni/Au layer on the bonding pads or contacts using expensive electroplating equipment for preventing oxidation and there is no need to fabricate plating lines on the chip carrier or reserve space for laying out the plating lines. Thus, the cost for fabricating the chip carrier is reduced, the effective area of the chip carrier is increased and the electrical performance of the chip carrier is improved.Type: GrantFiled: December 23, 2004Date of Patent: July 24, 2007Assignee: VIA Technologies, Inc.Inventors: Kwun-Yao Ho, Moriss Kung
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Patent number: 7247952Abstract: An optical target is provided. In one embodiment, the target is formed on a substrate. The target includes a first layer deposited below a second layer on the substrate. The second layer is deposited below a third layer on the substrate. The first layer has a topographic contour formed thereon, the first layer at least partially projecting a patterned topographical contour through the second layer to the third layer.Type: GrantFiled: October 30, 2003Date of Patent: July 24, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Simon Dodd, Michael D. Miller, Joseph M. Torgerson
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Patent number: 7247953Abstract: A system consisting of one or more satellites carrying photovoltaic panels that capture solar energy and convert it to electricity for storage and transmission to earth by a microwave energy beam. The earth station absorbs the microwave energy beam in a pressurized pool of water with an insulated dome cover. The dome cover allows the microwaves to enter but turns back the heat emanating from the pool. Succeeding microwave energy beams from the satellites heat the water which transfers the energy to another pool that is maintained in a constant boiling state to develop steam which drives a turbine that turns a generator and produces electric energy. The satellites follow a slightly off-polar orbit which assures their passing over large areas of the earth while at the same time following the earth's rotation assuring repeated passage over the same stations.Type: GrantFiled: July 6, 2006Date of Patent: July 24, 2007Inventor: Stanley Schmulewitz
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Patent number: 7247954Abstract: A portable ac power system for providing cordless remote electrical power. The portable ac power system includes a pair of portable power supply devices, and a recharging assembly. The pair of portable power supply devices each including a portable housing, an outlet, and an energy storage assembly, the outlet is designed for coupling with conventional electrical plugs. The recharging assembly is electrically couplable to a conventional household ac outlet. The recharging assembly is preferably electrically couplable to each one of the pair of portable power supply devices. The energy storage assembly is for recharging the portable power supply devices.Type: GrantFiled: January 23, 2004Date of Patent: July 24, 2007Inventor: Geraldine Dowdle
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Patent number: 7247955Abstract: A closed loop power converter circuit of a UPS or other power supply includes a pulse width modulator circuit in a forward path of the closed loop power circuit. A compensation circuit provides pulse width commands to the pulse width modulator at a first rate. A feedback circuit digitally filters samples of an output of the closed loop power converter at a second rate greater the first rate and that provides the filtered samples to the compensation circuit. In some embodiments, the compensation circuit may be operative to compensate for the phase lag associated with a low pass output filter.Type: GrantFiled: September 6, 2002Date of Patent: July 24, 2007Assignee: Eaton Power Quality CorporationInventors: John G. Tracy, Frederick Tassitino, Jr., Hans Pfitzer, Rennie Bobb, Julius Rice
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Patent number: 7247956Abstract: Performance Test Board for connecting at least one device under test (DUT) to a test system which has internal power supply sources (IPS) wherein said Performance Test Board (PTB) comprises at least one DC-DC-converter having an input terminal to which several internal power supply sources of said test system are connected in parallel, an output terminal to which a power supply terminal of said device under test (DUT) is connected and a control terminal to which a further internal power supply source of said test system is connected.Type: GrantFiled: November 30, 2004Date of Patent: July 24, 2007Assignee: Infineon Technologies AGInventors: Hartmut Berger, Kapil Gupta, Georg Eggers, Claus Peter, Hans-Joachim Kremer
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Patent number: 7247957Abstract: An electromagnetic transducer which may be driven as a linear electric motor (which may be a permanent magnet motor or a variable reluctance motor) in which coils disposed around first and second cores are positioned on opposite sides of a longitudinal plane in which the longitudinal axis of the armature lies. The transducer may be arranged to work as a generator.Type: GrantFiled: September 18, 2002Date of Patent: July 24, 2007Assignee: ISIS Innovation LimitedInventor: Michael William Dadd
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Patent number: 7247958Abstract: The invention prevents a temperature in an end portion of a stator iron core from becoming excessively high due to a heat generated in the end portion of the stator iron core of a turbine generator. In a dynamo-electric machine provided with a stator constituted by a stator iron core, a stator iron core pressing member and a stator coil, a rotor constituted by a rotor iron core, a rotor coil and a holding ring, and a baffle plate arranged in an inner diameter side of an end portion of the stator iron core and distributing a cooling medium cooling an inner side of the machine, the baffle plate is provided for forming a flow of the cooling medium along an inner periphery of the stator iron core pressing member and/or an inner peripheral surface of the end portion of the stator iron core.Type: GrantFiled: August 19, 2004Date of Patent: July 24, 2007Assignee: Hitachi, Ltd.Inventors: Kengo Iwashige, Hiroyuki Sato, Futoshi Hiyama, Takashi Karino, Takahiko Sano, Kenichi Toorisawa
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Patent number: 7247959Abstract: A dynamoelectric machine 30 includes a rotor 32 and a stator 34 surrounding the rotor. The dynamoelectric machine 30 further includes a generator housing 36 surrounding both the rotor 32 and the stator 34. Additionally, the dynamoelectric machine 30 includes at least one blower 39a, 39b for generating a cooling gas flow 38 within the generator housing 36 to cool the stator 34 and the rotor 32. The dynamoelectric machine 30 includes at least one arcuate heat exchanger 40a, 40b, 80a, 80b within the generator housing 36 for extracting heat from the cooling gas flow 38.Type: GrantFiled: October 11, 2002Date of Patent: July 24, 2007Assignee: Siemens Power Generation, Inc.Inventors: King Wai Chan, Homer Gay Hargrove
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Patent number: 7247960Abstract: A magnetic/encoder assembly has a compact design and combines the features of motor, encoder and chuck locating feature within a single motor housing. The motor/encoder includes a DC brushless motor with an inner magnetic rotor. The motor windings and the commutation electronics are mounted towards the bottom side of a printed circuit board. The rotor of the motor is extended above the surface of the printed circuit board. The extended rotor provides a precision seat for the magnetic wheel with multiple poles. The top surface of the printed circuit board mounts the sensor for the encoder. The extension of the rotor provides the precision mounting surface of the cartridge driving chuck.Type: GrantFiled: May 11, 2006Date of Patent: July 24, 2007Assignee: Quantum CorporationInventors: Ashok B. Nayak, Robert R. Heinze
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Patent number: 7247961Abstract: A magnetic/encoder assembly has a compact design and combines the features of motor, encoder and chuck locating feature within a single motor housing. The motor/encoder includes a DC brushless motor with an inner magnetic rotor. The motor windings and the commutation electronics are mounted towards the bottom side of a printed circuit board. The rotor of the motor is extended above the surface of the printed circuit board. The extended rotor provides a precision seat for the magnetic wheel with multiple poles. The top surface of the printed circuit board mounts the sensor for the encoder. The extension of the rotor provides the precision mounting surface of the cartridge driving chuck.Type: GrantFiled: May 11, 2006Date of Patent: July 24, 2007Assignee: Quantum CorporationInventors: Ashok B. Nayak, Robert R. Heinze
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Patent number: 7247962Abstract: A stator assembly (20) has a plurality of splayed stator poles (31-36). A first winding coil (51) is arranged on the first stator pole (31) between a first current rail (38) and the second current rail (40), the second winding coil (52) is arranged on the second stator pole (32) between the second current rail (40) rails and the third current rail (42), the third winding coil (53) is arranged on the third stator pole (33) between the third current rail (42) and the first current rail (38), the fourth winding coil (54) is arranged on the fourth stator pole (34) between the first current rail (38) and the second current rail (40), the fifth winding coil (55) is arranged on the fifth stator pole (35) between the second current rail (40) and the third current rail (42), and the sixth winding coil (56) is arranged on the sixth stator pole (36) between the third current rail (42) and the first current rail (38).Type: GrantFiled: December 6, 2002Date of Patent: July 24, 2007Assignee: emb-Papst St. Georgen GmbH & Co. KGInventor: Martin Burgbacher
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Patent number: 7247963Abstract: Because the bearing of an eccentric rotor is small, when it is integrated in a rotor by resin molding, the bearing unit can be fractured by impacts unless it has a sufficient mounting strength. Accordingly, an eccentric rotor is provided in which a sufficient mounting strength of the bearing on the rotor is ensured and the bearing unit is prevented from fracture by impacts. Also a vibration motor using the eccentric rotor is provided. The eccentric rotor includes a printed wiring board, a cylindrical bearing for insertion of a shaft, and a weight which are integrated to have a flat disk shape by resin molding. A shaft insertion hole has a diameter larger than the outer diameter of the shaft and smaller than the outer diameter of the bearing, and the bearing is integrated by resin molding in a state in which the entire periphery at the end portion thereof is disposed in contact with the printed wiring board around the insertion hole.Type: GrantFiled: November 16, 2004Date of Patent: July 24, 2007Assignee: Tokyo Parts Industrial Co., Ltd.Inventor: Katsuhito Sohara
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Patent number: 7247964Abstract: An electrical machine comprises a stator and a rotor. The rotor is adapted to magnetically interact with the stator to promote rotation of the rotor about an axis. The rotor includes a rotor core and a plurality of magnetized arcs supported by the rotor core. The plurality of magnetized arcs defines an outermost circumference. The rotor and the plurality of magnetized arcs include a first magnetized arc, a discontinuity disposed adjacent to the first magnetized arc along the outermost circumference, a second magnetized arc disposed adjacent to the discontinuity along the outermost circumference, and a magnetization pattern of alternating magnetic poles formed on the plurality of magnetized arcs. The magnetization pattern includes a first magnetic pole skewed with respect to a second magnetic pole to form an arc of magnetization skew.Type: GrantFiled: August 4, 2006Date of Patent: July 24, 2007Assignee: A.O. Smith CorporationInventors: Dan M. Ionel, Stephen J. Dellinger
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Patent number: 7247965Abstract: The invention relates to a rotor for an electric motor, especially an electric line-start motor, comprising spaces (4 to 7) which receive permanent magnets (10 to 13) and extend in an axial direction, and spaces (20 to 25) that accommodate conductor rods and extend in an axial direction. In order for the rotor to run as regularly as possible, the spaces (20 to 25) accommodating the conductor rods are provided with a substantially elongate cross-section in at least one sector of the rotor while being embodied in a curved manner along the longitudinal axis thereof in said sector when viewed from a cross-sectional perspective.Type: GrantFiled: December 12, 2003Date of Patent: July 24, 2007Assignee: Danfoss Compressors GmbHInventor: Niels Christian Weihrauch
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Patent number: 7247966Abstract: A generator includes a shaft and rotor body defining poles and a winding positioned around the shaft on the rotor body. A rotor pole crossover is aligned to the shaft and connects ends of the winding between adjacent poles. The rotor pole crossover includes a body member having a curved medial section and opposing legs extending outwardly from the curved medial section that connect to the ends of the winding. The curved medial section has at least one slot formed therein to add flexibility to the rotor pole crossover.Type: GrantFiled: June 24, 2004Date of Patent: July 24, 2007Assignee: Siemens Power Generation, Inc.Inventors: David Shore, Phillip Keaton
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Patent number: 7247967Abstract: An electric motor stator including a yoke having a plurality of yoke laminations. A body portion is formed as part of each of the plurality of yoke laminations. A first tooth is continuous with the body portion and is formed as part of at least a portion of the plurality of yoke laminations. The first tooth defines a first tooth profile. A first tooth attachment portion is formed as part of the plurality of yoke laminations. A second tooth includes a plurality of tooth laminations. Each tooth lamination of the second tooth includes a second tooth attachment portion and defines a second tooth profile that differs from the first tooth profile. The second tooth attachment portion is engaged with the first tooth attachment portion.Type: GrantFiled: August 9, 2004Date of Patent: July 24, 2007Assignee: A. O. Smith CorporationInventors: Dan M. Ionel, Stephen J. Dellinger, Alan E. Lesak
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Patent number: 7247968Abstract: Provided is a two-axis actuator having a large stage area. The two-axis actuator includes a stage moving in two directions and connected to an upper part of an inertial part. The two-axis actuator is configured to maximize a stage area relative to the overall area of the actuator, thereby increasing the data storage capacity of the stage.Type: GrantFiled: August 23, 2004Date of Patent: July 24, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-lock Baeck, Jong-up Jun, Ju-hwan Jung, Seung-bum Hong
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Patent number: 7247969Abstract: A surface acoustic wave device includes a three-dimensional substrate having an annular curved surface enabling to propagate a surface acoustic wave, and an electro-acoustic transducing element, which excites and propagates the surface wave along the surface, and receives the propagated surface wave. The substrate is made of a Li2B4O7, Bi12SiO20, LiNbO3, LiTaO3, or quartz crystal, and the element propagates the surface wave along a line of intersection between a crystal face of the crystal and the surface, and the line of intersection is defined as an outermost circumferential line of the surface. An environmental difference detecting apparatus uses the device having a plurality of propagating surface zones and compares surface acoustic wave reception signals of electro-acoustic transducing elements in the propagating surface zones of the device with each other, and detects an environmental difference in space portions with which the propagating surface zones come into contact.Type: GrantFiled: March 17, 2006Date of Patent: July 24, 2007Assignees: Toppan Printing Co., Ltd.Inventors: Noritaka Nakaso, Kazushi Yamanaka
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Patent number: 7247970Abstract: A frequency of a drive signal supplied to a piezoelectric element is swept within a specific range, a detection signal indicating the vibrating state of a vibrating member is detected, and the sweep speed of the drive signal frequency supplied to the piezoelectric element is controlled based on this detection signal. Thus, even if nonuniformities occur in the drive frequency of the piezoelectric element due to fluctuations in the surrounding temperature or the load, such nonuniformities can be overcome without any adjustments, and the piezoelectric element can be reliably driven. Also, since the sweep speed of the drive signal frequency is at a high speed when the vibrating member is in a non-drive state, needless drive signal output time during which the piezoelectric element cannot be driven can be reduced, needless power consumption can be curtailed, and nonuniformities in the drive speed of the driven object can also be reduced.Type: GrantFiled: July 1, 2005Date of Patent: July 24, 2007Assignee: Seiko Epson CorporationInventors: Jun Matsuzaki, Takashi Kawaguchi, Reiko Nagahama
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Patent number: 7247971Abstract: A piezoelectric motor for moving and positioning a load, the motor comprising: a piezoelectric vibrator having a plurality of electrodes and a coupling surface which is pressed to a load; and a power supply selectively operable to electrify at least one vibrator electrode with time varying voltage to generate vibrations in the coupling surface that step the load to a desired position or to electrify at least one vibrator electrode with DC voltage to displace the coupling surface and move thereby the load to a desired position, which DC voltage the power supply maintains to maintain the load at the desired position.Type: GrantFiled: July 23, 2003Date of Patent: July 24, 2007Assignee: Nanomotion LtdInventor: Ze'ev Ganor