Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.

Abstract: A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control circuit for controlling two differential outputs of the level shifter, and a post driver circuit driven by the two differential outputs of the level shifter, wherein the level shifter, the output control circuit, an the post driver circuit are operated under a high supply voltage, and wherein when the tri-state logic control module generates the inputs for putting the post driver circuit in a high impedance state, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors of the post driver circuit while isolating the level shifter from a high supply voltage.

Abstract: A current driver circuit includes a pull-down switch unit that is coupled between a node and a first reference potential and is operative to switch between an on-state and an off-state responsive to an input signal. A pull-up switch unit is coupled between the node and a second reference potential and is operative to switch between an on-state and an off-state, complementary to the pull-down switch unit. A turn-on speed of the pull-up switch unit is slower than that of the pull-down switch unit, and a turn-off speed of the pull-up switch unit is faster than that of the pull-down switch unit.

Abstract: The semiconductor device according to the present invention comprises an output MOS transistor M0, an MOS transistor M3 connected between a gate G1 of the output MOS transistor M0 and a ground voltage GND, a parasitic transistor Tr1 which is formed in parallel with the MOS transistor M3 with the substrate terminal of the MOS transistor M3 as a base, and a parasitic transistor control circuit for controlling the conducting status of the parasitic transistor Tr1 based on the power supply voltage Vcc.

Abstract: A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.

Abstract: Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply current while the IC is disabled. Further unwanted current flow can be avoided while the IC is disabled by providing a switch that is responsive to the enable input for selectively connecting and disconnecting the base of a reference voltage transistor to and from the transistor's grounded collector, which collector is defined by the substrate of the IC. Disconnection of the base from the grounded substrate/collector eliminates base current and thus prevents emitter-to-collector current flow through the transistor when the IC is disabled.

Abstract: A slicer with large input common mode range is provided. The slicer includes an input stage coupled to receive an input signal, a current source for providing current for the input stage, a self-biased load coupled to the input stage to provide an initial output signal, and an inverter for inverting the initial output signal to provide a final output signal. The input stage includes a first circuit including a plurality of transistors and a complimentary circuit including a plurality of transistors. When a low common mode input voltage causes the transistors of the first circuit to turn off, the transistors of the complimentary circuit will take over to accomplish the same task as the first circuit.

Abstract: A sample-hold circuit, which reduces droop and feed through and is suitable for high-speed operation while maintaining a wider freedom of design parameters, comprising a preamplifier to which an input analog signal is applied, a core section which outputs a voltage corresponding to the variation of an output from the preamplifier during the sampling period and holds the voltage corresponding to the output from the preamplifier during the hold period initiated by a transition of a clock signal, and a current switching circuit which is connected to the output pin of the preamplifier and enables the current flowing into the first transistor within the preamplifier during the sampling period to flow into another second transistor to apply a constant potential as an input to the core section.

Abstract: Systems and methods for decreasing transmission timing variations include precharging a data channel at a level before data is sent over the channel. The driver sets the level in response to the reception of a precharging control signal.

Abstract: A method, which is for determining switching state of a transistor-based switching device that includes a set of transistors, includes the steps of: applying a bias voltage to a transistor having a fastest response so as to dispose the transistors in the set in a desired transistor state; detecting a voltage level at a transistor having a slowest response to the bias voltage; and comparing the detected voltage level with a predetermined threshold voltage level in order to determine the switching state of the switching device. A transistor-based switching device is also disclosed.

Abstract: An internal reset signal generator that generates an internal reset disable signal after an internal high voltage device has been completely reset. This can substantially reduce errors in operation of semiconductor memory devices. A first circuit generates a first control signal until the power source voltage reaches a stabilized state and a second control signal thereafter. A delay circuit responds to the first and second control signals and a reset complete signal from a reset circuit, and generates an internal reset disable signal only when the second control signal and the reset completion signal are inputted simultaneously, and in other cases, generates an internal reset signal. A reset circuit is connected in a feedback circuit with the delay circuit. It resets a high-voltage device in response to the internal reset signal, and generates a reset completion signal when the high voltage device is reset.

Abstract: A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be caused by the leakage current, a leakage compensation circuit is provided. The leakage compensation circuit of a first embodiment replicates the leakage current using a replication capacitor and a current mirror. The voltage across the replication capacitor is proportional to the control voltage of a voltage-controlled oscillator of the compensating phase-locked loop. A second embodiment generates the compensation current by controlling the voltage on the gate of a transistor. The gate voltage depends on charge added and subtracted by a charge pump in addition to the charge pumps in the loop filter. A third embodiment applies a leakage compensation circuit to a delay locked loop.

Abstract: The invention discloses a delay locked loop which includes a coarse delay tuner circuit with edge suppressors suitable for use with delay locked loops (DLLs). The disclosed tuner circuit provides reduced lock time of the DLL circuit.

Abstract: In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to facilitate correct reading of the bit for the next clock cycle. If the bit on the line has been dynamic for the previous bits, the slew rate will be a lower slew rate to avoid crosstalk between neighboring lines.

Abstract: The invention relates to a method of establishing a PWM-modulated output signal representation (OS), providing a stream of parallelly determined intersection representations (PIR) on the basis of a stream of parallel reference signal representation (PRSR) and an input signal (IS), establishing a serial PWM output signal representation (OS) by transforming said stream of parallelly determined intersection representations (PIR) into a stream of serial intersection representations (SIR) by means of a relative time shift of at least one of said parallelly determined intersections (PIR). According to an embodiment of the invention, an advantageous way of providing intersection estimates has been obtained, as each or at least a number of intersection estimates between a reference signal and an input signal may be established partially while taking only the individual partial reference functions into consideration.

Abstract: A multi-threshold flip-flop includes a master latch, a slave latch, and at least one control switch. The master latch is composed of an input buffer formed with low threshold (LVT) transistors and a first latch circuit formed with LVT transistors. The slave latch is composed of a second latch circuit formed with high threshold (HVT) transistors and an output driver formed with LVT transistors. The at least one control switch enables or disables the LVT transistors and is implemented with at least one HVT transistor. The LVT and HVT transistors may be N-FETs and/or P-FETs. The multi-threshold flip-flop can operate at high speed, has low leakage current, and can save the logic state when disabled.

Abstract: A semiconductor device having a delay drift compensation circuit that compensates for a delay drift caused by temperature and voltage variations in a clock tree includes a clock driver having an output port, a first circuit having an input port, a first signal path between the output port of the clock driver and the input port of the first circuit and a first delay drift compensation circuit. The first delay drift compensation circuit, which is coupled with the first signal path, reduces a delay time of the first signal path when a power supply voltage increases, and increases the delay time of the first signal path when a temperature increases.

Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.

Abstract: The invention is a method and apparatus for supplying both positive and negative gate drive power supply potentials to the top switch, in a typical half-bridge semiconductor power topology, from the bottom switch gate drive power supplies and without the use of transformer, capacitive or optical isolation. A known method of providing the positive top switch gate drive supply is enhanced and used in conjunction with a new and novel method for providing the negative top switch gate drive supply. The negative top switch gate drive supply is provided by an additional, lower power semiconductor switch, which is substantially synchronized with the bottom semiconductor switch, except for a slight turn-on delay. When this additional switch is gated “on” and conducting, the negative bottom switch gate drive power is connected to the negative top switch gate drive supply energy storage capacitors.

Abstract: A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential VPP to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of VPP/2 and ground potential, a drain, and a gate. A second transistor has a source coupled to the drain of the first transistor, a drain coupled to the second node, and a gate. Programming circuitry is coupled to the gate of the first transistor and the gate of the second transistor and configured to in a programming mode apply a potential of either zero volts or VPP/2 to the gate of the first transistor and to apply a potential of VPP/2 to the gate of the second transistor. The first and second transistors have a BVDss rating of not more than about VPP/2.

Abstract: A bus driving device is provided with a driver circuit for driving a bus line thereof. The driver circuit includes an MOS transistor whose well is separated from other circuits. Further, the bus driving device is provided with a voltage control section for adjusting a well voltage, in accordance with a level of a signal in the bus line. With this bus driving device, a threshold voltage of the MOS transistor is set at a predetermined target value.

Abstract: A two-phase charge pump is provided that is controlled by first and second clock signals in phase-opposition. The charge pump has a sequence of cascade-connected stages. Each stage includes a capacitive element driven by one clock signal such that capacitive elements of adjacent stages are driven by different clock signals, a pass transistor that transfers electric charge to the capacitive element from the capacitive element of a previous stage, a first biasing circuit that enables the pass transistor during a first phase of the one clock signal, and a second biasing circuit that disables the pass transistor during a second phase of the one clock signal. Also provided is a two-phase charge pump having two branches that each include a sequence of such cascade-connected stages, with each stage of one branch having a corresponding stage in the other branch. A method of operating two-phase charge pumps is also provided.

Abstract: Voltage-activated and accurate current sink, and method of providing same. In one aspect, a circuit for accurately sinking current includes a zener diode coupled to a power source at the cathode of the zener diode, and first and second transistors, where the first transistor has its collector coupled to the power source and its base coupled to the cathode of the zener diode, and the second transistor has its base coupled to the anode of the zener diode and its emitter coupled to ground. A resistor is coupled between the emitter of the first transistor and the collector of the second transistor.

Abstract: An apparatus and method provide for curvature corrected temperature variations in a band-gap reference circuit. The apparatus includes a band-gap cell, an IPTAT circuit, a resistor, and a feedback circuit. The band-gap cell is arranged to provide a band-gap voltage. The resistor circuit is coupled to both the band-gap cell and the IPTAT circuit. The feedback circuit is arranged to selectively activate the IPTAT circuit such that an additional correction factor is added to the temperature response of the band-gap cell to provide a second order curve. The IPTAT circuit can be implemented as a simple transistor that is responsive to changes in absolute temperature.

Abstract: Disclosed herein is a circuit for generating reference current. The circuit for generating reference current comprises a current providing unit for generate a PTAT current, mirroring the PTAT current to generate an analogous PTAT current and generate an analogous BGR current, a current ratio control unit for generating an analogous BGR current in a first ratio, a PTAT current in a second ratio, and a current corresponding to the difference between the analogous PTAT current in the second ratio and the analogous BGR current in the first ratio, and a current increasing/decreasing unit for generating a BGR current in the first ratio.

Abstract: A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.

Abstract: Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of the present invention attempt to maintain the proper current ratio between reference and output supplies by adjusting the reference output of the current mirror. An existing reference voltage on the output side of the mirror can be used or a reference voltage can be created to be used for the voltage regulation of the reference side of the current mirror.

Abstract: For one or more disclosed methods, a supply voltage is supplied to an integrated circuit, the integrated circuit is placed in a test mode to select one of a plurality of reference voltage generators on the integrated circuit to supply to another voltage generator on the integrated circuit a reference voltage that is at least partially dependent on the supply voltage, and the integrated circuit is tested with the reference voltage supplied to the other voltage generator.

Abstract: A complex band-pass filter. The complex band-pass filter includes a band-pass filter coupled to a voltage source. The band-pass filter includes a first plurality of transconductors that receives a first voltage, where the first voltage controls the center frequency of the band-pass filter. The band-pass filter also includes a second plurality of transconductors, wherein the second plurality of transconductors receives a second voltage, where the second voltage controls the bandwidth of the band-pass filter. According to the system disclosed herein, the complex band-pass filter has automatic frequency tuning against process variations, a programmable center frequency, and a programmable bandwidth. Providing programmability to the center frequency (Fc) and bandwidth (BW) offers an alternative for multi-protected standards with different channels (Fc changes) and for time acquisition improvements (BS changes).

Abstract: An operational amplifier includes a current provider that introduces an additional current Ic to an internal node A of the operational amplifier for reducing the output offset voltage of the operational amplifier.

Abstract: A method and circuit for eliminating input voltage offset in an amplifier circuit are provided. An exemplary offset correction circuit is configured with DC restoration to eliminate the DC input voltage offset by suitably providing a correction voltage to correct an input voltage offset during operation of the amplifier circuit, without realizing recovery time problems associated with AC coupling. An exemplary offset correction circuit is configured with DC restoration and comprises a timing circuit, a sample and hold circuit, and a feedback circuit to provide a correction voltage signal to correct input voltage offset. The timing circuit is configured to determine a “dead time” and “live time” for operation of the amplifier circuit. During the “dead time” period the sample and hold circuit will sample a differential signal across the DC coupling and provide a feedback signal through feedback circuit to correct input offset voltage.

Abstract: A sampling differential amplifier for amplification of a signal having: a signal input (2) for application of an input signal to be amplified; signal amplification transistors (N1, N1) whose control connections are connected via sampling capacitors (CA, CA) to the signal input (2); with the signal amplification transistors (N1, N1) each being connected via series-connected load resistances (RL1, RL2) to a positive supply voltage (VDD) and via current source (N3) to a negative supply voltage (VSS); a signal output (3) for emitting an amplified output signal, with the signal output (3) being tapped off the signal amplification transistors (N1, N1); and having sampling switching transistors (N2, N2), which are each connected between the series-connected load resistances (RL1, RL2) and a control connection of one signal amplification transistor (N1, N1), with the control connection of the sampling switching transistors (N1, N1) being connected to a control signal input (13) for application of a sampling control s

Abstract: The present invention relates to a method of controlling a variable gain amplifier having at least one semiconductor switch, the amplifier having a first gain when the semiconductor switch is in a first steady state and a first gate voltage is applied to the semiconductor switch, and the amplifier having a second gain when the semiconductor switch is in a second steady state and a second gate voltage is applied to the semiconductor switch, whereby a sequence of third gate voltages is applied to the semiconductor switch to transition between the first and second gains.

Abstract: An amplifier includes a signal splitter operable to receive an input signal and generate at least first and second split signals, a first amplifier adapted to receive the first split signal and to generate a first amplified signal, and a second amplifier adapted to receive the second split signal and to generate a second amplified signal. A combining circuit is adapted to generate an output signal which is a sum of the first amplified signal and the second amplified signal. The amplifier further includes a phase control circuit arranged in a signal path of one of the first and second amplifiers, the phase control circuit comprising at least one thin film ferroelectric element. The amount of phase shift provided by the phase control circuit is selectively variable as a function of a control signal applied thereto.

Abstract: A power amplifier has an input conditioning circuit. At least first and second amplifiers are in parallel with each other and have inputs and outputs. An input signal is coupled to the inputs of the first and second amplifiers. A multi-input power combiner is provided. The outputs of the first and second parallel amplifiers are combined by the multi-input power combiner to add signals of the outputs constructively.

Abstract: Systems and methods are provided for efficient amplification of a signal utilizing a modified Doherty amplifier system. A modified Doherty amplifier system includes a nonlinear main amplifier and a nonlinear auxiliary amplifier. An impedance-inverting network separates the main amplifier from an associated load. A second quarter wave transmission line separates the auxiliary amplifier from an associated signal source. The signal source has an associated minimum signal power, such that the signal power never drops below a predetermined percentage of a peak signal power.

Abstract: A power amplifier with a multi-mode digital bias control circuit is provided. The power amplifier utilizes a complementary reference voltage generation circuit and a bias current-control circuit to generate a plurality of bias current levels for different output power levels. In an embodiment of the present invention, the power amplifier circuit is connected to a reference voltage and two control signals. Depending on the desired output power level, the control signals set the corresponding bias current in the amplifying transistors, to ensure sufficient linearity. The power amplifier is capable of operating at a very low quiescent current level, for example, 5 mA. As a result, a significant improvement in the power amplifier's overall efficiency is achieved, and the battery talk time of a wireless communication device is increased. The invention finds application in wireless communication devices such as CDMA, WCDMA, EDGE and WLAN mobile devices.

Abstract: A hybrid distortion compensation method and apparatus that greatly improves the capability to compensate for non-linear distortion due to a high frequency power amplifier over a wideband in strict conditions of smaller size and reduced power consumption. An adaptive pre-distortion section (14) and a feed forward distortion compensation circuit (30) are connected via a D/A converter (20), an A/D converter (28) and the like, and signals of parts of the feed forward distortion compensation circuit (30) are taken out using a switch circuit (SW), fed back to a digital signal processing system, and processed using highly accurate digital signal processing in a control-monitoring section (60). After an adjustment section (51) makes characteristics of two input signals of the feed forward distortion compensation circuit (30) coincide, feed forward distortion compensation is performed. A sequencer (80) controls the components sequentially.

Abstract: The invention generally relates to stabilizing an amplifier. In one aspect, a stabilization module that is in electrical communication with the amplifier is provided. The stabilization module includes both an open loop control system and a closed loop control system. The open loop control system is used to modify at least one characteristic of an input signal received by the stabilization module and to pass control to the closed loop control system. The closed loop control system is then used to modify the at least one characteristic of the input signal. The modified input signal is provided to the amplifier.

Abstract: In a contactless IC card system, a modulating circuit manufactured in an IC form is operable at a high power efficiency. The demodulating apparatus is configured to include: first signal output means for outputting a first output signal having a predetermined phase with respect to that of an input signal, a second signal output means for outputting a second output signal having a predetermined phase with respect to that of the input signal, gate means for gating at least the second output signal, calculation means for adding, or subtracting the first output signal and the second output signal; and control means for controlling the operation of the gate means in response to a logic level of input data.

Abstract: Differential amplifier includes a differential amplifier circuit, a bias circuit and an output circuit. The differential amplifier circuit includes first and second differential amplifier sections. The first differential amplifier section includes a first PMOS transistor which has a source connected with a power supply line, and a first pair of PMOS transistors which have sources connected with a drain of the first PMOS and gates respectively receiving first and second input voltages. The second differential amplifier section includes a first NMOS transistor which has a source connected with a ground line, and a second pair of NMOS transistors which have sources connected with a drain of the first NMOS and gates respectively receiving the first and second input voltages. The bias circuit activates one of the amplifier sections in response to a control signal. The output circuit outputs an output signal from an output of the activated differential amplifier section.

Abstract: Differential amplifiers comprise a differential input stage, first, second, third, and fourth fixed current sources, a first resistive element, and a current-folding element. Due to topology thereof, the differential amplifier converts the difference between the input voltages to the voltage difference between the source voltages of the transistors in the differential pair, and a current is induced through the first resistive element, thereby generating two currents. The current-folding element folds the two currents to generate output voltages.

Abstract: An operational transconductance amplifier includes a first amplifier circuit that generates a first bias. A second amplifier circuit receives the first bias and generates a feedback signal. The first amplifier circuit also receives the feedback signal. A Miller compensation circuit receives the feedback signal and generates a second bias. An Ahuja compensation circuit receives the first and second biases and the feedback signal and generates a third bias. The second amplifier circuit receives the third bias. A feedback loop has an open loop response with first and second poles and a zero that are located below a crossover frequency. The Miller compensation circuit increases a frequency difference between the first and second poles. The Miller compensation circuit also adjusts a frequency of one of the poles so that the zero cancels an effect of the pole on the open loop response.

Abstract: A radio frequency power amplifier module that brings sufficient attenuation to a radio frequency signal in a bias supply line connecting a bias control part and a radio frequency power amplifier part without increasing module substrate area is aimed. At least one bonding pad 106 having a capacitance component to a ground and stitch structure inductances 108, 109 composed of a bonding wire 105 provided via the bonding pad are provided in the bias supply line connecting the bias control part and the radio frequency power amplifier part.

Abstract: A broadcast transistor includes an amplifier transistor, and a negative feedback circuit connected to the amplifier transistor. A collector bias current in the amplifier transistor is switched to high and low within a range larger than a range of a current exhibiting the minimum noise figure, and the amount of feedback performed by the negative feedback circuit is changed in association with the switching of the collector bias current. When the collector bias current is switched to high, the amount of feedback becomes large; when the collector bias current is switched to low, the amount of feedback becomes small.

Abstract: A method and apparatus is described for controlling conduction between two nodes of an integrated circuit via a stack of FETs of common polarity, coupled in series. In an RF Power Amplifier (PA) having appropriate output filtering, or in a quad mixer, stacks of two or more FETs may be used to permit the use of increased voltages between the two nodes. Power control for such RF PAs may be effected by varying a bias voltage to one or more FETs of the stack. Stacks of three or more FETs may be employed to control conduction between any two nodes of an integrated circuit.

Abstract: The variable lock-in circuits basically include a sensor, triggering transistors, current mirror, current source, an N-bit triggering circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the triggering transistors, which provide a total current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor. Consequently, all variable lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.

Abstract: A clock circuit for outputting serial data without using a PLL is described. The clock is a VCO designed to start at a frequency that is slightly higher than necessary to preserve the data. The frequency of the clock is measured and if the frequency is too high or too low the DC control voltage for the VCO is changed to bring the VCO frequency back to the start frequency. Clock counters, holding registers, comparators, and a D/A form a feed back path around a VCO. In addition, a word boundary generator is used to define individual data words. The word boundary is formed by the absence of a bit clock transition while there is a data bit transition. A high/low threshold may be used where the VCO frequency, as measured, must transcend a threshold before the DC control voltage to the VCO is changed.

Abstract: Charge from a charge pump of a PLL is dumped to a loop filter of the PLL. The dumped charge is temporarily stored in a capacitor, between the charge pump and the loop filter. A voltage of the capacitor is shifted, while temporarily storing the dumped charge. Other embodiments are also described and claimed.