Abstract: A method of making an energy conversion device includes forming a plurality of pores within a substrate and forming a junction region within each of the plurality of pores. Each of the junction regions has a depletion region and each of the plurality of pores defines an opening size in the substrate and a spacing from adjacent pores so that the depletion regions of each of the pores is at least substantially in contact with the depletion region of the pores which are adjacent.

Abstract: A method for manufacturing an image sensor includes the steps of: providing a substrate having an upper surface and a lower surface; mounting a frame layer on the upper surface of the substrate to form a cavity together with the substrate; mounting a photosensitive chip, which is formed with a plurality of bonding pads, to the upper surface of the substrate, the photosensitive chip being located within the cavity; providing a plurality of wires to electrically connect the bonding pads of the photosensitive chip to the substrate; supplying an adhesive medium to the cavity; placing a transparent layer on the frame layer to cover the photosensitive chip so as to form the image sensor; and rotating the image sensor to make the adhesive medium be uniformly distributed over the upper surface of the substrate so that particles within the cavity are adhered to the adhesive medium.

Abstract: An imager, an image sensor included in the imager and a method of fabricating the image sensor are provided. The image sensor having a substrate with front and back sides to produce image data, includes a transparent conductive coating arranged on the back side of the substrate, a first well region of a first conductive type having first and second opposite sides, the first side being arranged adjacent with the front side of the image sensor; and a second well region of a second conductive type, different from the first conductive type and having a deep well region provided adjacent with the second side of the first well region, the transparent conductive coating configured to develop or to receive a first potential and the first well region configured to receive a second potential to substantially deplete a region between the transparent conductive coating and the first well region.

Abstract: The present invention provides a method of forming a transparent conductive film at a low temperature that is suitable for use with a synthetic resin substrate. According to the production method of a substrate with an electrode of the present invention, an oxide conductive film composed of an amorphous material or mainly composed of an amorphous material is formed on a substrate at a temperature equal to or less than the crystallization temperature of the film, and subsequently, the formed oxide conductive film is crystallized by heating. The oxide conductive film is processed into the shape of an electrode either before or after crystallization, according to necessity.

Abstract: In one embodiment a method is provided. The method comprises inserting a first end of a P-type semiconductor pin in a first through hole via in a substrate; inserting a first end of an N-type semiconductor pin in a second through hole via in the substrate; and electrically connecting the first ends of the P and N-type semiconductor pins to form a precursor Peltier cooling device which in cooperation with a semiconductor die, bridges the P and N-type semiconductor pins between their ends remote from the first ends to define a Peltier cooling device in the substrate.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a body having a contact surface spaced farther from the microelectronic component than a bond pad surface of the base. The bond wire couples the microelectronic component to a bond pad carried by the bond pad surface and has a maximum height outwardly from the microelectronic component that is no greater than the height of the contact surface from the microelectronic component.

Abstract: A method of fabricating a built-in chip type substrate containing a semiconductor chip is disclosed. The method comprises a first step of mounting the semiconductor chip on a substrate; a second step of forming chip connection wiring connected to the semiconductor chip mounted on the substrate; and a step of forming an alignment post on the substrate before the first step, the alignment post being used for positioning the chip connection wiring.

Abstract: A method of making an electronic package is described, wherein a substrate is provided with a pattern of conductive pads and a portion of solder positioned on selected ones of the pattern of copper pads. The solder is then reflowed to form partial hemispherically shaped caps on the selected copper pads. The partial hemispherically shaped caps are then coated with a solder flux. A thin semiconductor chip with a pattern of conductive elements, corresponding to partial hemispherically shaped capped pads, is then positioned on the substrate so that the conductive elements of the thin semiconductor chip substantially line up with the partial hemispherically shaped capped pads of the substrate. The solder is then heated to reflow temperature and an electrical couple is formed between the thin semiconductor chip and the substrate.

Abstract: A method of crystallizing amorphous silicon using a mask having a transmitting portion including a plurality of stripes, wherein end lines of at least two stripes are not collinear; and a blocking portion enclosing the plurality of stripes includes the steps of setting the mask over a substrate having an amorphous silicon layer, applying a first laser beam to a first area of the amorphous silicon layer through the mask, thereby forming a first crystallization region, moving the substrate in a first direction, thereby disposing the blocking portion of the mask over the first crystallization region, and applying a second laser beam to the first area of the amorphous silicon layer through the mask, thereby forming a second crystallization region.

Abstract: The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

Abstract: A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions.

Abstract: The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the trench; providing a first liner mask layer on the partial filling; providing a sacrificial filling on the liner mask layer to completely fill the trench; shallow etching back of the sacrificial filling into the trench; forming a first mask on the top side of the sacrificial filling in the trench; removing a subregion of the sacrificial filling in the trench using the first mask; and optionally removing a subregion of the first liner mask layer below it on the partial filling, the remaining subregion of the sacrificial filling in the trench serving as a second mask.

Abstract: A nonvolatile memory device and a method for fabricating the same is disclosed, to prevent a “smiling” phenomenon in an ONO layer, thereby improving the programming and erasing characteristics, reliability and yield. The device generally includes a semiconductor substrate; a gate insulating layer, a selection gate and a first insulating layer on the semiconductor substrate; an ONO layer formed on the semiconductor substrate including the selection gate; and a control gate formed on the ONO layer at least partially overlapping with the selection gate.

Abstract: Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: A method of fabricating a semiconductor storage cell that includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals. Spacer control gates are located in the trenches adjacent to the charge storage stacks on the trench sidewalls. The trench depth exceeds the spacer height so that a gap exists between a top of the spacers and the top of the substrate. A continuous select gate layer overlies the first trench. The gap facilitates ballistic programming of the DSEs adjacent to the gap by accelerating electrons traveling substantially perpendicular to the trench sidewalls. The storage cell may employ hot carrier injection programming to program a portion of the DSEs proximal to the source/drain regions.

Abstract: A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.

Abstract: A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced.

Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).

Abstract: A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.

Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

Abstract: In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region.

Abstract: A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

Abstract: A method and apparatus for packaging semiconductor devices using patterned laminate films to reduce stress buffering. The method includes fabricating a semiconductor die having thin film resistors and bond pads formed on an active surface. A film layer is formed onto the active surface of the die, covering the thin film resistors and bond pads. The film layer is then patterned to create recesses in the film layer in the vicinity of the bond pads on the active surface of the die. The die then undergoes wire bonding and is next encapsulated in a molding compound. The film layer between the film resister and the molding compound reduces stress buffering created by the molding compound.

Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

Abstract: An integrated circuit device structure (and methods). The structure includes a semiconductor substrate comprising a surface. A first doped polysilicon liner is defined within a first trench region formed on a first plug coupled to the surface of the substrate and a second doped polysilicon liner is defined within a second trench region on a second plug coupled to the surface of the substrate. The first trench region is separated from the second trench region by a predetermined dimension. The structure also has a first rugged polysilicon material overlying surfaces of the first doped polysilicon material within the first trench region and a second rugged polysilicon material overlying surfaces of the second doped polysilicon material in the second trench region. The first rugged polysilicon material is free from a possibility of electrical contact with the second rugged polysilicon material.

Abstract: Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.

Abstract: In preferred embodiments, a method of manufacturing a hybrid integrated circuit device is provided, in which a plurality of circuit substrates 10 are manufactured from a single metal substrate 10A? by dicing. In some embodiments, the method includes: preparing a metal substrate 10A? having an insulating layer 11 formed on the top surface thereof; forming a plurality of conductive patterns 12 on the top surface of insulating layer 11; forming grooves 20 in lattice form on the rear surface of metal substrate 10B?; mounting hybrid integrated circuits onto conductive patterns 12; and separating individual circuit substrates 10 with, for example, a rotatable cutter.

Abstract: A MEMs (microelectromechanical systems) structure is provided. In one implementation, the MEMs structure includes a substrate wafer including a MEMs device formed on a surface of the substrate wafer, and a MEMs cover structure to cover the MEMs device formed on the surface of the substrate wafer. The MEMs cover structure comprises a first wafer bonded to a second wafer, in which only the first wafer of the MEMs cover structure is sawed through and not the second wafer of the MEMs cover structure during dicing of the MEMs structure.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, which comprises a first surface on which an electrode pad is formed, and a second surface arranged at an opposite side of the first surface; an external terminal formed on the first surface of the semiconductor substrate and is electrically connected to the electrode pad; and a sealing resin which seals the first surface so that a surface of the external terminal is exposed. An outer edge of the second surface has a chamfered portion, a surface of which is inclined by substantially 45 degrees from the second surface.

Abstract: A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can be arranged on the first surface of the substrate body; and a plate member, a rigidity thereof being higher than that of the substrate body, attached to the second surface of the substrate body. A plurality of semiconductor elements can be mounted on the semiconductor element mounting surface defined on the first surface of the substrate body.

Abstract: A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.

Abstract: A manufacturing method for producing a stained silicon wafer has the steps of forming an Si1-xGex composition-graded layer of which Ge concentration is stepwisely increased on a single crystal silicon substrate, forming an Si1-xGex uniform composition layer of which Ge concentration is constant on the Si1-xGex composition-graded layer, forming a stain-relaxed Si1-yGey layer of which Ge concentration y is constant while y satisfies relationship of 0.5x?y<x on the Si1-xGex uniform composition layer and epitaxially growing a strained Si layer on the strain-relaxed Si1-yGey layer.

Abstract: The present invention is directed to a wafer device method for processing same. A wafer for epitaxial deposition is backside sealed with a dopant seal layer (protection layer comprised of silicon dioxide or silicon nitride. Then, a layer of polysilicon is formed coextensively over the dopant seal layer. The polysilicon layer acts as a seed layer for potentially nodule forming gasses present during epitaxial deposition. During CVD epitaxy, the epitaxial layer is deposited on the primary surface with optimal resistivity uniformity. The fugitive gasses from the epitaxial process which diffuse to the wafer periphery and backside deposit as a film on the seed layer instead of in nodules. The polysilicon layer acts as a continuous seed layer which eliminates the preferential deposition at seal layer pinholes or island seed sites.

Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.

Abstract: A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.

Abstract: Disclosed is a method for forming a bonding pad of a semiconductor device. The present invention provides a method for forming a bonding pad of a semiconductor device comprising the steps of: (a) forming a top metal line having a predetermined width on a structure of a semiconductor substrate; (b) forming an insulating layer on the top metal line and the structure of the semiconductor substrate; (c) selectively etching the insulating layer to form a bonding pad which exposes portions of the top metal line; (d) performing a plasma treatment over the semiconductor substrate by using CF4, Ar, and O2 gas.

Abstract: A method for forming a solder bump structure with increased height. A substrate having at least one metal bonding pad thereon is provided. A passivation layer is formed on the substrate, which substantially exposes the metal bonding pad. An under ball metallurgy (UBM) layer is formed on the exposed metal bonding pad. A dielectric layer and a resist layer are successively formed on the passivation layer, wherein the dielectric layer has a first opening to expose the UBM layer and the resist layer a second opening over the first opening. A solder bump is formed on the UBM layer in the first and second openings, and the resist layer is then removed.

Abstract: Aligning metal fill shapes with corresponding holes of a metal shield is provided. The holes of the metal shield are laid out corresponding to a pre-selected grid referenced to a pre-selected origin. The metal fill shapes of the metal fill pattern, are arranged in accordance with the same pre-selected grid and referenced to the same pre-selected origin. Accordingly, regardless of the size or spacing of the metal fill holes, a metal fill shape will substantially align with a corresponding metal fill hole. Such alignment between metallization levels and the structure of the metal shield and metal fill shape pattern enhance the electric noise blocking properties of the metal shield in conjunction with the metal fill shape.

Abstract: Semiconductor devices with composite etch stop layers and methods of fabrication thereof. An semiconductor device with a composite etch stop layer includes a substrate having a conductive member, a first etch stop layer on the substrate and the conductive member, a second etch stop layer and a dielectric layer sequentially over the second etch stop layer, having a conductive layer therein down through the dielectric layer, the second etch stop layer and the first etch stop layer to the conductive member.

Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

Abstract: Some embodiments of the present invention include fabricating carbon nanotube bundles with controlled length, diameter, and metallic contacts.

Abstract: An ALD method includes exposing a substrate to a first precursor including a plurality of different ligands, chemisorbing a precursor monolayer on the substrate, and reacting a second precursor with the precursor monolayer to yield a product monolayer. A surface reactive ligand exhibits a chemisorption affinity that exceeds the chemisorption affinity exhibited by a gas reactive ligand. Another deposition method includes exposing a substrate to a precursor containing an amino and/or imino ligand and a halide ligand and depositing a layer. The precursor exhibits a volatility that exceeds the volatility with a halide ligand taking the place of each amino and/or imino ligand. The precursor exhibits a thermal stability that exceeds the thermal stability with an amino and/or imino ligand taking the place of each halide ligand. The layer may exhibit less halogen content than with a halide ligand taking the place of each amino and/or imino ligand.

Abstract: The present invention provides a method for manufacturing a semiconductor wafer capable of manufacturing a wafer without ring-like sag in an outer peripheral portion thereof when polishing an alkali etched wafer, and a wafer without the ring-like sag in an outer peripheral portion thereof. The present invention comprises: a back surface part polishing and edge polishing step for performing back surface part polishing and edge polishing such that mirror polishing is performed on a chamfered portion and an inner part extending inward from a boundary between the chamfered portion and a back surface of a starting wafer; and a front surface polishing step for mirror polishing a front surface of the wafer subjected to the back surface part polishing and edge polishing step holding the wafer by the back surface thereof.

Abstract: Provided are a metal-polishing liquid that comprises an oxidizing agent, an oxidized-metal etchant, a protective film-forming agent, a dissolution promoter for the protective film-forming agent, and water; a method for producing it; and a polishing method of using it. Also provided are materials for the metal-polishing liquid, which include an oxidized-metal etchant, a protective film-forming agent, and a dissolution promoter for the protective film-forming agent.

Abstract: A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness for a subsequent CMP step and lowers the dielectric constant. There is no loss of H2O or CH4 during the He treatment. The low k dielectric layer is then treated with a H2 plasma which converts some of the Si—O and Si—CH3 bonds near the surface to Si—H bonds, thereby further lowering the dielectric constant and increasing thermal stability that improves breakdown resistance. Moisture uptake is also reduced. The method is especially useful for interconnect schemes with deep sub-micron ground rules. Surprisingly, the k value obtained from two different plasma treatments is lower than when two He treatments or two H2 treatment are performed.

Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.

Abstract: A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t* is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tlot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).