Abstract: The present invention relates to a fingerprints detection apparatus by a capacitance detection method. The fingerprints detection apparatus of the present invention includes a sensor portion in which an insulating protection film is formed so as to cover detection electrodes arranged like an array, and the detection electrodes and the wiring beneath the detection electrodes are formed of a refractory metal or a compound of the refractory metal. This structure heightens the Vickers hardness of the detection electrodes and the wiring. This makes it possible to provide a highly reliable fingerprints detection apparatus in which a tolerance to cracks of the insulating protection film in the sensor portion is improved.

Abstract: Microfluidic devices and methods that use electrical admittance as the basis for measuring flow rate of fluids and/or for distinguishing (e.g., characterizing, sorting, separation, etc.) different particles, chemical compositions or biospecies (e.g., different cells, cells containing different substances, different particles, different chemical compositions, etc.).

Abstract: Aspects of the invention relate to a system for assessing the condition of a thermal barrier coating on a turbine vane during engine operation. According to embodiments of the invention, one or more wires can be passed along the airfoil portion of the vane. The wires can extend over, within, or beneath the thermal coating. An electrical current can be passed along the wires, and electrical resistance can be measured across the wires. Thus, if a portion of the thermal coating becomes damaged, then the wires located in that area may break. A disconnect in the wires can lead to an increase in resistance across the wires, which can alert an operator to a problem. Some assessment systems can provide a general indication of the magnitude of damage and whether the damage is spreading.

Abstract: A device for measuring a resistance includes a comparator. A D-type flip-flop has its D input connected to the output of the comparator and its latch input connected for receiving a pulse signal at a fixed pulse repetition rate. A reference voltage source is connected to a first of the inputs of the comparator and an integrator is coupled between an output of the flip-flop and the second of the two inputs of the comparator. The integrator includes a resistor whereby the integrator develops a voltage at the second input of the comparator that depends on the pulse repetition rate and on the resistance of the resistor. The comparator, the integrator and the flip-flop are connected in a negative feedback loop such that at steady state the voltage developed by the integrator at the second input of the comparator is substantially equal to the reference voltage.

Abstract: Wafer-level testing is performed on an electronic device to be used in an optical communications system. An optical test signal is generated and is provided to a first photo detector. An electrical output of the first photo detector is supplied to the electronic device on the wafer. An electrical output from the electronic device on the wafer is used to drive a light source. An optical output of the light source is supplied to a second photo detector and an electrical signal output from the second photo detector is examined.

Abstract: A probe assembly suitable for making test measurements using test signals having high currents. The disclosed probe assembly provides for a test signal exhibiting relatively low inductance when compared to existing probe assemblies by preferably reducing the electrical path distance between the test instrumentation and the electrical device being tested.

Abstract: A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers.

Abstract: A circuit board inspection device for inspecting the operation of a circuit board having a predetermined part or wire formed therein includes a supporting substrate disposed substantially in parallel with the parts mounting surface of the circuit board, and a signal change detection unit made of a coil or a capacitor disposed in a position of the supporting substrate corresponding to the part or wire of the circuit board, with the supporting substrate being disposed substantially in parallel with the circuit board.

Abstract: A method of testing circuit boards, in particular non-componented circuit boards in which the level of the surface of a circuit board to be tested is detected automatically in a contacting process, and the further contacting operations are then controlled on the basis of the level detected. By this process, the control of the movement of the test probes of the finger tester effects automatic matching to the level, which is of particular advantage in the testing of flexible circuit boards, since their surface may have a three-dimensional form.

Abstract: A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.

Abstract: A hard disk drive system includes an external interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. The hard disk drive system includes a system on chip (SOC) that includes a controller and a read/write channel that communicates with the controller and that includes an integrated system test (IST) module that communicates with the external interface. A memory module communicates with the SOC and includes memory and an IST module. The hard disk drive system includes a spindle/voice coil motor driver module that includes an IST module. At least one of the IST modules is a master IST module that receives the test configuration data and that configures the IST modules for testing at least one of the controller, the read/write channel, and the memory module.

Abstract: A detection unit 1 for detecting an electric field or a magnetic field is placed above a circuit board 4 to be detected. A control device 3 allows the detection unit 4 to carry out detection processes while moving the detection unit 1 in a predetermined direction with an electric current being applied to the circuit board 4 so that an electric field distribution or a magnetic field distribution on the circuit board 4 is detected. Moreover, the control device 3 compares the results of the detection with reference data that has been preliminarily registered, and if there is any portion between the two pieces of data that is not coincident with each other, it is determined that the corresponding circuit board 4 is a defective circuit board. Thus, it is possible to detect any defective portion on the printed circuit board with high precision in a non-contact state to the circuit board.

Abstract: A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the robustness of the design when used in a TMR mode of operation. Various addressing schemes are provided, which allow dual use of the configuration data lines as selection signals using one addressing scheme, while allowing for dual use of the configuration address lines as selection signals using the second addressing scheme.

Abstract: A digital audio system on a chip includes a plurality of general purpose input/output (GPIO) modules operably coupled to the bus. Each of the plurality of GPIO modules includes a plurality of GPIO cells, wherein a GPIO cell of the plurality of GPIO cells is coupled to a pin of the digital audio SOC. A first GPIO module of the plurality of GPIO modules functions, in a first mode, as an input/output for system management and functions, in a second mode, as an output. A second GPIO module of the plurality of GPIO modules functions, in a first mode, as an I2C input/output, and functions, in a second mode, as an input/output.

Abstract: A shift register includes a plurality of stages each generating an output signal in sequence and including a buffering section, a driving section, a first charging section, and a charging control section. The buffering section receives one of a scan start signal and an output signal of a previous stage so that the driving section generates the output signal of a present stage. The first charging section includes a first terminal electrically connected to the driving section and a second terminal electrically connected to a first source voltage. The charging control section applies the output signal of a next stage to the first charging section. Therefore, a gradual failure of TFT is reduced.

Abstract: Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS logic gate includes a delayed enable clock transistor coupled to a source region of at least two input transistors. The dynamic pseudo-pMOS logic gate includes a delayed enable clock transistor coupled to a drain of at least two input transistors. None of the logic input devices are connected in series.

Abstract: An electronic circuit for providing a logic gate function includes a differential signal input, a combining stage, a discriminating stage and a differential signal output. The discriminating stage includes four transistors each having first electrodes and second electrodes and a respective gate electrode. The first electrodes of the four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of the four transistors respectively.

Abstract: Current feedback amplifiers circuits that generate common mode (CM) and/or differential mode (DM) currents are provided herein. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: In general, the embodiments introduce a pre-charge state between an idle state (when no data in being transmitted) and an active state (when data is being transmitted). In the pre-charge state, both differential signals are pre-charged to the common mode voltage, which is also the crossover voltage. Similarly, an additional pre-charge state is inserted between the active state and the idle state when the signals transition from active to idle. Because both signals for each bit, including the first and last bits, are being driven from the same voltage level, the quality of the first and last bits are improved to be similar in quality to the middle bits.

Abstract: A low voltage differential signaling (LVDS) driving apparatus is disclosed, which comprises an LVDS output circuit to output an LVDS differential signal; a switch circuit coupled to the LVDS output circuit to control the phase of the LVDS differential signal; and a reference current control circuit to provide a control voltage to the LVDS output circuit such that the magnitude of the LVDS differential signal is determined based on the control voltage.

Abstract: A voltage source converter with a line-side diode rectifier, a load-side inverter with an electronic circuit, a power supply for the electronic circuit, and a slim DC link with a DC link capacitor is described. The slim DC link connects a DC output side of the line-side diode rectifier with a DC input side of the load-side inverter. A buffer capacitor is connected across the power supply, and a decoupling diode and a current limiting circuit are electrically connected in series with the buffer capacitor. The serially connected buffer capacitor, decoupling diode and current limiting circuit are connected in parallel with the DC link capacitor. This arrangement results in a voltage source converter that has an improved service reliability even in unstable power grids, without adding circuit complexity to the line input.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: The present invention provides an event edge synchronization system and a method of operating the same. In one embodiment, the event edge synchronization system includes: (1) a first clock zone device configured to generate an event signal based upon a first clock rate, (2) a second clock zone device configured to operate at a second clock rate, which is asynchronous with the first clock rate and (3) a synchronous notification subsystem configured to receive the event signal, synchronize the event signal to the second clock rate based upon an edge transition of the event signal and the second clock rate, and generate a synchronous notification signal therefrom.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: A semiconductor device with a blind scheme for boosting an internal voltage using an external supply voltage is disclosed. The semiconductor device includes a voltage detector for detecting a voltage level of the external supply voltage being applied to the semiconductor device, a pulse generator for being controlled by a logic level value output from the voltage detector and generating a pulse signal having a variable pulse width, an internal voltage generator for generating the internal voltage for driving an internal circuit of the semiconductor device, and a driving unit for providing the external supply voltage to an output terminal of the internal voltage generator that outputs the internal voltage in response to the pulse signal.

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract: Embodiments of the invention provide methods and apparatuses for restoring a duty cycle of a complementary output signal pair. In one embodiment, the output signal pair is brought in phase with a complementary input signal pair by delaying a complementary intermediate signal pair from which the output signal pair is generated. The intermediate signal pair is switched to a first logic state in response to detecting a crossing point between rising and falling signals of the output signal pair. The intermediate signal pair is switched to a second logic state in response to detecting a crossing point between rising and falling signals of the input signal pair.

Abstract: A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.

Abstract: A circuit includes: a PLL circuit which multiplies a reference clock by a multiplication factor and outputs a PLL clock; a first counter which counts up with the PLL clock for a fixed period of time; a comparator which compares a count value of the first counter with the multiplication factor; a second counter which counts up the number of times the comparison values have been matched for the fixed period of time; and an output unit which generates an enable signal when a count value of the second counter reaches the number of times the circuit waits for stability, and opens a gate to transmit the PLL clock in response to the enable signal.

Abstract: A switch includes at least two signal ports in series with a series FET connected therebetween, and a shunt path having an FET, whereby an input bias is applied to a gate on the series FET and to a drain on the shunt FET. In one embodiment, the switch includes a control signal input, an FET connected in series across the first port and the second port, the series FET having a gate coupled to the control signal input, and a shunt path provided by an FET, the shunt FET having a drain coupled to the control signal input and to the gate of the series FET, whereby a single control signal is applied to both the series FET and the shunt FET, via the control signal input, in order to turn the series FET on and simultaneously turn the shunt FET off and, conversely, in order to turn the series FET off and simultaneously turn the shunt FET on.

Abstract: A multiplexer circuit includes a plurality of switched differential amplifier circuits, one of which can be selected at a time. Each switched differential amplifier includes a pair of differential inputs and a pair of differential outputs, with each pair of differential inputs accepting a corresponding pair of input signals. Each of the switched differential amplifier circuits is configured to present a current mode version of its input signals at its differential outputs when the switched differential amplifier circuit is selected, and to present substantially zero level output signals at its differential outputs when the switched differential amplifier circuit is deselected. The multiplexer circuit also includes a selector that accepts a select signal and selects one of the plurality of switched differential amplifier circuits based on said select signal. A current mirror is used to combine a pair of multiplexer outputs into a single ended output, a version of which is used for feedback.

Abstract: An apparatus and method for generating an output signal that tracks the temperature coefficient of a light source are provided. A light source temperature coefficient tracking mechanism (e.g., a current source circuit) that generates an output signal, which tracks the temperature coefficient of the light source (e.g., temperature coefficient of a light emitting diode (LED)) is provided. A proportional to absolute temperature current source circuit (PTAT current source circuit) generates a first signal. A complimentary to absolute temperature current source circuit (CTAT current source circuit) generates a second signal. The output signal that tracks the temperature coefficient of the light source is based on the first signal and the second signal.

Abstract: The leakage current output by a MOS transistor is minimized by varying a back bias voltage across a range of voltages, and detecting the back bias voltage within the range that minimizes the leakage current output by the MOS transistor. The detected back bias voltage is then applied to the MOS transistor.

Abstract: A differential charge pump circuit has two current paths and generates a differential current in accordance with currents inputted to the two current paths. The two current paths have a pair of current sources respectively and form a differential pair. The differential charge pump circuit has controlling means for detecting an output potential difference between the two current paths and controlling current values of the current sources in accordance with the output potential difference.

Abstract: The present invention provides a boosted voltage generator of a semiconductor device where a boosted voltage efficiency and drivability at a target boosted voltage level can be evaluated accurately by employing an enable signal generator. The boosted voltage generator includes a boosted voltage pad; a level detection means for detecting whether or not a present boosted voltage reaches a target boosted voltage level; an oscillation means for performing an oscillation mode in response to a signal outputted from the level detection means; a charge pumping means for outputting a level-controlled boosted voltage in response to a signal outputted from the oscillation means; and an enable signal generation means for operating the oscillation means in response to a signal outputted from the level detection means.

Abstract: A multi-mode charge pump drive circuit has a multi-mode charge pump, a switch control circuit, a current regulation circuit, an error amplifier, a variable resistance unit, and a mode selection circuit. The multi-mode charge pump is operated with a plurality of modes, each of which provides a different multiplicative ratio for converting an input voltage source into a drive voltage. The switch control circuit applies a switch control signal to the multi-mode charge pump. The switch control signal has a slew rate of edge for determining a transition span of the interchange between charging and discharging phases. The mode selection circuit controls the multi-mode charge pump to selectively operate with one of the plurality of modes. When the mode selection circuit changes the mode of the multi-mode charge pump, the mode selection circuit applies a mode change signal to the switch control circuit so as to reduce the slew rate of edge.

Abstract: The present invention provides an internal voltage generator for maintaining a voltage level of an internal voltage by forcibly discharging an over-supplied voltage. The internal voltage generator includes a reference voltage generator for outputting at least one reference voltage with a predetermined voltage level after receiving an external voltage; a level shifter for outputting an internal reference voltage with a shifted voltage level by receiving the reference voltage of the reference voltage generator; a driver for outputting an internal voltage by using the internal reference voltage; and a discharging unit for forcibly discharging an over-supplied voltage of the internal voltage by a release pulse signal.

Abstract: An integrated circuit current regulator that compensates for variation in current required based on the switching activity of the integrated circuit. A first embodiment incorporates a voltage controlled on-chip bypass circuit with a scaling unit to divide an input voltage into n fractional voltages and an on-chip voltage monitor to compare a fraction of the on-chip supply voltage with a reference voltage and control a corresponding on-chip power supply bypass. At least one bypass resistor per comparator is switched between the supply voltage and ground potential according to the output signal of the corresponding comparator to dampen power supply noise. The value of the by-pass resistance R increases with decreasing on-chip supply voltage and decreases with increasing supply voltage.

Abstract: An amplifier circuit includes a first amplifier and a second amplifier and sets of switching devices controlled by a bistate control signal. The bistate control signal is in the first state to cause the first and second sets of switching devices to configure the first amplifier and the second amplifier in a positive parallel configuration and the bistate control signal is in the second state to cause the first and second sets of switching devices to configure the first amplifier and the second amplifier in a negative parallel configuration. When the bistate control signal switches states at each sample cycle of the amplifier circuit, the first amplifier and the second amplifier toggle between the positive parallel configuration and the negative parallel configurations to cancel out crosstalk signals stored at the positive and negative input terminals of the first and second amplifier circuit.

Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).

Abstract: An apparatus and a system, as well as a method and an article, may include detecting an indication of an amplifier output signal amplitude and responsively adjusting the amplifier input signal phase to reduce a change in the phase of the output signal.

Abstract: Methods and apparatus are provided for efficiently combining and filtering a plurality of input signals into a single combined output signal. M number of input signals are received, combined and filtered by a filter/combiner. The filter/combiner has a plurality of input stages for each input signal, and an output stage that combines the outputs of the input stages into the combined signal. The filter/combiner has a desired overall filter transfer function designed to filter signals having frequencies outside a passband and which passes the desired M input signals.

Abstract: A linear power efficient radio frequency (RF) driver system (100) includes a pre-driver amplifier (105) for amplifying an RF signal; and an output driver (107) having a substantially high impedance input for amplifying the signal from the pre-driver amplifier (105). A bias controller (109) is used for controlling the RF power output of the output driver (107) where the current drain of the pre-driver amplifier (105) and the bias controller (109) are controlled to a minimum level while maintaining linearity of the output driver (107). The system and method of the invention work to provide minimal current drain in portable products using simultaneous current and power amplifier reduction based on driver input swing to lower signal distortion.

Abstract: A RFPA (radio frequency power amplifier) circuit (150) which includes a RFPA (101), a supply voltage source (104), means (155) for applying to the RFPA a gain control bias voltage and a feedback control loop (156) for adjusting a voltage applied to the RFPA, the feedback control loop including a sampler (107) for sampling an output of the RFPA, a RF detector (109) for detecting a level of RF power sampled by the sampler, a comparator (115) for comparing an output signal from the RF detector with a reference signal, an integrator (117) for integrating an output signal of the comparator and a voltage regulator (151) having a first input from the integrator and a second input from the supply voltage source and an output connected to the RFPA, the regulator being operable to apply to the RFPA a supply voltage adjusted in response to an input signal from the integrator.

Abstract: An input tracking current mirror for a differential amplifier system includes a current mirror having an input leg and an output leg, a differential amplifier including a first set of at least two transconductance components, each having at least one input terminal for receiving input signals, the first set of at least two transconductance components having a first common node connected to the output leg which has a first voltage that is a function of the input signals, and a tracking circuit including a second set of at least two transconductance components each having at least one input terminal for receiving the input signals, the second set of at least two transconductance components, having a second common node connected to the input leg which has a second voltage that is a function of the input signals, the tracking circuit driving the second voltage on the input leg to track the first voltage on the output leg with variations in the input signals.

Abstract: Methods of and apparatus for distributing power and biasing RF PAs. A power distribution network includes a pre-final amplifier stage power distribution network and a final amplifier stage power distribution network. The pre-final amplifier stage power distribution network includes one or more pre-final amplifier stage power distribution branches, which may be configured to distribute power from one or more pre-final amplifier power supplies to one or more pre-final amplifier stages. Each pre-final amplifier stage power distribution branch comprises a ? C-R-C network coupled to an inductive load. A final amplifier stage power distribution network is configured to distribute power from a final amplifier stage power supply to a final stage of the amplifier circuit.

Abstract: A semiconductor integrated circuit capable of performing internal oscillation with high precision is provided. The semiconductor integrated circuit has a memory circuit, an oscillator circuit for generating an internal clock signal based on control information held in the memory circuit, a logic circuit for generating control information for causing the frequency of the internal clock signal to coincide with the frequency of an external clock signal, and an electric fuse circuit or a blow fuse circuit capable of storing the control information generated in the logic circuit and uses the internal clock signal for the synchronous operation of the internal circuit.

Abstract: An oscillator circuit and a method of generating an oscillating signal are disclosed. An oscillator comprises a first flip-flop and a second flip-flop coupled with the first flip-flop to provide an oscillating signal. A method of generating an oscillating signal comprises providing the oscillating signal as a first clock input to a first flip flop, inverting the oscillating signal and providing the inverted oscillating signal as a second clock input to a second flip flop, using the output of the first flip flop and the output of the second flip flop to generate a combined output that alternates between a logic low level and a logic high level, and using the combined output to sustain the oscillation of the oscillating signal.

Abstract: The phase locked loop (PLL) frequency synthesizer includes a phase detector receiving a reference signal, a controlled oscillator (e.g. a voltage controlled oscillator) connected to the phase detector and generating a synthesized frequency output signal based upon the reference signal, a mixer (e.g. an in-phase and quadrature-phase (IQ) modulator) connected to the controlled oscillator, a divider connected between the mixer and the phase detector, and a signal source driving the mixer. The frequency synthesizer and method have narrow frequency steps (e.g. as low as fractions of a Hertz) while using a relatively high reference frequency to maintain low phase noise. Furthermore, the fine frequency tuning resolution is achieved while also reducing output spurs and using a relatively simple topology.