Abstract: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for v= 5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we show how to manipulate the collective state of two e/4-charge anti-dots in order to switch said collective state from one carrying trivial SU(2) charge, |1>, to one carrying a fermionic SU(2) charge |?>. This is a NOT gate on the {|1>, |?>} qubit and is effected by braiding of an electrically charged quasi particle ? which carries an additional SU(2)-charge. Read-out is accomplished by ?-particle interferometry.

Abstract: An electronic device containing a polythiophene wherein R represents a side chain, m represents the number of R substituents; A is a divalent linkage; x, y and z represent, respectively, the number of Rm substituted thienylenes, unsubstituted thienylenes, and divalent linkages A, respectively, in the monomer segment subject to z being 0 or 1, and n represents the number of repeating monomer segments in the polymer or the degree of polymerization.

Abstract: A calibration structure for probing devices.

Abstract: A semiconductor device can include a channel including a gallium oxide film.

Abstract: The invention includes SOI constructions containing one or more memory cells which include a transistor and a thyristor. In one aspect, a scalable GLTRAM cell provides DRAM-like density and SRAM-like performance. The memory cell includes an access transistor and a gated-lateral thyristor integrally formed above the access transistor. The cathode region (n+) of the stacked lateral thyristor device (p+/n/p/n+) is physically and electrically connected to one of the source/drain regions of the FET to act as the storage node for the memory cell. The FET transistor can include an active region which extends into a Si/Ge material. The material comprising Si/Ge can have a relaxed crystalline lattice, and a layer having a strained crystalline lattice can be between the material having the relaxed crystalline lattice and the transistor gate. The device construction can be formed over a versatile substrate base.

Abstract: A semiconductor device having two thin film transistors where cross-talk is minimized and a flat panel display device having the same.

Abstract: The present invention is directed to electronic devices comprising high-purity molybdenum oxide in at least a part of the devices. The devices according to the present such a bipolar transistor, a field effect transistor and a thyristor have a high withstand voltage. The present invention is directed also hostile-environment electron devices formed using high-purity molybdenum oxide. The devices according the present invention can be fabricated at a relatively lower temperature such as 700° C. than that at which GaN or SiC devices are fabricated, the at is a temperature higher than 1000° C.

Abstract: A semiconductor laser device including: semiconductor layers including an n-type semiconductor layer, an active layer and a p-type semiconductor layer, the semiconductor layers having a stripe-shaped waveguide region formed therein; end face protective film formed on the end face of the semiconductor layer that is substantially perpendicular to the waveguide region; wherein a p-side protruding portion is formed in the vicinity of the end portion of a p-electrode or n-electrode.

Abstract: An electronic device includes a radiation-emitting component, a radiation-responsive component, or a combination thereof. In one embodiment, the electronic device includes a substrate and a first structure overlying the substrate. The electronic device also includes a second structure that includes a first layer, wherein the first layer has a first refractive index, and the first layer includes a first edge. The electronic device further includes a second layer overlying at least portions of the first structure and the second structure at the first edge. The second layer has a second refractive index that is lower than the first refractive index. In another embodiment, the first structure includes a layer having a perimeter and a pattern lying within the perimeter. The pattern extends at least partly though the first layer to define an opening with a first edge. In another embodiment, a process is used to form the electronic device.

Abstract: A gallium nitride-based light emitting device, and a method for manufacturing the same are disclosed. The light emitting device comprises an n-type GaN-based clad layer, an active layer, a p-type GaN-based clad layer and a p-side electrode sequentially stacked on a substrate. The device further comprises an n-side electrode formed on one region of the n-type GaN-based clad layer, and two or more MIM type tunnel junctions formed on the other regions of the n-type GaN-based clad layer. Each of the MIM type tunnel junctions comprises a lower metal layer formed on the GaN-based clad layer so as to contact the n-type GaN-based clad layer, an insulating film formed on the lower metal layer, and an upper metal layer formed on the insulating film. The device is protected from reverse ESD voltage, so that tolerance to reverse ESD voltage can be enhanced, thereby improving reliability of the device.

Abstract: Light-emitting devices capable of preventing separation or alteration of a first electrode to obtain high performance, methods of manufacturing the light-emitting device, and display units are provided. A first electrode as an anode, an insulating film, an organic layer including a light-emitting layer, and a second electrode as a cathode are laminated in this order on a substrate with a planarizing layer as a base layer in between. The first electrode has a structure in which an adhesive layer, a reflective layer and a barrier layer is laminated in this order from the substrate. Alteration of the reflective layer can be prevented by the barrier layer, and the reflective layer can be prevented from being separated from the planarizing layer by the adhesive layer. The first electrode is formed through forming the adhesive layer, the reflective layer and the barrier layer on the planarizing layer, and then patterning them in order from the barrier layer.

Abstract: In an epitaxial structure of a solid state lighting system, electrical current injection into the active layer is used to excite the photon emission. The present invention employs a unique waveguide layer in the epitaxial structure for trapping the light generated by the active layer in the fundamental waveguide mode. Multiple photonic crystal regions located either outside or inside one or more current injection regions extract photons from the waveguide layer(s). This novel design optimizes the interplay of electrical pumping, radiation and optical extraction to increase the optical output to several times that of conventional LEDs. A transparent and conductive ITO layer is added to the surface of an epitaxial structure to reduce the interface reflection in addition to functioning as a current spreading layer. The present invention creates solid state lighting with high optical output and high power efficiency.

Abstract: A display apparatus includes an array of fiber-type semiconductor light-emitting elements. Each of the fiber-type semiconductor light-emitting elements includes a layered structure having a first electrode layer, a second electrode layer, and a semiconductor light-emitting layer at least part of which is sandwiched by the first and second electrode layers, and a fiber for supporting the layered structure and for propagating light emitted from the light-emitting layer. The display apparatus also includes driving connectors including a switching element or a plurality of first and second conductive lines, which are electrically connected to the first and second electrode layers, respectively, for driving the plurality of the fiber-type semiconductor light-emitting elements.

Abstract: An LED illumination source comprises a heat dissipating substrate which includes a metal plate and at least two insulating layers thereon. LEI) bare chips are mounted on a surface of the substrate. An optical reflector with holes surrounds the LED bare chips. The optical reflector is provided on the surface of the substrate on which the LED bare chips are mounted. A resin encapsulates the entire optical reflector on the substrate, the resin molding each of the LED bare chips and functioning as an optical lens for each of the LED bare chips.

Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.

Abstract: An IGBT includes a plurality of n+ doped regions (11) selectively formed in a main surface (103) of a p+ semiconductor layer (12) opposite from an n type semiconductor layer (80) without being connected to the n type semiconductor layer (80). The n+ doped regions (11) are formed in corresponding relation to and only under channel regions (CH1a-CH1d) of structures (200a-200d), respectively. This lowers the effective concentration of the p+ semiconductor layer (12) on the n+ doped regions (11) to reduce the number of holes injected from a collector layer (9) in an off state, reducing a leakage current.

Abstract: A method of making a bulk crystal substrate of a GaN single crystal includes the steps of forming a molten flux of an alkali metal in a reaction vessel and causing a growth of a GaN single crystal from the molten flux, wherein the growth is continued while replenishing a compound containing N from a source outside the reaction vessel.

Abstract: The nitride semiconductor device according to one embodiment of the present invention comprises: a silicon substrate; a first aluminum gallium nitride (AlxGa1?xN (0?x?1)) layer formed as a channel layer on the silicon substrate in an island shape; and a second aluminum gallium nitride (AlyGa1?yN (0?y?1, x<y)) layer formed as a barrier layer of a first conductive type or i-type on the first aluminum gallium nitride layer.

Abstract: The present invention, which aims to provide a gallium arsenide field-effect transistor that can reduce degradation of field-effect transistor characteristics, and to realize miniaturization of the transistor, includes: a substrate; a mesa which includes a channel layer and is formed on the substrate; a source electrode formed on the mesa; a drain electrode; and a gate electrode, wherein, on the mesa, a top pattern is formed in which finger portions of the source electrode and the drain electrode which are formed in comb-shape are located so as to interdigitate, and a gate electrode is formed between the source electrode and the drain electrode, while common portions, which are base parts of the finger portions of the source and drain electrodes, are formed on the surface of the mesa, and the part located below the straight portion which is parallel to the finger portions of the gate electrode is electrically separated from the part located below a corner portion that connects neighboring straight portions of

Abstract: A semiconductor device includes: a gate electrode that is provided on a semiconductor layer; a source electrode and a drain electrode that are provided on the semiconductor layer so as to interpose the gate electrode; a source wall that extends from the source electrode to a point between the gate electrode and the drain electrode through the region above the gate electrode, the source wall having a joining portion in the extending region; and an electrode portion that is joined to the joining portion and has a region extending closer to the drain electrode than the joining portion.

Abstract: The electronic device includes a plurality of layout regions each including a plurality of patterns defined by a buried structure buried in a substrate. For each of the layout regions, in each of the layout regions, the minimum space between the patterns, and a maximum area percentage allowed for the patterns in the layout region are defined based on a size of the layout region. In larger one of the layout regions, the minimum space between the patterns in the region is set larger.

Abstract: A fin field effect transistor (FinFET) includes a reversed T-shaped fin. The FinFET further includes source and drain regions formed adjacent the reversed T-shaped fin. The FinFET further includes a dielectric layer formed adjacent surfaces of the fin and a gate formed adjacent the dielectric layer.

Abstract: There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

Abstract: An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, while other transistors can have normal symmetrical (i.e, two-sided) active area extension regions (e.g., lightly doped drains) with resulting high performance and short gate lengths. The asymmetrical active area extension region of the transistor associated with the photodiode can serve to reduce dark current at the photoconversion device. The punch-through problem normally cured by a lightly doped drain is fixed at the transistor associated with the photoconversion device by adding a Vt adjustment implant and/or increasing its gate length.

Abstract: Ferroelectric rare-earth manganese-titanium oxides and methods of their manufacture. The ferroelectric materials can provide nonvolatile data storage in rapid access memory devices.

Abstract: A capacitor of a memory device, and a method of fabricating the same, includes a lower electrode electrically coupled to a doping region of a transistor structure, the lower electrode having a metal electrode and a metal oxide electrode, a ferroelectric layer covering and extending laterally along the lower electrode, and an upper electrode formed on the ferroelectric layer.

Abstract: A field-effect transistor (FET) structure and method of formation thereof is presented. The FET structure includes first and second source/drain regions formed in a semiconductor substrate to define a channel region. A gate insulation layer is formed at a surface of the channel region. A control layer is formed at a surface of the gate insulation layer. A diode doping region is formed to realize a diode in the semiconductor substrate. An electrically conductive diode connection layer connects the diode doping region to the control layer. A depression is formed in the semiconductor substrate. The diode doping region is formed at a bottom of the depression and the diode connection layer is formed in the depression to dissipate excess charge carriers in the semiconductor substrate.

Abstract: Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

Abstract: A nonvolatile semiconductor memory device includes a substrate, a central structure, a second gate insulating film, a floating gate, and a control gate. The substrate has a trench. The central structure is formed so as to be embedded in the trench and protruded from the substrate. The second gate insulating film is formed on the substrate so as to be contact with the central structure. The floating gate is formed on the second gate insulating film. The control gate is formed so as to cover the floating gate through a insulating film;. The central structure includes an assistant gate and a first gate insulating film which is formed such that the assistance gate is surrounded with the first gate insulating film. The floating gate is formed in a side wall shape on the side surface of the central structure.

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

Abstract: A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage MOS transistor having a high-voltage gate insulation layer is provided. The PMOS access transistor has an access gate oxide layer that has a thickness equal to the thickness of the high-voltage gate insulation layer in a peripheral circuit area.

Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

Abstract: A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes a new well design that provides a large capacitance from a retrograde well region of the second conductivity type to the substrate thereby providing noise decoupling with a low number of well contacts. The present invention also provides a method of fabricating such a semiconductor structure.

Abstract: A layout structure of a static random access memory (SRAM) cell array includes at least one SRAM cell area, oxide defined (OD) area and strapping cell area. The SRAM cell area has a longitudinal side being at least twice longer than a transverse side thereof. The oxide defined (OD) area is formed on an insulating layer, extending across at least two neighboring SRAM cell areas for construction of a passing gate transistor and a pull-down transistor used in an SRAM cell. The strapping cell area is interposed between the SRAM cell areas, in which a strapping cell is constructed for connecting the OD area to a fixed potential, thereby preventing bodies of the passing gate transistor and the pull-down transistor constructed on the OD area from floating.

Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

Abstract: The semiconductor component has ESD protective elements configured outside the semiconductor body. The ESD protective elements connect an additional conductor track that carries a reference potential to conductor tracks of the leadframe. ESD protective structures integrated on the semiconductor body are no longer required. The correspondingly high area consumption is avoided.

Abstract: Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.

Abstract: A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.

Abstract: A conductor with improved magnetic field per current ratio is disclosed. The conductor includes a magnetic liner lining a second surface and sides thereof. The magnetic liner is preferably a super-paramagnet with high susceptibility or a ferromagnet with a microstructure where the size of the non-exchanged coupled micro domains is so small that their energy content is close to or small compared to kT that such films have super-paramagnetic properties and essentially behave like a paramagnet with high susceptibility.

Abstract: A package for an integrated circuit contacting device which is shaped like a frame. A portion of the contacting device may be bonded to the printed circuit board, and includes leads which extend along in outer surface thereof, from an outside edge of the package to a downward facing surface of the package which faces an integrated circuit die. The package may be in dented in the shape of the die, and may also include indentations allowing a lid and/or a back portion to be located thereon. In an embodiment, a lens amounts may also be used.

Abstract: A packaging structure suitable for an integrated circuit device receiving short-wavelength laser light is provided. A lead-mounted substrate is placed on the side of the light receiving surface of the integrated circuit device having a photo detecting part. The lead is electrically connected with the integrated circuit device via an electrode. The integrated circuit device and the substrate are encapsulated with an encapsulation section. The substrate has an opening at a position above the photo detecting part.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier.

Abstract: An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.

Abstract: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.

Abstract: Provided is a method for manufacturing a lead frame and a semiconductor package having a semiconductor chip for connecting to an outer board and having a base metal layer formed of iron and nickel as main elements. The method includes preparing the base metal layer of a lead frame, forming one or more plating layers on the base metal layer, mounting the semiconductor chip on the lead frame, molding the semiconductor chip and at least a portion of the lead frame, bending the lead frame to form the lead frame in a predetermined shape, and heat-treating the lead frame for forming a diffusion layer in order to protect the lead frame from corrosion.

Abstract: A semiconductor package that includes two semiconductor die each disposed on a respective die pad and a large tracking distance interposed between at least two leads of the package for better creepage characteristics.

Abstract: Signal traces are patterned on a top surface of a substrate. A ground trace is patterned on the top surface of the substrate for at least one pair of the signal traces. A die paddle is patterned on the top surface of the substrate, and the die paddle is connected directly with the ground trace.