Abstract: A cabinet cord eject structure includes a cord eject port penetrated in a rear part of a rear cabinet molded of a flame retardant synthetic resin, and a movable lid for closing the cord eject port integrally formed via a thin hinge portion on the rear cabinet. The movable lid is rotated open around the thin hinge portion, a chassis is inserted into the rear cabinet, an AC cord is pulled out through the cord eject port, the chassis is placed on a bottom plate portion of the rear cabinet, and the movable lid is rotated closed around the thin hinge portion to close the cord eject port.

Abstract: The present invention relates to a stand 1 for an external flat screen display device 4a such as an LCD or plasma display monitor. Accordingly, the stand 1 has base side members 2 that create clearance 6a where an attached portable computer display can be stored behind a mounted, external flat screen display 4a. The attached portable computer display 10 is slid between the base side members while being tucked under and behind the mounted flat screen display 4a. The mounted flat screen display 4a remains positioned directly above the portable computer's 9 keyboard, while the portable computer 9 remains positioned between the base side members. The present invention also provides a flat screen display stand 1 that does not significantly increase the dimensions of the shipping container. Alternatively, this invention may be used to mount flat screen display 4a devices to both horizontal and vertical surfaces.

Abstract: A system for displaying images includes: (a) a base; (b) a movable, arcuate-shaped receptacle that rotates into and from the base; and (c) a display attached to the receptacle so that the display is visible when the receptacle is rotated from the base and the display is partially or entirely not visible when the receptacle is rotated into the base.

Abstract: According to one embodiment of the present invention, a method of converting a computer from a folded position into an alternate position is disclosed. The method includes: providing a display; providing a base coupled to the display; providing a base flap pivotally attached to the display and the base, the base flap being attached to the display at a distance sufficiently away from edges of the display to provide a reduced volumetric size of the computer in a laptop position.

Abstract: Portable computers include a display unit and a base unit. The base unit often includes a keyboard and a touch-sensing device. The position of the display unit relative to the base unit can be adjusted. In one embodiment, a track and support bar is used to vary the display unit's height. In another embodiment, a collapsible support bar is used to vary the display unit's height. In another embodiment, a ball-and-socket joint is used to pivot the display unit. In another embodiment, a retractable touch-sensing device is attached to the base unit.

Abstract: A two-way auto-locking tablet PC hinge is described. The two-way auto-locking tablet PC hinge includes a hinge base, a central rotational frame, a shaft, a fixing bracket, a rotational cam, a fixed cam, and two positioners. The fixing bracket, the rotational cam, and the fixed cam are configured on the shaft. A monitor of the tablet PC is fixed on the fixing bracket and the hinge base is fixed on a tablet PC base. The positioners are composed of protrusion blocks and concaves and are axially symmetrically formed on the fixed cam and the rotational cam respectively. When the monitor is parallel to the tablet PC base, the protrusion blocks are engaged with the concaves correspondingly, thereby locking the monitor on the tablet PC.

Abstract: A computer system with vertically offset hard disk drives has a space in one side for containing the two vertically offset hard disk drives held by a mobile rack in a vertically offset manner. The mobile rack fixes the two hard disk drives with two vertically offset screw sets. A holding frame in the space of the computer system has two vertically offset connectors that allow the two hard disk drives to be connected at the same time when the mobile rack is completely inserted into the holding frame.

Abstract: An energy dissipative element (24) protects hard disk drives (22, 72, 92) from shocks and vibrations. A closed elastic envelope (48) houses a body of open cell foam (54), a volume of viscous liquid (56), and a compressible gas (64). Under compression or expansion of the foam (54), viscous liquid (56) flows through cell orifices and thereby dissipates energy resulting from external force applied against the elastic wall (48). The energy dissipative elements (24) are applied between a disk drive housing (22) and an outer case (26) to create a ruggedized portable disk drive module (20).

Abstract: A computer drive carrier to be removably received within a receiving frame so that a computer drive transported by the carrier can be interfaced with a host computer. A handle is pivotally connected to the computer drive carrier and adapted to be rotated between a closed position when the carrier is received within the receiving frame and an open position when it is desirable to remove the carrier and its drive from the receiving frame to be replaced by a different carrier. A key controlled lock is mounted on the receiving frame and includes a locking pawl that is rotatable from an unlocked position, at which to permit the handle to be rotated from the closed position to the open position so that the computer drive carrier can be removed from its receiving frame, to a locked position, at which to prevent the handle from being rotated to the open position so that the computer drive carrier is locked in place in the receiving frame.

Abstract: Described is a device which includes a housing, a chimney and a heat dissipation element. The housing includes at least one heat generating electric component mounted within an interior space thereof. The chimney extends from a proximal end surrounding a space adjacent to the at least one component through an opening in the housing to a distal end outside the housing. The heat dissipation element is attached to the distal end of the chimney and separated from the housing so that heat from the at least one component travels through the chimney to the heat dissipation element from which it is dissipated.

Abstract: An extended fin array has a main heat-dissipation module and an extended heat-dissipation module. The main heat-dissipation module and the extended heat-dissipation module are stacked to increase the effective convective area to increase the heat-dissipation effect. The extended heat-dissipation module is in the main heat-dissipation module when the heat amount generated by an electronic device is normal. The extended heat-dissipation module extends out from the main heat-dissipation module to increase the heat convection area when the heat amount generated by the electronic device is large.

Abstract: A fan assembly formed of a fan, at least one fan grill comprising a face panel and at least one side panel comprising a spring slot the fan grill coupled to the fan, and a spring coupled to the fan grill the spring comprising a spring driver end extending through the spring slot.

Abstract: A heat dissipation device includes a heat sink (20) having a plurality of fins (26), a fan duct (50), a fan (70) and a mounting bracket (60) for mounting the fan duct and the fan to the heat sink. The fan duct is mounted to a front side of the heat sink, and includes an inlet, an enlarged outlet covering the front side of the heat sink and at least two channels (56). The fan duct is capable of expanding an airflow generated by the fan by the enlarged outlet and dividing the airflow by the at least two channels into at least two sub-airflows. Thus, the fan can blow the airflow through all of the fins to thereby promote a heat dissipating efficiency of the heat dissipation device.

Abstract: An electronic component, cooling apparatus comprises a so-called water-cooled heat sink, a radiator to be cooled by a motor-driven fan, first and second coolant paths for circulating a coolant between the heat sink and the radiator, and a motor-driven pump for giving a moving energy to the coolant. A plurality of engaging pieces of the motor-driven fan and a plurality of engaged portion of the radiator are engaged to connect the motor-driven fan and the radiator.

Abstract: A thermal management system for an IC device mounted on a circuit board is provided. The system includes a socket housing and an array of power contacts disposed within the housing. The power contacts deliver power to an underside of the IC device and generate heat at the underside of the IC device. A heat conducting interface conveys heat from the underside of the IC device to a heat sink positioned above the IC device.

Abstract: Embodiments of the present invention include an apparatus, method and system for a thermal management arrangement in a standardized peripheral device.

Abstract: A display apparatus dissipates heat efficiently from a tape carrier package driver integrated circuit providing an address voltage to a display panel. The display apparatus includes a display panel, a chassis base, a driving circuit, an flexible printed circuit electrically connecting electrodes of the display panel to the driving circuit, and a driver integrated circuit connected through the flexible printed circuit to the display panel, the driver integrated circuit providing a voltage selectively to the electrode of the display panel in accordance with signals controlled by the driving circuit. A thermally conductive medium in liquid-phase or gel-phase is placed between the driver integrated circuit and the chassis base. A pressing plate is placed on the outside of the driver integrated circuit opposite to the chassis base, the pressing plate pressing the driver integrated circuit toward the chassis base for good contact and heat dissipation.

Abstract: A rack for housing dosimeters includes a plurality of blocks having a rectangular shape. Each block is provided with a housing space for housing the dosimeter and an entrance opened in a front surface of the block for inserting the dosimeter therethrough. Each block also has at least one of a projection and a concavity formed on at least one of top, bottom, left, and right surfaces to be fitted to each other. Accordingly, it is possible to assemble the plurality of the blocks in at least one of vertical and horizontal directions by fitting the projection and the concavity on the blocks.

Abstract: The present invention discloses a timer switch that uses an integrated circuit to control the time and a self-locking electromagnetic coil solenoid valve to drive the operation of a microswitch, which is particularly applicable to be installed on a wall as a timer switch. The switch device uses the electronic control of two 1.5V AA batteries to enter a set time through input keys, and a CPU will issue a pulse with very short timing of 30 ms to the solenoid to produce a magnetic field to drive a turning rod and open a primary switch in order to turn on or off a circuit.

Abstract: Device for locking and unlocking at least one interface card plugged into a socket of a receiving system (2) linked to a data processing system. The device (1) comprises a box (3) mounted to the receiving system (2) and receiving at least one sliding locking/unlocking element (4a-4n) for locking/unlocking interface cards. Each of elements (4a-4n) is disposed opposite a socket in a position that blocks the access to or removal of an interface card. Each element (4a-4n) comprising an element for controlling the power supply (63) of the card, a visual element for indicating the operation and the recognition of the card, and a detecting element for detecting the intent to unlock the card. The device (1) includes a communication element that makes it possible to transmit signals between the data processing system and the device.

Abstract: A display includes a monitor module, a base and a shielding apparatus. The base is coupled to the monitor module, and the shielding apparatus is disposed between the base and the monitor module. The shielding apparatus includes a magnetic core and a non-flexible coiled device having a number of fixed shape coils. The coiled device is put through the magnetic core so that the magnetic core is selectively surrounded by at least one of the coils of the coiled device. The monitor module is therefore grounded via the shielding apparatus.

Abstract: A mechanism may couple an electrical assembly with circuit boards in a computer system. The mechanism may include injectors on the electrical assembly and a receptacle on each of the circuit boards. The injectors may engage the receptacles to couple header connector parts on the electrical assembly with receptacle connector parts on the receptacles. The electrical assembly may include a latch device that holds the injectors in a closed position after injection of the electrical assembly.

Abstract: Provided is a direct-current converter which can reduce power consumption at light load by reducing switching losses of a main switch. The direct-current converter is provided with: a first serial circuit which is connected to both ends of a direct current power supply Vdc1 and in which a primary winding P of a transformer T and a main switch Q1 are serially connected to each other; a second serial circuit which is connected both ends of the primary winding P of the transformer T and in which an auxiliary switch Q2 and a snubber capacitor C2 are serially connected to each other; rectifying/smoothing circuits D5, D6, L1 and C5 which rectify and smooth a voltage generated in a secondary winding S of the transformer T by energy supplied from the primary winding P of the transformer T when the main switch Q1 is turned on; and a control circuit 10 which turns on/off the main switch Q1 and the auxiliary switch Q2 alternately using a signal with predetermined switching frequency.

Abstract: A content comparator memory (CCM) device can include a row (100) of CCM cells (102-1 to 102-I). Each CCM cell (102-1 to 102-I) can have a controllable signal path (104-1 to 104-I) arranged in series to form a match path (106) that provides a match indication MATCH that can be activated when a comparand value (CD[1:I]) is determined to match a stored data value. Each CCM cell (102-1 to 102-I) can also be commonly connected to a comparator line (110) that can provide a comparator indication CMP when a compare value (CD[1:I]) has a predetermined magnitude with respect to a stored value.

Abstract: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

Abstract: A Y selection line for write for controlling operations of a column selection switch within a write amplifier and a Y selection line for read for controlling operations of a column selection switch within a read amplifier are provided individually and the column selection switch within the read amplifier is set to the non-operating condition during the write operation. Accordingly, a through-current during the write operation may be reduced. In this case, the write IO line and read IO line are allocated crossing sense amplifier columns, while the column selection line for write and column selection line for read are allocated in parallel to the sense amplifier columns.

Abstract: A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.

Abstract: The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.

Abstract: In a memory circuit having memory cells which are connected in series between a ground line PL and a bit line BL and in each case have a resistance memory element said element having a bipolar switching behavior having an anode electrode and a cathode electrode, and a drive transistor connected in parallel with the resistance memory element, the drive transistors of the memory cells in each case are connected to a word line in order to switch the drive transistor on and off in such a way that a current path is formed via the associated drive transistor in a non-activated state of a memory cell and a current path is formed via the associated resistance memory element in an activated state of a memory cell, a first changeover switch being arranged at one end and a second changeover switch at other ends of the series of memory cells in order alternately to produce a connection between the series-connected memory cells and the ground line and the bit line in a manner dependent on an applied address.

Abstract: A memory capable of suppressing disturbance causing disappearance of data from a nonselected memory cell is provided. This memory applies a second voltage of polarity reverse to that of a first voltage applied to a nonselected memory cell in a read operation to at least the nonselected memory cell in addition to the read operation collectively performed on all memory cells connected to a selected word line.

Abstract: The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor.

Abstract: A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells.

Abstract: The present invention relates to magnetic or magnetoresistive random access memories (MRAMs). The present invention provides an array with magnetoresistive memory cells arranged in logically organized rows and columns, each memory cell including a magnetoresistive element (32A, 32B). The matrix comprises a set of column lines (34), a column line (34) being cells of a column. A column line (34) is shared by two adjacent columns, the shared column line (34) having an area which extends a continuous conductive strip which is magnetically couplable to the magnetoresistive element (32A, 32B) of each of the memory cells of a column. A column line (34) is shared by two adjacent columns, the shared column line (34) having an area which extends over substantially the magnetoresistive elements of the two adjacent columns sharing that column line.

Abstract: Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.

Abstract: Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells.

Abstract: Data encoding system and method for implementing robust non-volatile memories. A data bit is stored using two memory cells. The data bit is represented by setting a voltage level of a first memory cell to a first voltage level and setting a voltage level of a second memory cell to a second voltage level. In one embodiment, the first voltage level and the second voltage level are of opposite polarity. In one embodiment, to store a data bit having the value “0,” the first memory cell is set to a first voltage level and the second memory cell is set to a second voltage level of opposite polarity to the first voltage level, and to store a data bit having the value “1,” the first memory cell is set to a third voltage level and the second memory cell is set to a fourth voltage level of opposite polarity to the third voltage level.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

Abstract: A semiconductor device includes: memory blocks each having groups of memory cells that are connected to word lines; select gates for selecting the groups of memory cells; and an apply circuit that applies, at the time of reading data, a back bias to the select gates of unselected memory blocks.

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract: In a flash memory device and a bit line voltage control method thereof a circuit capable of reducing the change in a voltage of a bit line during programming. The flash memory device includes: a flash memory cell, a source of which is connected to a source line, a drain of which is connected to a bit line and a gate of which is connected to a word line; a word line voltage generation circuit connected to the word line, for generating and providing a word line voltage to the word line; a program current generation circuit connected to the bit line, for generating and providing a program current to the bit line; and a bit line voltage clamp circuit connected to the bit line and the word line, for sensing a voltage of the bit line and controlling a bias current of the word line voltage generation circuit to thereby control a voltage of the bit line, during a programming operation of the flash memory device.

Abstract: An integrated circuit device comprising a memory cell array including a plurality of memory cells wherein each memory cell includes at least one electrically floating body transistor having source, drain and a body regions, wherein the body region is electrically floating and disposed between the source and drain regions; a gate is disposed over the body region. Each memory cell includes a first data state representative of a first charge in the body region and a second data state representative of a second charge in the body region. The integrated circuit device further includes operating characteristics adjustment circuitry, coupled to the memory cell array, to adjust one or more operating or response characteristics of one or more memory cells to improve the uniformity of operation/response characteristics of the memory cells of the memory cell array relative to the other memory cells of the array.

Abstract: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.

Abstract: A method for verifying a programmed flash memory. When reading a memory cell, a voltage applied to a drain of the memory cell is a read drain voltage. First, a word line is enabled by applying a verification gate voltage. Next, a first bit line, which is connected to the drain of the memory cell, is enabled and a verification drain voltage, which is higher than the read drain voltage, is applied to the first bit line. Then, a second bit line is enabled and grounded. Thereafter, a third bit line is enabled and a verification isolation voltage is applied. Then, a drain current of the first bit line is sensed, wherein the drain current flows through the first bit line, the memory cell, and the second bit line. Finally, it is judged whether or not the memory cell is successfully programmed according to the drain current.

Abstract: A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low Vt value. A data region that is to be programmed to a highest Vt value is programmed first. Remaining data regions in the nitride read-only memory cell are programmed in a time order according to their descending Vt values. For a nitride read-only memory cell that, in an erased state, exhibits a high Vt value, a data region that is to be programmed to a lowest Vt value is programmed first with remaining data regions programmed in a time order according to their ascending Vt values.

Abstract: An integrated circuit (IC) includes volatile memories, at least one non-volatile memory, at least one control circuit, and a configurable logic array. Each volatile memory has an associated interface including a respective first input and a respective second input. The control circuit is coupled to the volatile memories and the non-volatile memory. The control circuit stores respective contents from each volatile memory in the non-volatile memory responsive to the respective first input, and loads the respective contents into each volatile memory from the non-volatile memory responsive to the respective second input. The configurable logic array is coupled to the volatile memories and is configurable to control each first input and each second input.

Abstract: Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the first differential amplifier, and connects the output node to a low power supply line in response to the activation of an output signal of the second differential amplifier. Only during the activation period of the drivability control signal, a second driving circuit connects the output node to the high power supply line in response to the activation of the output signal of the first differential amplifier, and connects the output node to the low power supply line in response to the activation of the output signal of the second differential amplifier.

Abstract: A peripheral voltage generator is provided for reducing an operating current by generating a peripheral voltage within a mobile SDRAM, and a current is used in a deep-power down mode and a self refresh mode to thereby enhance operational characteristics. The peripheral voltage generator includes a reference voltage generating unit for generating a peripheral reference voltage having a different level in response to an enable signal and a self-refresh signal; a comparing unit for comparing the peripheral reference voltage with a peripheral driving voltage to thereby output a peripheral voltage control signal based on the comparison result; and a peripheral voltage control unit for generating the peripheral driving voltage having a first peripheral level in response to the peripheral voltage control signal.

Abstract: A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode register outputs a soft reset signal when at least a value of one-bit of the register part represents a reset state. A reset signal generator outputs a reset signal for resetting an internal circuit in response to the soft reset signal. In the present invention, a system that controls the semiconductor memory is required to necessarily assign a predetermined bit with a setting command of the mode register in order to generate the soft reset signal. Accordingly, it is possible to reliably reset the internal circuit by external control.

Abstract: An additive latency circuit for a DDR2 standard compliant integrated circuit memory includes a half flip-flop register assigned for each case of additive latency. A unique clock is generated to control each bit in the register chain. Sufficient register bits are required in the chain to support the highest additive latency specified. For latency settings less than the maximum, those clocks assigned to the bits above the chosen latency are enabled so the data passes through un-clocked. For the additive latency zero case, a separate bypass path is provided. Both address and command information is delayed by the additive latency delay chain. Once delayed by the proper number of cycles, the address information remains in that state until the time when a new state is required. Command information remains valid for one cycle upon reaching the proper delay point. A reset circuit is provided to reset command signals.

Abstract: A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant columns of memory is associated with a corresponding one of a plurality of memory sub-arrays. The columns of memory of the sets of local redundant columns of memory are adapted to replace defective columns of memory of the respective memory sub-arrays. The column redundancy system further includes columns of shared redundant memory that are adapted to replace defective columns of memory of the plurality of memory sub-arrays.