Abstract: A semiconductor light-emitting device includes: a semiconductor multilayer film, a substrate supporting the semiconductor multilayer film; and a phosphor layer formed on the substrate so as to cover the semiconductor multilayer film. The phosphor layer has an outer edge of a cross section taken in a direction parallel to the principal surface of the substrate having a substantially circular shape or a substantially regular polygonal shape having five or more sides. An outer edge of the principal surface of the substrate is formed in a substantially circular shape or a substantially regular polygonal shape having five or more sides. With this configuration, light obtained therefrom has less non-uniformity in color and a high luminous flux can be realized.

Abstract: Employing a LED which emits light via excitation with UV light, particularly the foregoing high-power LED, disclosed are a white LED exhibiting high reliability and longer operating life, and a method of manufacturing the white LED. Also disclosed are a white light emitting diode possessing a phosphor layer which emits light via excitation with UV light, wherein the phosphor layer consists of phosphor, or possesses phosphor and transparent inorganic oxide, and a method of manufacturing the white light emitting diode, possessing the step of making phosphor particles to collide with a light emitting diode at high speed to deposit the phosphor layer, employing an aerosol deposition process.

Abstract: To improve the front brightness of the light emitted from a surface light emitter having a surface light emitting device. In the surface light emitter to which a light control sheet having depressions is provided, the surface of the light control sheet having the depressions is adhered to a light emitting side surface of a surface light emitting device, and the transparent material whose refractive index is lower than the refractive index of the light control sheet is arranged in the spaces formed between the depressions and the light emitting side surface of the surface light emitting device.

Abstract: A light emitting diode module having improved luminous efficiency is provided. The light emitting diode module includes: a light emitting chip; a phosphor layer formed of phosphor materials emitting light having a wavelength longer than the light emitted from the light emitting chip using light emitted from the light emitting chip as an excitation source; and a reflection plate that is disposed between the light emitting chip and the phosphor layer and that reflects the light emitted by the phosphor layer.

Abstract: A semiconductor device 10 has such a structure that a plurality of through electrodes 30 is formed on a substrate 20 and each of terminals of light emitting devices (LEDs) 40 is electrically connected to each of the through electrodes 30 via a bump 50 on a lower surface side. In the semiconductor device 10, moreover, a partition wall 80 for surrounding a mounting region of each of the light emitting devices 40 is formed on the substrate 20. The partition wall 80 is formed by laminating a metal film (Cu) using a thin film forming method such as a plating method. Furthermore, the partition wall 80 is formed to be opposed close to each of side surfaces of the light emitting devices 40 and is provided to surround each of the light emitting devices 40.

Abstract: A Chip on Board (COB) package which can reduce the manufacturing costs by using a general PCB as a substrate, increase a heat radiation effect from a light source, thereby realizing a high quality light source at low costs, and a manufacturing method thereof. The COB package includes a board-like substrate with a circuit printed on a surface thereof, the substrate having a through hole. The package also includes a light source positioned in the through hole and including a submount and a dome structure made of resin, covering and fixing the light source to the substrate. The invention allows a good heat radiation effect by using the general PCB as the substrate, enabling manufacture of a high quality COB package at low costs. This in turn improves emission efficiency of the light source, ultimately realizing a high quality light source.

Abstract: A nitride-based group III-V semiconductor substrate has an as-grown surface on the surface thereof; and a flat surface on the back surface of the substrate. The c-axis of a nitride-based group III-V semiconductor crystal composing the substrate is substantially perpendicular to the surface of the substrate or inclined at a predetermined angle to the surface of the substrate.

Abstract: There is disclosed a radiation detector comprising a II-VI compound semiconductor substrate that absorbs radiation having a first energy, a II-VI compound semiconductor layer of a first conductivity type provided on a main surface of the II-VI compound semiconductor substrate, a metal layer containing at least one of a group III element and a group V element provided on the II-VI compound semiconductor layer, a IV semiconductor layer having a second conductivity type opposite to the first conductivity type provided on the metal layer, and a IV semiconductor substrate that absorbs radiation having a second energy different to the first energy provided on the IV semiconductor layer.

Abstract: A III-nitride heterojunction semiconductor device that includes a power electrode that is electrically connected to a conductive substrate through a trench in the heterojunction thereof.

Abstract: To increase productivity of organic thin-film transistors, in an organic thin-film transistor manufacturing equipment, a liquid containing at least either one of a wiring material and a semiconductor material is coated on a substrate to form a number of organic thin-film transistors. Substrate carrying means carry the substrate. The substrate is heated by a first heating means, and the temperature of the substrate is controlled by a controller. The liquid containing at least either one of the wiring material and the semiconductor material is heated by a second heating means, and the temperature of this liquid is controlled also by the controller.

Abstract: A semiconductor light emitting device has a gallium nitride compound semiconductor, and a first cladding layer of a first conductivity type, an active layer, an electron barrier layer of a second conductivity type and made of InxAlyGa1-x-yN (0?x?1 and 0?y?1), and a second cladding layer of the second conductivity type, laminated, in orders, on a substrate. The electron barrier layer has a larger band gap than each of the active layer and the second cladding layer. The thickness of the electron barrier layer is in a range from 2 nm to 7 nm.

Abstract: A field effect transistor includes a first semiconductor layer made of a first group III-V nitride; a second semiconductor layer formed on the first semiconductor layer, made of a second group III-V nitride and having a gate recess portion for exposing the first semiconductor layer therein; and a gate electrode formed on the first semiconductor layer in the gate recess portion. A product of stress applied by the second semiconductor layer to the first semiconductor layer and the thickness of the second semiconductor layer is 0.1 N/cm or less.

Abstract: A semiconductor device including a horizontal unit semiconductor element, the horizontal unit semiconductor element including: a) a semiconductor substrate of a first conductivity type; b) a semiconductor region of a second conductivity type formed on the semiconductor substrate; c) a collector layer of the first conductivity type formed within the semiconductor region; d) a base layer of the first conductivity type having an endless shape and formed within the semiconductor region such that the base layer is off the collector layer but surrounds the collector layer; and e) a first emitter layer of the second conductivity type formed in the base layer, the horizontal unit semiconductor element controlling, within a channel region formed in the base layer, movement of carriers between the first emitter layer and the collector layer, wherein the first emitter layer is formed by plural unit emitter layers which are formed along the base layer.

Abstract: A method of manufacturing a field emission device (FED), which reduces the number of photomask patterning processes and improves the manufacturing yield of the FED, is provided.

Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.

Abstract: A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.

Abstract: A semiconductor device of complementary structure with increased carrier mobilities of both polarities by applying orientation-dependent mechanical stresses to their respective semiconductor channel regions, comprises a semiconductor region subjected to compressive stress in a first direction along a surface and tensile stress in a second direction different from the first direction, a field effect transistor of a first conductivity type formed in the semiconductor region and including source and drain regions separately arranged along the first direction and a field effect transistor of a second conductivity type formed in the semiconductor region and including source and drain regions separately arranged along the second direction.

Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.

Abstract: The present invention relates to a sensor element which has a semiconductor structure based on a Group III-nitride. The semiconductor sensor element serves for determining the pressure, the temperature, a force, a deflection or an acceleration. It has a substrate base 1, disposed thereon, a homogeneous semiconductor layer based on a Group III-nitride, the surface of the homogeneous semiconductor layer 2 orientated towards the substrate base 1 having at least partially a spacing from the surface of the substrate base orientated towards the homogeneous semiconductor layer 2, 2f, and being distinguished in that at least two electrical conducting contacts 5 for conducting an electrical output signal, which can be generated by the homogeneous semiconductor layer 2, 2f, are disposed on, at or under the homogeneous semiconductor layer 2, 2f or are integrated in the latter.

Abstract: An integrated circuit having a resistance temperature sensor composed of a first resistance structure formed within a trench, and a second resistance structure formed within a mesa region is disclosed. This embodiment makes it possible to suppress or reduce manufacturing-technological fluctuations of the width of the trenches to a resistance value of the resistance temperature sensor.

Abstract: An imaging device capable of multiplying carriers and miniaturizing the device is obtained. The imaging device includes a carrier storage portion for storing carriers generated by photoelectric conversion, having a photoelectric conversion function, a multiplier section including a multiplier electrode applying an electric field for multiplying carriers due to impact ionization by an electric field, one first transfer electrode so provided between the carrier storage portion and the multiplier electrode as to be adjacent to the carrier storage portion and the multiplier electrode.

Abstract: Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.

Abstract: A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.

Abstract: An imaging apparatus is provided in which a plurality of pixels, each having a conversion element and a thin-film transistor, are arranged in a two-dimensional fashion on an insulating substrate; the photoelectric conversion element is arranged over the thin-film transistor, with an insulating film, which serves as an interlayer insulating film, inserted between the conversion element and the thin-film transistor; and by way of a contact hole portion provided in the insulating film, the source electrode or the drain electrode of the thin-film transistor and the photoelectric conversion element are connected with each other. The imaging apparatus has a pixel in which the contact hole portion is removed through a laser-beam irradiation so that the connection portion between the conversion element and a conductive layer, which serves as the source electrode or the drain electrode of the thin-film transistor, is discontinued.

Abstract: A ferroelectric varactor suitable for capacitive shunt switching is disclosed. High resistivity silicon with a SiO2 layer and a patterned metallic layer deposited on top is used as the substrate. A ferroelectric thin-film layer deposited on the substrate is used for the implementation of the varactor. A top metal electrode is deposited on the ferroelectric thin-film layer forming a CPW transmission line. By using the capacitance formed by the large area ground conductors in the top metal electrode and bottom metallic layer, a series connection of the ferroelectric varactor with the large capacitor defined by the ground conductors is created. The large capacitor acts as a short to ground, eliminating the need for vias. The concept of switching ON and OFF state is based on the dielectric tunability of the ferroelectric thin-films. At 0 V, the varactor has the highest capacitance value, resulting in the signal to be shunted to ground, thus isolating the output from the input.

Abstract: A dual-gate non-volatile memory cell includes a first dielectric layer extending over a first gate, a semiconductor region extending over the first dielectric layer, a second dielectric layer comprising tunnel oxide extending over the semiconductor region, a ferroelectric layer extending over the second dielectric layer, and a second gate extending over the ferroelectric layer.

Abstract: A plurality of floating gates are formed on a principal surface of a semiconductor substrate that constitutes a nonvolatile semiconductor memory device through a first gate dielectric film. An auxiliary gate formed on the principal surface of the semiconductor substrate through a third gate dielectric film is formed on one adjacent side of the floating gates. A groove is formed on the other adjacent side of the floating gate, and an n-type diffusion layer is formed on a bottom side of the groove. A data line of the nonvolatile semiconductor memory device is constituted by an inversion layer formed on the principal surface of the semiconductor substrate to be opposed to an auxiliary gate by applying desired voltage to the auxiliary gate, and the n-type diffusion layer.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.

Abstract: A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.

Abstract: A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation film. The entirety of that part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer. At least a portion of that part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer.

Abstract: A semiconductor device having reduced pitting may be formed from isolation layer patterns on a semiconductor substrate defining an active region, a tunnel oxide layer on the active region, the tunnel oxide layer having a nitrified surface, a floating gate on the tunnel oxide layer, a dielectric layer on the floating gate, and a control gate on the dielectric layer.

Abstract: A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.

Abstract: Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, and including a first gate insulator having a first thickness. The device further includes a high-voltage transistor circuit formed on the semiconductor substrate, and including a second gate insulator having a second thickness greater than the first thickness, and a peripheral circuit formed on the semiconductor substrate, and including the second gate insulator.

Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.

Abstract: In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the <11-20> direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

Abstract: Circuits, methods, and apparatus for power MOSFETs having a high cell density for a high current carrying capability while maintaining a low pinched-base resistance. One device employs a number of transistor cells having varying mesa (regions between trench gates) sizes. A heavy body etch is utilized in larger cells to reduce the pinched-base resistance. This etch removes silicon in the mesa region, which is then replaced with lower-impedance aluminum. A number of smaller cells that do not receive this etch are used to increase device current capacity. Avalanche current is directed to the larger, lower pinched base cells by ensuring these cells have a lower BVDSS breakdown voltage. The large cell BVDSS can be varied by adjusting the critical dimension or width of the trench gates on either side of the wider mesas, or by adjusting the depth of the heavy body etch.

Abstract: Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

Abstract: A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relatively a low voltage and a switching operation is principally performed, body floating may be adopted. Body voltage fixing may be adopted in an analog system circuit that essentially dislikes a kink phenomenon of a current-voltage characteristic. Body bias variable control may be adopted in a logic circuit that requires the speedup of operation in an active state and needs low power consumption in a standby state. Providing in mixed form the transistors which are subjected to the body floating and the body voltage fixing and which are variably controlled in body voltage, makes it easier to adopt an accurate body bias according to a circuit function and a circuit configuration in terms of the speedup of operation and the low power consumption.

Abstract: The present invention is to provide a semiconductor device that achieves high mechanical strength without reducing the circuit scale and that can prevent the data from being forged and altered illegally while suppressing the cost. The present invention discloses a semiconductor device typified by an ID chip that is formed from a semiconductor thin film including a first region with high crystallinity and a second region with the crystallinity inferior to the first region. Specifically, a TFT (thin film transistor) of a circuit requiring high-speed operation is formed by using the first region and a memory element for an identifying ROM is formed by using the second region.

Abstract: In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

Abstract: A semiconductor device includes a semiconductor layer formed by epitaxial growth in a first region which is obtained by etching a semiconductor substrate to a predetermined depth, a surface of the semiconductor layer having a same height from the bottom of the semiconductor substrate as a height of a surface of the semiconductor substrate, a buried insulating layer buried between the semiconductor substrate and the semiconductor layer and an element isolation region separating each element region in the semiconductor layer and isolating the semiconductor layer from the semiconductor substrate in plan.

Abstract: A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the active layer, source and drain regions formed in the active layer, sandwiching the channel region, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film and on side surfaces of the island-like active layer, and insulated and isolated from the channel, source, and drain regions, and an electrode connected to the active layer.

Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.

Abstract: A semiconductor power device includes Zener diodes for providing an electrostatic discharge (ESD) protection. The semiconductor power device further includes a thick insulation layer for substantially insulating the Zener diodes from a doped region doped with the body dopant ions of the semiconductor power device whereby the Zener diode is substantially insulated from a doped region below the thick insulation layer for eliminating a channel effect between two terminals of the Zener diode disposed above the doped region. The Zener diode further includes an array of doped regions comprising doped regions doped alternately with a first conductivity type and a second conductivity type with a first and last doped regions doped with a first conductivity type. Specifically, the Zener diode may include an array of doped regions comprising doped regions arranged as N+PN+PN+ regions. Alternately, the Zener diode may include an array of doped regions comprising doped regions arranged as N+PN+PN+PN+ regions.

Abstract: A method of forming a wire structure connecting to a bonding pad of a semiconductor chip includes depositing a passivation layer on an active surface of the semiconductor chip, depositing a seed metal layer on the bonding pad and the passivation layer, depositing a metal layer on the seed metal layer, etching selected portions of the seed metal layer, leaving unetched a first area, overlapping the bonding pad and a second area overlapping a connection pad, wherein the wire structure is formed by the metal layer being electrically connected to the bonding pad and the connection pad, but floating from the passivation layer, and depositing an insulting layer on the wire structure.

Abstract: A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.

Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.