Abstract: A sensor including a bobbin including a first region adapted to receive windings and a second region defining a cavity formed in the bobbin. A first electrical terminal is coupled to the bobbin and disposed in the cavity and a second electrical terminal is coupled to the bobbin and disposed in the cavity. A wire including a wound portion wound about the first region. The wire is conductively coupled to the first terminal and the second terminal to provide an electrically conductive pathway from the first terminal to the second terminal. A magnetizable core is disposed at least partially within the wound portion and a magnet is positioned adjacent the magnetizable core. An overmolded shell defining an exterior surface of the sensor encapsulates at least the first region and the wound portion and contacts at least the wound portion.

Abstract: A sensor including a bobbin including a first region adapted to receive windings and a second region defining a cavity formed in the bobbin. A first electrical terminal is coupled to the bobbin and disposed in the cavity and a second electrical terminal is coupled to the bobbin and disposed in the cavity. A wire including a wound portion wound about the first region. The wire is conductively coupled to the first terminal and the second terminal to provide an electrically conductive pathway from the first terminal to the second terminal. A magnetizable core is disposed at least partially within the wound portion and a magnet is positioned adjacent the magnetizable core. An overmolded shell defining an exterior surface of the sensor encapsulates at least the first region and the wound portion and contacts at least the wound portion.

Abstract: A sensor including a sensor core is disclosed. The sensor core includes a magnet, a pole piece, a bobbin, at least two terminals coupled to the bobbin, and a conductor wound about the bobbin and coupled to the terminals. At least a portion of the windings are disposed about at least a portion of the pole piece. The magnet is disposed substantially adjacent the pole piece. A support contacts at least a portion of the conductor. A supported portion of the conductor is located between the windings and the terminals. A sensor housing surrounds at least a portion of the sensor core. A method of manufacturing a sensor including providing a sensor core including a magnet, a pole piece, a bobbin, at least two terminals, and a conductor which is wound about the bobbin and coupled to the terminals is further disclosed. At least a portion of the windings surround at least a portion of the pole piece. The magnet is disposed substantially adjacent the pole piece.

Abstract: A mechanical response of an implantable medical device (IMD) to a first static magnetic field and a first gradient magnetic field slew rate is simulated by exposing the IMD to a second static magnetic field having a magnitude greater than the first static magnetic field and generating a second gradient magnetic field at the IMD such that a product of the second static magnetic field and a second gradient magnetic field slew rate is substantially equal to a product of the first static magnetic field and the first gradient magnetic field slew rate.

Abstract: To provide a position detection apparatus with an expanded range of good linearity in a magnetic sensor's output characteristic with respect to position of a movable body as well as to provide a vehicle mirror angle detection apparatus using the position detection apparatus. Two permanent magnets 42 and 44 and one Hall-effect sensor 46 are used. The permanent magnets 42 and 44 are arranged with their relative position fixed. The Hall-effect sensor 46 is placed laterally to the arrangement of the two permanent magnets 42 and 44. The permanent magnets 42 and 44 and Hall-effect sensor 46 move relative to each other in a direction parallel to the arranging direction of the permanent magnets 42 and 44. Those surfaces 42a and 44a of the permanent magnets 42 and 44 which face the Hall-effect sensor 46 constitute magnetic pole faces of opposite polarity and the magnetic pole faces 42a and 44a are placed with an inward tilt.

Abstract: A fuel level sensor having a magnetic position sensor connected to an arm for attachment to a float, wherein the magnetic position sensor comprises a stator and a movable part, the stator having two soft magnetic pieces defining an air gab, which contains a magnetoresistive probe for measuring the variation in induction in the gap, the moveable part comprising a yoke of soft magnetic materiel displaceable parallel to the magnetic pieces of the stator, and a magnet partly embedded in a cavity in the yoke facing the stator, the poles of the magnet being polarized perpendicularly to direction of movement of the moveable part relative to the stator.

Abstract: To measure a magnetic field strength at each scan spacing s which is smaller than a loop size by scanning a magnetic field sensor (loop antenna) of the loop size. A magnetic field strength distribution is determined with spatial resolution of the spacing s along a scan direction, by performing arithmetic processing including addition and subtraction in relation to each of the measured magnetic field strength values. It is to be noted that the magnetic field sensor may be a magnetic field sensor array with plural magnetic field sensors placed at the spacing s.

Abstract: The use of two or more sensors tuned to the same nuclear quadrupole resonance frequency and detecting the nuclear quadrupole resonance signal results in improved signal-to-noise ratio and therefore improved nuclear quadrupole resonance detection system performance.

Abstract: A magnetic resonance imaging apparatus includes a receiver coil, at least one transmitter antenna, receiver antennas, a signal selection unit and a processing unit. The receiver coil receives a nuclear magnetic resonance signal from an object as a reception signal. The transmitter antenna transmits the reception signal by radio. The receiver antennas are arranged to receive the reception signal. The signal selection unit selects a reception signal received by a specific receiver antenna. The processing unit reconstructs an image of the object from the reception signal selected by the signal selection unit.

Abstract: The present invention relates to a magnetic resonance imaging (MRI) device. The basic components of an MRI device are the main magnet system (2), the gradient system (3), the RF system and the signal processing system. According to the present invention, the magnetic resonance imaging (MRI) device has an eddy current shield system, wherein the eddy current shield system comprises at least one perforated eddy current screen (13, 14), and wherein the or each perforated eddy current screen (13, 14) is assigned to the main magnet system (2).

Abstract: Tracking a boring tool is performed within an underground region using a locating signal. The boring tool is moved through the ground during a series of distance movements such that potential movement of the boring tool during any one of the distance movements is less than a maximum movement value. A current positional relationship is determined for a current one of the distance movements based on: a last-determined positional relationship established for an immediately preceding one of the distance movements, certain orientation parameters, the maximum movement value and the determined signal strength of the locating signal in the current positional relationship. Target coordinates are accepted and a target position, based on the target coordinates, is included as part of the current positional relationship. The position of the target is unconstrained with respect to system geometry. Steering command features are provided along with steering warnings.

Abstract: There is a ground-fault resistance measurement circuit which measures a ground-fault resistance between a conductive frame body of electrical equipment and a charge section insulated from the frame body. This ground-fault resistance measurement circuit includes: a capacity which is connected between the charge section and the frame body; a switch which opens and closes a connection path between the charge section and the capacity; a charging unit which charges the capacity to a predetermined voltage; a voltage measurement section which measures a charging voltage of the capacity; a discharge control section which connects the capacity and the charge section after the capacity is charged, and discharges the capacity; and a calculation section which calculates a resistance between the charge section and the frame body, based on a change in the charging voltage of the capacity.

Abstract: A system for detecting a defect or discontinuity in media or at an interface of the media includes a signal generator; a transmission path coupled to the signal generator, wherein the transmission path is arranged along or through the media; a detection circuit for detecting a transmitted and a detected portion of a signal provided by the signal generator; and a circuit for analyzing the reflected portion and identifying a location of a discontinuity or defect in the media. A related method of detecting a defect or discontinuity in media or at an interface between the media includes establishing an electromagnetic energy path along or through the media; coupling electromagnetic energy into the path; detecting a reflected portion of the electromagnetic energy; and analyzing the detected portion so as to determine a position of the defect or discontinuity.

Abstract: An automatic failed roll condom detection and removal apparatus wherein failed roll condoms are rapidly removed from a testing mandrel such that shut down of the testing and handling equipment is not required. Detection means detect the presence of a failed roll condom on a testing mandrel as it returns from the testing and removal station and ejection means remove the failed roll condom from the mandrel. The ejection means has a series of rotating brushes having relatively stiff bristles, the brushes being mounted on a reciprocating carriage in ascending manner in the mandrel return travel direction. When a failed roll condom is detected, the shuttle carriage return rate is slowed and the rotating brushes are brought into contact with the failed roll mandrel, each brush in succession pushing or rolling the condom higher on the mandrel until the final brush ejects the condom.

Abstract: Information handling system chassis RF shielding is accurately characterized in a repeatable and rapid manner with a stirring device disposed within the chassis. An RF signal from an RF signal source disposed in the chassis emits a more homogeneous and uniform field due to movement of reflective surfaces of the stirring device within the chassis. For example, an RF receiver located outside the chassis measures the RF signal received from the chassis over one or more complete revolutions of the stirring device to provide improved uniformity of the RF field maximized or averaged over each revolution. The reflective surface is interchangeable to support testing of shielding for chassis of different sizes and rotate vertically and horizontally to average out both vertical and horizontal polarization.

Abstract: One type of capacitive sensing apparatus has a sensing element that includes a first portion and a second portion adjacent opposite edges of a sensing region. Signals from the first and second portions are combined. Another type of apparatus includes: a first sensing element including first and second portions; a second sensing element including third and fourth portions; and a third sensing element including fifth and sixth portions. The first, third and fifth portions form a first pattern, and the second, fourth and sixth portions form a second pattern. The patterns are bilaterally symmetrical about a median of a sensing region. In another type of apparatus, an electrical conductor coupled to a first sensing element passes through a gap in a second sensing element. An electrical conductor coupled to the second sensing element is dimensioned such that a capacitive coupling to the second sensing element is compensated for the gap.

Abstract: Methods, systems and devices are described for detecting a measurable capacitance using charge transfer techniques. According to various embodiments, a charge transfer process is performed for two or more times. During the charge transfer process, a pre-determined voltage is applied to the measurable capacitance, and the measurable capacitance is then allowed to share charge with a filter capacitance through a passive impedance that remains coupled to both the measurable capacitance and to the filter capacitance throughout the charge transfer process. The value of the measurable capacitance can then be determined as a function of a representation of a charge on the filter capacitance and the number of times that the charge transfer process was performed. Such a detection scheme may be readily implemented using conventional components, and can be particularly useful in sensing the position of a finger, stylus or other object with respect to an input sensor.

Abstract: Provided is a current-mode semiconductor integrated circuit device that operates in a voltage mode during a test mode. The current-mode semiconductor integrated circuit device includes a first transmitting converter, a first receiving converter, a second transmitting converter, and a second receiving converter. During the test mode, one of a first signal path and a second signal path is selected according to the location of the chip. In the first signal path, the first transmitting converter, the first receiving converter, and the second transmitting converter operate. In the second signal path, the second transmitting converter, the second receiving converter, and the first transmitting converter operate. Each of the first and second transmitting converters receives a test voltage signal and converts it into a current signal. Each of the first and second receiving converters generates a reference voltage signal, compares it with the test voltage signal, and outputs the comparing result.

Abstract: A probe for an array of interconnecting leads between a PCA and an IC has one or more contacts extending laterally from or plated upon one or more arms formed of a flexible printed circuit, and connected by traces along the arm(s) to a header that itself affords connection to measurement equipment. The flexible printed circuit is thin enough to loosely slide between the top of the PCA or PCB and the bottom of the IC. The arm or arms is/are narrow enough to slide between the adjacent leads forming the array, while the normally flat contacts will successively interfere with, to engage and electrically contact, consecutive layers of leads as the probe is progressively inserted. An arm is not so stiff that it cannot yield by a slight compressive warping as the contacts encounter leads. Indexing may be ‘by feel’ or by visible indicia along a top surface of the probe or by a reticle device that moves over the top of the IC, which then has a pattern of indicia corresponding to lead location.

Abstract: A control unit of a wafer prober for implementing wafer examination, using a probe card including a multiple number of probes, executes a multiple number of measuring operations by bringing the probes of the probe card into contact with bonding pads formed on a wafer and by measuring the electric characteristics between predetermined pads of the bonding pads, each of the measuring operations being implemented after varying the relative position between the probe card and the wafer, in directions parallel to the face of the wafer. The control unit, upon execution of each of the measuring operations, implements the measuring operation after adjusting the relative position between the probe card and the wafer so that the contact position of each probe of the probes against each pad of the bonding pads is separated from all the positions at which the probes have already touched that pad of the bonding pads for a predetermined number of different times.

Abstract: A printed circuit board assembly has plural printed circuit boards that are mechanically and electrically connected to each other with them being stacked, and a connection layer that connects the adjacent two printed circuit boards to each other is provided. The connection layer includes an insulation portion and an electric conduction portion. The insulation portion contains an insulating member and is adhered to each of the adjacent two printed circuit boards. The electric conduction portion passes through the insulation portion and connects electrode terminals of the adjacent two printed circuit boards.

Abstract: A probe card mainly includes a circuit board, a probe assembly, an elastic support assembly, a plurality of level maintaining assemblies and a turning secure assembly. The circuit board has pads and spring bores. The probe assembly has a electrical signal transform board and probes on it. The elastic support assembly has a fixed plate, a locking plate and a plurality of springs. The springs are received in the spring bores of the circuit board to urge the electrical signal transform board for absorption of a height difference of the electrical signal transform board when the electrical signal transform board is inclined.

Abstract: Methods and apparatus are described for controlling orientation of a probe contact array relative to a wafer contact array on a wafer. The probe contact array is configured on a probe card having first kinematic reference features associated therewith. The wafer is positioned in a wafer prober having an interface with second kinematic features. The first and second kinematic features are together operable to restrain relative motion between the probe card and the wafer prober when the probe card and the interface are docked. The orientation of the probe contact array relative to the wafer contact array is determined. Where the probe contact array is out of alignment with the wafer contact array, a height of at least one of the kinematic reference features is adjusted to bring the probe contact array and the wafer contact array into substantial alignment.

Abstract: A semiconductor probe and a method of fabricating the same are provided. The semiconductor probe includes a cantilever doped with first impurities, a resistive tip which protrudes from an end of the cantilever and doped lightly with second impurities, doping control layers formed on both sides of a protruding portion of the resistive tip, and first and second electrode regions formed under the doping control layers and doped heavily with the second impurities.

Abstract: A temperature compensation circuit for effectively compensating the difference of a switching timing due to temperature change of a switching element included in a logic circuit is provided. The temperature compensation circuit includes a temperature detecting section for detecting a value corresponding to the temperature of the switching element, and a correction section for correcting the voltage of a logic signal inputted from a previous circuit to the logic circuit in order to reduce the difference of the switching timing due to the temperature change of the switching element based on the value corresponding to the temperature.

Abstract: A universal contact element for use on multiple handlers has a contactor body. A cavity is formed in a central area of the contactor body for holding semiconductor devices of a predetermined size. A first plurality of channels is formed in the cavity and extends through the contactor body. A plurality of contact pins is provided. A contact pin is positioned inside each of the first plurality of channels. A plurality of alignment pins is positioned around the outer perimeter of the contactor body outside of the cavity. The plurality of alignment pins is positioned around the top surface of the contactor body to conform to different alignment openings on multiple handlers. A retainer plate is coupled to a bottom surface of the contactor body for keeping the plurality of contact pins inside each of the plurality of first channels.

Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.

Abstract: When a test handler loads semiconductor devices of user trays onto a test tray, the test handler adjusts a front/rear pitch or a right/left pitch between the semiconductor devices, adjusts the right/left pitch or the front/rear pitch, and loads the semiconductor devices. The test handler can sequentially adjust individually the front/rear pitch and the right/left pitch between the semiconductor devices, thereby reducing the apparatus weight and the loading time.

Abstract: In a method of testing a semiconductor wafer, semiconductor chips of a predetermined number are selected from among a plurality of semiconductor chips formed on a semiconductor wafer, and a first test is performed on I/O pins of each of the selected semiconductor chips. Then, a second test is performed on a part of the I/O pins of each of non-selected semiconductor chips as ones of the plurality of semiconductor chips other than the selected semiconductor chips.

Abstract: The present invention provides an ID chip or an IC card in which the mechanical strength of an integrated circuit can be enhanced without suppressing a circuit scale. An ID chip or an IC card of the present invention has an integrated circuit in which a TFT (a thin film transistor) is formed from an insulated thin semiconductor film. Further, an ID chip or an IC card of the present invention has a light-emitting element and a light-receiving element each using a non-single-crystal thin film for a layer conducting photoelectric conversion. Such a light-emitting element or a light-receiving element may be formed consecutively to (integrally with) an integrated circuit or may be formed separately and attached to an integrated circuit.

Abstract: A method for testing a liquid crystal display panel wherein there are, disposed in matrix form, pixels comprising liquid crystal elements in which a liquid crystal material is sealed between opposing electrodes, this method for testing a liquid crystal display panel being characterized in that it comprises a first charging step for applying a first voltage between the opposing electrodes of the liquid crystal element of the pixel under test; a second charging step for applying a second voltage of the opposite polarity of the first voltage between the opposing electrodes of the liquid crystal element of the pixel under test; and a measuring step for discharging the charge that has accumulated in the electrodes of the liquid crystal element of the pixel under test after the second charging step, and measuring the amount of charge discharged.

Abstract: A meter connects to the input of a thermocouple-based RF signal power detector. The apparatus can sense its own load resistor DC impedance, so it can detect both aging in and damage sustained through overload to the RF dissipation element.

Abstract: Methods and apparatus provide for: selectively supplying a first source of power to a plurality of circuit blocks of a system using a plurality of gate circuits responsive to respective control signals provided by at least one control circuit; and providing a second source of power to operate the control circuit before the first source of power is available to the gate circuits such that the control signals are valid before such availability.

Abstract: A current/temperature measurement method using parasitic components in an electronic power circuit is disclosed. The measured values derived from these parasitic components with inadequate precision are first of all compensated for, in terms of their current/temperature or voltage dependence, during the production process. The evaluation which takes place during operation involves compensating for the temperature or current dependence of the sensor components using two measurements which are linearly independent of one another and appropriate arithmetic operations in an evaluation unit.

Abstract: An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Abstract: A semiconductor integrated circuit for matching the resistance of a variable resistor, which is used as a terminating resistor or a reference of said terminating resistor, to the characteristic impedance of a transmission line, has a terminating resistor adjusting circuit that has a current circuit connected to a power supply, said variable resistor that is connected between said current circuit and the ground and receives a main current output from said current circuit, a comparator circuit that compares the potential of the variable resistor with a first reference potential and outputs a signal, and a control circuit that controls the resistance of said variable resistor based on the output signal of said comparator circuit; and an additional current adjusting circuit that is connected between said power supply and said variable resistor and outputs an additional current to said variable resistor according to an external signal determined by the resistance of an external parasitic resistor between said term

Abstract: Provide is a molecular electronic device which includes a first electrode, a molecular active layer self-assembled on the first electrode using a thiol-based anchoring group or a silane-based anchoring group, and a second electrode including an organic electrode layer covering the molecular active layer. The organic electrode layer includes a highly conductive monomer, an oligomer or a polymer. The molecular active layer composes a switching element which is mutually switchable to states of ON and OFF according to voltages applied between the first electrode and the second electrode, and a memory element in which a predetermined electric signal is stored according to voltages applied between the first electrode and the second electrode.

Abstract: Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: An integrated circuit package (1) comprising first and second dies on a laminate (5) in a resin encapsulating housing (6) comprises a digital signal processing integrated circuit (8) fabricated on the first die (2), and a digital-to-analogue converting circuit (9) fabricated on the second die (3). First external terminals (16) are selectively coupled to corresponding first input terminals (10) of the digital signal processing circuit (8) through corresponding primary input switches (19), and first output terminals (11) of the digital signal processing circuit (8) are selectively coupled through primary output switches (23) and secondary input switches (25) to second input terminals (12) of the digital-to-analogue converting circuit (9). Second output terminals (13) of the digital-to-analogue converting circuit (9) are selectively coupled to second external terminals (17) through secondary output switches (30).

Abstract: An output circuit including: a tri-state output circuit capable of outputting high-impedance state, high-level state, and low-level state, in which the high-level state and low-level state are low-impedance state, and switching the high-impedance state and the low-impedance state in accordance with a first control signal; and a delay circuit outputting the first control signal to the tri-state output circuit by inputting a second control signal and delaying the second control signal so that timing delay time of the second control signal switching the high-impedance state to the low-impedance state is longer than the timing delay time of the second control signal switching the low-impedance state to the high-impedance state, is provided.

Abstract: The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.

Abstract: A power supply circuit and a control method are provided, in which the original enable pad and output pad, or the enable pad and feedback pad are used to trim the output voltage of the power supply circuit without extra trim pads.

Abstract: In a motor driving circuit in which a first NMOS and a second NMOS coupled in series to the final output stage to drive a motor are driven and a common node of the source of the first NMOS and the drain of the second NMOS serves as the final output, the motor driving circuit comprises: a first PMOS and a third NMOS having a common node of drains thereof coupled to the gate of the first NMOS; a second PMOS and a fourth NMOS having a common node of drains thereof coupled to the gate of the third NMOS; one or more PMOSs having drains coupled to the gate of the third NMOS which are turned on to charge the gate capacity of the third NMOS when the final output is low and a returned off when gate capacity of the third NMOS is charged; and one or more NMOSs having drains coupled to the gate of the third NMOS which are turned on to discharge the gate capacity of the third NMOS when the final output is high and are turned off when the gate capacity of the third NMOS is discharged and is characterized in that the gate o

Abstract: An output driver of a semiconductor memory device that operates in a differential mode and in a single mode is disclosed. The output driver includes a current supplying circuit that operates as a resistor in a single mode and as a current source in a differential mode. Accordingly, the semiconductor memory device including the output driver can have high test efficiency, since the number of test pins utilized during a test operation can be selectively reduced for low frequency tests.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a control circuit for outputting a control signal of which the logic level changes according to the result of logic evaluation performed by a replica of the evaluation circuit; and an initialization circuit for receiving the control signal from the control circuit and an external control signal, to control start and stop of initialization of the dynamic node according to the control signals.

Abstract: Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper and lower boundaries of the voltage swing at the dynamic node may be different from the upper and lower boundaries of the voltage swing at the output node. For example, the voltage swing at the dynamic node may be less than the voltage swing at the output node, optimized for speed or power consumption. As another example, the voltage swing at the dynamic node may be greater than the voltage swing at the output node, optimized for speed or power consumption. Further, the domino logic circuit may use dual Vt thereby reducing the short-circuit current during operation. Meanwhile, full voltage swing signals may be maintained at the inputs and outputs for high speed operation.

Abstract: Circuits are provided for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and a dual threshold voltage CMOS technology may be utilized to place idle domino logic circuits into a low leakage state. The circuits may significantly lower the total leakage power as compared to the standard dual threshold voltage domino logic circuits at both the high and low die temperatures. The energy overheads of the circuit techniques may be low, justifying the activation of the proposed sleep schemes by providing net savings in total power consumption during short idle periods.