Abstract: A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create A plasticity mechanism is also provided, which is based on a plasticity rule for creating stable connections from the plurality of self-assembling chains of nanoparticles for use with the universal, reconfigurable logic gate. The plasticity mechanism can be based, for example, on a 2-dimensional binary input data stream, depending upon design considerations. A circuit is also associated with the plurality of self-assembling chains of nanoparticles, wherein the circuit provides a logic bypass that implements a flip-cycle for second-level logic. Additionally, an extractor logic gate is associated with the plurality of self-assembling chains of nanoparticles, wherein the extractor logic gate provides logic functionalities.

Abstract: Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus employ programmable switches to emulate memory units that are used in LUTs and illustrate construction of 2- and 3-input LUTs as building blocks of other multi-input LUTs.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the finite input resistance. The third circuit may be configured to cancel the current by (i) generating the current in response to presenting the voltage across a replica resistor having a resistance similar to the finite input resistance and (ii) passing the current away from the apparatus.

Abstract: A current mode comparator for a semiconductor device is disclosed. The current mode comparator may include a logic circuit coupled to a voltage sensing node, a first cascode coupled to the voltage sensing node and a first power node, and a second cascode coupled to the voltage sensing node and a second power node. The logic circuit may convert a voltage of the voltage sensing node to an output signal.

Abstract: A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method performs the following steps. The indication provider generates an indicatory signal indicating a state of the optical storage system. The throughput rate detector generates a control signal in response to the indicatory signal. The clock generator generates the clock at the clock rate in response to the control signal. The clock rate determined by the clock rate adjustment apparatus may be adjusted dynamically in response to a required minimum clock rate and a variable data rate.

Abstract: Accurate correction of a local clock that avoids excessive drift in the local clock while avoiding an accumulation of quantization errors. A local clock according to the present techniques generates a local time by accumulating a sequence of rate coefficients selected from a plurality of rate coefficients using a series of progressively longer replacement periods.

Abstract: A method and integrated circuit for the transmission of differential signals with a signal and a complementary signal is disclosed. For trimming the edge steepness of the signal with that of the complementary signal, the integrated circuit has a first driver for generating the signal, and a second driver for generating the complementary signal. A circuit is provided, configured to control the edge steepness of the signal or of the complementary signal.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to?1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Abstract: A semiconductor memory device comprises a n-channel type MOSFET in which a drain and a gate are connected to an external power supply and a source and a back gate are connected each other, a node connected to the source and the back gate of the n-channel type MOSFET, and a detector for detecting an input of the external power supply based on a potential of the node

Abstract: A differential charge pump with common mode and active regulators is presented. Either type of regulator may be used to improve the performance characteristics of the differential charge pump. The active regulator increases the output range of the differential amplifier. The common mode regulator establishes the common mode voltage of the differential charge pump. The common mode voltage is established independently from external circuitry and does not use a feedback path. The common mode regulator may also be used to establish a mid-rail voltage, which may be used to further improve the output range of the differential amplifier.

Abstract: A delay-locked loop (DLL) circuit has a reference signal input for a receiving a periodic reference signal and a number of signal outputs for outputting respective output signals derived from the reference signal and having a desired phase relationship with one another. The DLL circuit comprises a voltage controlled delay line (VCDL) comprising a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number of stages matches the period of the periodic reference signal. Signal outputs are connected to derive their respective output signals from respective nodes within said delay line. The phase comparator compares the phase of first and second differently delayed versions of the reference signal from respective nodes within the variable delay line separated only by a plurality of identical delay stages. Duty cycle distortion is minimised as a result.

Abstract: A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

Abstract: Three flip-flops receive a common data signal input through a data terminal based on different timing signals which are obtained from an external timing signal and differ from one another by a specific delay step. A judging circuit judges whether or not the output data of the three flip-flops coincide with one another. If all the output data coincide with one another, the latch timing is maintained, whereas if the output data of the flip-flop latching the data signal at a fastest or latest timing differs from the output data of the flip-flop latching the data signal at the central timing, the judging circuit changes the variable timing to obtain a suitable latch timing.

Abstract: A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.

Abstract: Systems and methods for pulse width modulating waveforms to represent asymmetric signal levels using pulses that are symmetric within their respective switching periods. One embodiment comprises a pulse width modulation system including an asymmetric correction unit and a pair of modulators. The asymmetric correction unit receives samples of an input signal and produces two separate output signals for corresponding modulators. For each sample, the asymmetric correction unit determines whether the signal level of the sample is symmetric or asymmetric. If the signal level of the sample is symmetric, the sample is forwarded to each of the modulators. If the signal level is asymmetric, the asymmetric correction unit increases one modified sample to the next higher symmetric signal level and decreases another modified sample to the next lower symmetric signal level and forwards the modified samples to the modulators.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: Integrated circuit and process for aligning a first signal with a second signal. The integrated circuit includes a single latch, a switch control circuit coupled to an input of the single latch to align an edge of the first signal with an edge of the second signal, and a second switch control circuit coupled to the output of the single latch to produce a 50% duty cycle output.

Abstract: A tunable multiple frequency source system employing offset signal phasing includes a first frequency source, a phase delay element, and a second frequency source configured to operate concurrently with the first frequency source. The first frequency source includes an input coupled to receive a reference input signal and an output for providing a first frequency source signal. The phase delay includes an input coupled to receive the input reference signal, and an output, the phase delay element operable to apply a predefined phase delay to the input reference signal to produce a phase-delayed input signal. The second frequency source includes an input coupled to receive the phase-delayed input signal and an output for providing a second frequency source signal.

Abstract: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.

Abstract: Methods and circuits are provided for controlling a signal applied to a control terminal of a variable voltage attenuator. In one embodiment, a method comprises detecting an output signal of the variable voltage attenuator, generating a logarithm of the detected output signal of the variable voltage attenuator, and generating the signal applied to the control terminal of the variable voltage attenuator at least partially based on the logarithm of the detected output signal of the variable voltage attenuator.

Abstract: A level translator for translating a digital signal from a first voltage level to another voltage level having a higher voltage assigned to the high state of the signal comprises a latch and a pair of N-MOS transistors being coupled to the latch. This design is improved in that the N-MOS transistors are native thick oxide N-MOS transistors, each having a thin oxide layer N-MOS transistor coupled to native thick oxide transistors for reducing leakage current and improving speed in the transient state.

Abstract: A monolithic interface circuit for providing a voltage, from a control circuit supplied by a supply voltage referenced to a reference voltage, to a terminal likely to be at a high voltage with respect to the reference voltage, comprising a high-voltage N-channel MOS transistor having its gate intended to receive a control signal referenced to the reference voltage and having its source intended to be connected to the reference voltage, and a high-voltage PNP transistor having its base connected to the drain of the MOS transistor, having its emitter intended to receive the supply voltage and having its collector intended to provide a voltage to the terminal likely to be at a high voltage.

Abstract: A level shifter circuit, which includes a Schmitt trigger function, shifts voltage of a high level signal into a low voltage and shifts a signal at an intermediate value of an input voltage. The level shifter circuit includes an input terminal connected to low and high voltage circuits. The low voltage circuit outputs a low drive voltage or ground voltage. The high voltage circuit outputs a high drive voltage or a high reference voltage, which is supplied to an RS latch circuit via a potential adjustment circuit at a level equal to an output potential at the low voltage circuit. The RS latch circuit uses the output of the potential adjustment circuit when the input voltage shifts to a high level and uses the output of the low voltage circuit when the input voltage shifts to a low level.

Abstract: A device and method for temperature compensation of an electronic device are disclosed. The device includes a temperature bias controller with a temperature sensor. A bias signal based upon a signal from the temperature sensor is provided to a first gate of a multiple fin gate field effect transistor (multigate FinFET) transistor of a functional block. A second gate of the multigate FinFET transistor receives a control signal to control its operation within the functional block. In this configuration the first gate of the multigate FinFET transistor can be used for temperature compensation while the second gate is used for functional operation of the transistor. Specific embodiments of the present disclosure will be better understood with respect to the figures.

Abstract: A smart card includes a power source, a processing chip, and a charge-pump subsystem for powering the processing chip. The charge-pump subsystem includes a capacitor which is connected cyclically to the power source to charge the capacitor, to the processing chip to power the processing chip, and to ground to discharge the capacitor. The charge-pump subsystem can include three such capacitors so that while one of them is charging, another is powering the processing chip, and a third is discharging. The charge-pump subsystem blocks attempts to discover a secret key in the processing chip by decorrelating power consumption from the internal operations of the processing device.

Abstract: In a charge pump circuit, the through rate at which a clock signal is fed to charge transfer transistors is changed according to the output voltage. This configuration helps alleviate rush currents at start-up without unduly lowering efficiency.

Abstract: An apparatus and method for regulating voltage levels. The apparatus includes a first transistor and a second transistor. The first transistor and the second transistor are each coupled to a first current source and a second current source. Additionally, the apparatus includes a third transistor coupled to the second transistor and configured to receive a first voltage from the second transistor, and a fourth transistor configured to receive the first voltage from the second transistor and generate an output voltage. Moreover, the apparatus includes an adaptive system coupled to the fourth transistor. Also, the apparatus includes a delay system coupled to the third transistor and configured to receive a sensing current from the third transistor and generate a delayed current associated with a predetermined time delay. Additionally, the apparatus includes a current generation system.

Abstract: A semiconductor integrated circuit apparatus and an electronic apparatus having a power control function configured from power control MOS transistors in such a manner that leakage current and on resistance at the time of cut-off is sufficiently small in actual use. Semiconductor integrated circuit apparatus is comprised of a CMOS logic circuit, a second pseudo power supply line connected to a low potential side power supply terminal of the CMOS logic circuit, and a power control NchMOS transistor connected across a second pseudo power supply line and a low potential side power supply line, with the substrate and gate of power control NchMOS transistor being electrically connected. The gate and the substrate may also, for example, be connected via a current limiter utilizing, for example, a source follower of a depletion type NchMOS transistor.

Abstract: A coupling capacitor for converting the DC level between circuits is incorporated into a semiconductor integrated circuit to reduce the number components. A high-pass filter (34) having a cutoff frequency fC is composed of a coupling capacitor C1 that cuts off direct current between circuits (22) and (24), and a switched capacitor circuit (28) constituting an equivalent resistor RSC. If the switching frequency fSC or the capacitance CSC charged and discharged by the switched capacitor circuit (28) is set low, the RSC can be increased and the C1 at the prescribed fC can be reduced proportionately. Accordingly, the high-pass filter (34) having the C1 can be integrated onto the chip of the IC (20).

Abstract: A differential amplifier comprises first, second, and third input terminals (1, 2, and 3), output terminal (4), first and second differential pairs (531 and 532) (533 and 534) driven by a corresponding current source and having output pairs commonly connected to load circuits (537 and 538), and an amplifier stage (539) having input end connected to at least one of the common connection points of the load circuits and output pairs of the first and second differential pairs and output end connected to output terminal. Input pair of second differential pair receives a signal from third input terminal and a feedback signal from output terminal.

Abstract: I Embodiments of the present invention relate to a modulation system in which an m-level, m>2, digital subcarrier is used to modulate a signal.

Abstract: A switched distributed power amplifier includes an amplifier stage that includes a first amplifier subsection and a second amplifier subsection, both including one or more field effect transistors (FETs). Each FET in the first amplifier subsection is coupled to a radio frequency (RF) input terminal. Each FET in the second amplifier subsection is coupled to the RF input terminal through an input delay element, which includes a first inductor, a first capacitance associated with gates of the FETs in the first amplifier subsection, a second capacitance associated with gates of the FETs in the second amplifier subsection, and a third capacitance associated with a capacitor coupled to the RF input terminal. The input delay element is designed such that the sum of the first and third capacitances is equal to the second capacitance. A shunt switch prevents the second amplifier subsection from turning on during a low power mode.

Abstract: A feed-forward amplifier having a signal cancellation loop including a cancellation node that includes a gain controller and a phase controller. Each controller provides a discrete tap steering signal and modulates the corresponding tap steering signal with a discrete tracer signal that takes on a preselected sequence of values. The sequence chosen so that the tracer signal is mutually orthogonal to each other tracer signal over a preselected period. A gain and phase adjuster connected to the outputs of the controllers provides a controlled gain change and phase shift in the signal cancellation loop, the magnitude of the gain change and phase shift controlled by the corresponding tap steering signals presented to the gain and phase adjuster by the controllers. A detector, the input of which is connected to the cancellation node and the output of which is connected to the controllers, outputs a measure of the envelope of the signal at the cancellation node.

Abstract: A radio system for communication is provided that has a differential amplifier for amplifying a transmission frequency, particularly 2.4 GHz, wherein the differential amplifier has a first inductor, which is magnetically coupled to a second inductor, and a capacitor. The capacitor, the first inductor, and the second inductor are wired into a resonant circuit in such a way that the resonant circuit has a common-mode impedance for a common-mode signal and a push-pull impedance, different from the common-mode impedance, for the push-pull signal.

Abstract: An operational transconductance amplifier (OTA) includes a first, a second and a third differential units, a voltage-to-current converting unit and a current subtraction device. The first and the second differential units receive a differential input voltage and the voltage-to-current converting unit converts it into an output current. The OTA adopts a replica scheme, that is, by copying the first differential unit to generate a third differential unit and then performs a subtraction between the first output current from the first differential unit and the second output current from the third differential unit in order to eliminate the static current component in the output current. In addition, since the first and the third differential units have the same layout, the output current will not vary with the channel length modulation of transistors, and the static current component in the output current can be eliminated completely.

Abstract: A transmission power control apparatus which reduces the number of steps required for adjustments of the transmission power control apparatus and performs transmission power control with high accuracy in a wide dynamic range. The apparatus has a first variable amplifying circuit (122) with the resolution of 1 dB and a second variable amplifying circuit (123) with the resolution of 0.

Abstract: An object of the invention is to provide a receiving circuit where the quality of reception can be prevented from deteriorating when the gain changes, so that the good quality of the received signal can be preserved, as well as a receiving apparatus and a transmitting/receiving apparatus using the receiving circuit. In the configuration of the invention, a switch (113) is converted to a short state in response to a change in the gain of a variable gain amplifier (107) by means of a gain control apparatus 112, and thereby, the output terminal of a high pass filter (111) is fixed at a reference voltage and the cutoff frequency of a low pass filter (108) is increased. As a result, the period during which the DC voltage has transient response properties in the low pass filter (108) can be shortened, and this transient response prevented from passing through the high pass filter (111).

Abstract: A variable gain amplifier of the present invention connects an input and an output of a first variable gain amplifier circuit to an RF input terminal and an RF output terminal, respectively, connects one terminal of an attenuation circuit is to an RF input terminal, connects an input and an output of a second variable gain amplifier circuit to the other terminal of the attenuation circuit and an RF output terminal, respectively, connects one terminal of the variable resistance circuit to a node between the attenuation circuit and the second variable gain amplifier circuit, and grounds the other terminal of the variable resistance circuit. A gain of the first variable gain amplifier circuit, a gain of the second variable gain amplifier circuit, and a resistance value of the variable resistance circuit are then varied by a gain control voltage outputted from a gain control section.

Abstract: A waveform equalizer includes: a calculation circuit (7a) that permits free setting of the boost factor by which the gain, in a predetermined frequency range, for the input signal by varying the boost factor; and an all-pass filter (7b) that is connected to the stage preceding or following the calculation circuit, that has a first conductance amplifier and a second conductance amplifier, and that adjusts and thereby corrects the group delay characteristic of the input signal by varying the conductance of at least one of the first and second conductance amplifiers.

Abstract: A high-performance Peltier-cooled single-channel millimeter-wave low-noise amplifier (LNA) capable of operating over an on-orbit operating temperature range of ?40° C. to +80° C. with a noise figure on the order of 1.5 dB.

Abstract: This invention relates to a low noise amplifier, used in radio frequency integrated circuit design, especially low noise amplifiers for ultra broad-band wireless communication, comprising at least a transistor of the core circuit of a low noise amplifier structure, a transformer that is implemented on the chip, in order to form a dual feedback amplifier, that is, an amplifier structure comprising an inductive feedback and a capacitive feedback, wherein the capacitive feedback is used for the low and medium frequency range, while the inductive feedback is used for the high frequency range. By assembling an amplifier circuit with these two feedback paths, it is possible to provide a broadband and good impedance matching at the signal input end of the circuit.

Abstract: Disclosed is a power amplifier having highly stable and excellent controllability, and having low noise in comparison with conventional power amplifiers. With the power amplifier, a differential amplifier made up of transistors Q1, Q2 is provided in the initial stage thereof, and baluns doubling as inter-stage matching circuits, comprised of Cp1, Cp2, Lp1, and Ct1, Ct2, Lt1, respectively, are provided between the initial stage, and a second stage while an unbalanced single-ended circuit is provided in the second stage. The differential amplifier has an emitter-coupled type configuration for coupling both emitters with each other, and output control of the amplifier in the initial stage is executed by varying current of a current source coupled to both the emitters.

Abstract: Power amplifier (PA) apparatus that includes: a PA device operating at a fundamental frequency and having a maximum operating frequency that is higher than the fundamental frequency, an output current having a fundamental component at the fundamental frequency and a plurality of harmonic components at different harmonic frequencies of the fundamental frequency, and an output voltage based on the output current; a first matching circuit coupled to the PA device and corresponding to the fundamental component; and a second matching circuit coupled between the PA device and the first matching circuit and corresponding to at least one of the harmonic components, wherein the first and second matching circuits maintain the PA output voltage at a value that is no more than a predetermined maximum value, which is less than a breakdown voltage for the PA device.

Abstract: A power supply apparatus for supplying predetermined supply voltages respectively to an anode electrode, a cathode electrode, a collector electrode, and a helix of an electron tube. The power supply apparatus comprises an anode switch for turning on/off the anode voltage output, and an anode switch control circuit for controlling the on/off operation of the anode switch such that a pulsed anode voltage is repeatedly applied to the anode electrode a plurality of times at a predetermined period when operation of a helix power supply and a collector power supply is stopped.

Abstract: A crystal oscillator emulator integrated circuit, comprises a first temperature sensor that senses a first temperature of the integrated circuit; memory that stores calibration parameters and that selects at least one of the calibration parameters based on the first temperature; a semiconductor oscillator that generates an output signal having a frequency that is based on the calibration parameters; and an adaptive calibration circuit that adaptively adjusts a calibration approach for generating the calibration parameters based on a number of temperature test points input thereto.

Abstract: A technique provides a clock source that meets accuracy requirements, allows the use of a low cost resonator, provides a wide range of output frequencies, and provides suitable phase noise performance. The technique generates a clock signal having a target output frequency using a controllable oscillator having at least one continuous frequency range of operation. The technique dynamically adjusts a reference control value based on a voltage for adjusting a frequency of the clock signal around a frequency determined by the reference control value. The reference control value is adjusted to be approximately within the center of an actual pull range corresponding to the controllable oscillator and a voltage control input of the controllable oscillator. The effective pull range of the controllable oscillator is continuous across the at least one continuous frequency range of operation.

Abstract: A clock signal generating circuit is provided. The clock signal generating circuit includes a clock signal generator for generating a first clock signal having a predetermined frequency; a frequency dividing circuit receiving the first clock signal, for providing a second clock signal with a frequency that is lower than the predetermined frequency of the first clock signal; and a frequency multiplier circuit receiving the second clock signal, for providing a system clock signal resuming the predetermined frequency to a load.