Abstract: A stacked MCM is manufactured at reduced cost without using expensive apparatus. A first wiring and a second wiring are formed on a surface of a semiconductor chip of a first semiconductor device through an insulation film. A glass substrate having an opening to expose the second wiring is bonded to the surface of the semiconductor chip on which the first wiring and the second wiring are formed. A third wiring is disposed on a back surface and a side surface of the semiconductor chip through an insulation film and connected to the first wiring. And a conductive terminal of another semiconductor device is connected to the second wiring through the opening.

Abstract: Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices are disclosed herein. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The microelectronic workpiece of this embodiment further includes a protective layer over the backside of the substrate. The protective layer is formed on the backside of the substrate from a material that is in a flowable state and is then cured to a non-flowable state.

Abstract: The invention relates to a method of transferring useful layers from a donor wafer which includes a multi-layer structure on the surface of the donor wafer that has a thickness sufficient to form multiple useful layers for subsequent detachment. The layers may be formed of materials having sufficiently different properties such that they may be selectively removed. The layers of material may also include sub-layers that can be selectively removed from each other.

Abstract: A manufacturing method of a thin film transistor of a liquid crystal display device using 3-mask includes forming a gate electrode over a substrate, consecutively forming a gate insulating layer and an active layer, forming a first photoresist pattern, removing an active layer formed at a source/drain region, ashing the first photoresist pattern to expose a part of an active region, forming a source/drain electrode, forming a passivation layer, forming a second photoresist pattern that exposes a pixel region over the passivation layer; forming a pixel region by using the second photoresist pattern as a mask, side-etching a part of the passivation layer to expose a part of the drain electrode, forming a pixel electrode material over the second photoresist pattern and the pixel region, and simultaneously removing the second photoresist pattern and the pixel electrode material formed thereon to form a pixel electrode.

Abstract: A method of forming a semiconductor device includes forming a first layer over a semiconductor substrate and forming a second layer over the first layer. The second layer includes silicon and has an etch selectivity to the second layer that is greater than approximately 1,000. In one embodiment, the second layer is a porous material, such as porous silicon, porous silicon germanium, porous silicon carbide, and porous silicon carbon alloy. A gate insulator is formed over the second layer and a control electrode is formed over the gate insulator. The first layer is selectively removed with respect to the second layer and the semiconductor substrate.

Abstract: An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and the second-type FinFET are planar with each other. A first region of the BOX layer below the first FinFET fin is thicker above the substrate when compared to a second region of the BOX layer below the second FinFET fin. Also, the second FinFET fin is taller than the first FinFET fin. The height difference between the first fin and the second fin permits the first-type FinFET to have the same drive strength as the second-type FinFET.

Abstract: The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped region. According to the present invention, plural TEGs are manufactured as Lov resistance monitors in which mask alignment is misaligned with several ?m interval to perform a resistance measurement on each of the TEGs. Consequently, a resistance distribution corresponding to a tapered shape can be obtained in a channel forming region, a gate-overlapped region and a source/drain region.

Abstract: A method of fabricating a thin film transistor includes preparing an insulating substrate; forming a first amorphous silicon layer on the substrate; forming a diffusion barrier layer pattern on the first amorphous silicon layer; forming a second amorphous silicon layer over the whole surface of the substrate; forming a metal silicide layer on the second amorphous silicide layer; and heat-treating the substrate to form first and second polysilicon layers.

Abstract: A semiconductor device is provided with a stressed channel region, where the stresses film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surround the channel region, and may apply stress from all sides of the channel. Consequently, the stress film better surrounds the channel region of the semiconductor device and can apply more stress in the channel region.

Abstract: A method of manufacturing a semiconductor device that provides a semiconductor device having improved channel mobility includes a process of forming a gate insulation film of silicon oxide film, silicon nitride film or silicon oxide nitride film or the like on a silicon oxide substrate, and following formation of the gate insulation film on the silicon oxide substrate with heat treatment for a given time at a temperature range of 900° C. to 1000° C. in an atmosphere containing not less than 25% H2O (water).

Abstract: A method of making a semiconductor structure includes depositing a nitride layer, on a metallic layer, by PECVD. The metallic layer is on a gate layer containing silicon, and the gate layer is on a semiconductor substrate.

Abstract: An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.

Abstract: A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentially forming a tunnel insulating film and a charge-storable film so as to cover active regions between the element isolation regions; forming an interlayer insulating film on the charge-storable film; forming plural control gates on the interlayer insulating film in a direction orthogonal to a longitudinal direction of the trenches; among source formation regions and drain formation regions alternately provided between the plural control gates, etching the element isolation insulating film in the source formation regions, using as a mask a resist film having openings in the source formation regions, to expose surfaces of the trenches; and carrying out isotropic plasma ion implantation on the source formation regions to form source diffusion layers in

Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

Abstract: In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

Abstract: A semiconductor device of the present invention includes capacitors made up of a lower electrode, a capacitive insulation film made from metal oxide material, provided on one surface of a semiconductor substrate. An ozone TEOS film is provided on these capacitors, and a protective film for covering the upper surfaces of the capacitors is then provided on this ozone TEOS film. An interlay insulation film that is thicker than the ozone TEOS film is provided on the protective film for covering the upper surfaces of the capacitors. In this way, the present invention prevents degradation in film quality of the capacitive insulation film due to mutual reaction etc. As a result, it becomes possible to provide a capacitor using an insulating film made of a metal oxide as a capacitive insulation film, having a protective film for sufficiently preventing diffusion of H2, a semiconductor device having high reliability, and a method of manufacturing such a semiconductor device, are provided.

Abstract: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.

Abstract: Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.

Abstract: In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation pattern to partially fill up the opening. A sacrificial layer is formed on the preliminary polysilicon layer. The sacrificial layer is partially etched to expose a portion of the preliminary polysilicon layer formed on a shoulder portion of the isolation pattern. A first polysilicon layer is formed by etching the exposed portion of the preliminary polysilicon layer to enlarge an upper width of the opening. After the etched sacrificial layer is removed, a second polysilicon layer is formed on the first polysilicon layer to fill up the enlarged opening.

Abstract: A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.

Abstract: A method of forming a device (and the device so formed) comprising the following steps. A structure having a gate structure formed thereover is provided. Respective low doped drains are formed within the structure at least adjacent to the gate structure. A pocket implant is formed within the structure. The structure adjacent the gate structure is etched to form respective trenches having exposed side walls. Respective first liner structures are formed at least over the exposed side walls of trenches. Respective second liner structures are formed over the first liner structures. Source/drain implants are formed adjacent to, and outboard of, second liner structures to complete formation of device.

Abstract: A method for forming a dopant in a substrate, by accumulating at least one dopant species in an asher chamber and forming the accumulated dopant species on an exposed portion of the substrate. A target concentration for the plasma chamber dopant species is determined by test or measurement. The asher is used to form the dopant species on the substrate, and the dopant species is driven into the substrate. A threshold voltage is measured on the substrate to verify or confirm that a proper dopant level has been achieved.

Abstract: A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.

Abstract: A method of manufacturing a semiconductor device having a dual-damascene gate including forming LDD regions by forming a gate oxide film on a semiconductor substrate, and by implanting lowly-concentrated impurities in the semiconductor substrate in accordance with a predetermined LDD pattern, and forming a nitride film on the gate oxide film, and forming a wide nitride film in accordance with the wide nitride pattern. The method also includes forming a narrow nitride film by a narrow etching process on the wide nitride film in accordance with a predetermined narrow nitride film pattern, forming a dual-damascene gate by depositing a polysilicon layer on an exposed entire surface and smoothing the deposited polysilicon layer to a top surface of the nitride film, and forming a gate electrode by removing a predetermined region of the polysilicon layer.

Abstract: A method of making a memory device and a memory device is described. In one embodiment, a method of manufacturing a memory device is described. The method includes providing a substrate having a tunneling layer deposited on a main surface and having a first conductive lines arranged on the tunneling layer running in a first direction. A layer of dielectric material is deposited on the first conductive lines. A control gate layer is deposited. The first conductive lines are patterned to produce gate stacks. Dielectric material is deposited in between the gate stacks. The gate stacks are partially removed to uncover floating gate electrodes in region of selection transistor lines to be prepared creating selection transistor line recesses running in the second direction. The selection transistor line recesses are filled with a conductive material to create the selection transistor lines.

Abstract: A first electrode and a second electrode to be used are electrodes each of which has a collector, and a porous material layer with electron conductivity placed between the collector and a separator, and each of which has a configuration wherein the porous material layer includes at least particles of a porous material with electron conductivity, and a thermoplastic resin being capable of binding the particles of the porous material together and having a softening point TB lower than a softening point TS of the separator. A production method includes a thermal treatment step of thermally treating a laminate at a thermal treatment temperature T1 satisfying a condition represented by Formula (1): TB?T1<TS, thereby bringing the collector of the first electrode, the porous material layer of the first electrode, the separator, the porous material layer of the second electrode, and the collector of the second electrode in the laminate into an integrated state.

Abstract: A semiconductor substrate including a first region, a second region larger than the first region and an isolation region is provided. A mask layer is selectively formed on the first and second regions. A trench is formed on the isolation region. A first isolation material is deposited on the entire surface so that the trench is filled with the first material and the first material covers the first and second regions. The first material is subjected to a chemical mechanical polish so that the mask layer formed on the first region is exposed while the mask layer formed on the second region is still covered by the first material. Then, a second insulation material is deposited on the exposed mask layer and the first material. Finally, the second material is subjected to the chemical mechanical polish so that mask layer formed on the first and second regions is substantially exposed.

Abstract: Methods for preparing a semiconductor assembly are disclosed. In an implementation, the technique includes providing a support substrate and a bonding surface thereon, providing a donor substrate having a weakened zone that defines a useful layer and a bonding surface on the useful layer, and providing an interface layer of a predetermined material on the bonding surface of either the support substrate or the useful layer to provide a bonding surface thereon. The method also includes molecularly bonding the bonding surface of the interface layer to the bonding surface of the other of the support substrate or the useful layer to form a separable bonding interface therebetween, and to thus form the semiconductor assembly, and heat treating the semiconductor assembly to a temperature of at least 1000 to 1100° C.

Abstract: An object of the present invention is to prevent the thin film device formed by laser annealing from making, due to overheat, abnormal operations. Firstly, on a glass substrate 101. a heat insulating film, a silicon oxide film and an amorphous silicon film are formed in succession, and the amorphous silicon film is irradiated from above with a laser beam of an excimer laser. After being molten, the amorphous silicon film undergoes recrystallization to form a polycrystalline silicon film. Subsequently, using the polycrystalline silicon film as an active layer, a TFT is formed, and then a plastic substrate is bonded onto the TFT, and finally the glass substrate is peeled off by way of the heat insulating film, whereby a transfer of the TFT is completed. Because the heat insulating film is removed, abnormality caused by overheat at the time of operation is well prevented from occurring.

Abstract: The invention relates to a method for manufacturing a compound material wafer. The technique includes forming a weakened zone in a source substrate, attaching the source substrate to a handle substrate to form a source-handle assembly, and thermally annealing the source-handle assembly to further weaken the weakened zone. The method also includes holding the assembly at a holding temperature, and detaching the source substrate from the assembly at the weakened zone at the holding temperature. The holding temperature is greater than room temperature but does not promote further weakening of the weakened zone.

Abstract: An SOI substrate which has a thick SOI layer is first prepared. Then, the SOI layer is thinned to a target film thickness using as a unit a predetermined thickness not more than that of one lattice. This thinning is performed by repeating a unit thinning step which includes an oxidation step of oxidizing the surface of the SOI layer by the predetermined thickness not more than that of one lattice and a removal step of selectively removing silicon oxide formed by the oxidation. The SOI layer of the SOI substrate is chemically etched by supplying a chemical solution to the SOI layer, and the film thickness of the etched SOI layer is measured. When the measured film thickness of the SOI layer has a predetermined value, a process of chemically etching the SOI layer ends.

Abstract: A semiconductor substrate having a first substrate surface which includes a device area in which semiconductor devices are formed and a substrate peripheral portion which does not overlap with the device area. A concavo-convex portion is formed in the substrate peripheral portion. Preferably, a concavo-convex portion is formed in a side portion which adjoins the peripheral portion. The concavo-convex portion formed in the substrate peripheral portion or the side portion may be formed by a method such as dry etching, wet etching, mechanical grinding, electrolytic plating, nonelectrolytic plating, or patterning using one of a resin material and a metal material. A thin processing method includes forming the device area; forming the concavo-convex portion in the substrate peripheral portion; adhering the first substrate surface to a support; and grinding a second substrate surface of the semiconductor substrate, which is opposite with the first substrate surface.

Abstract: The present invention relates to a method for dividing a substrate into a number of individual chip parts, comprising the steps of: forming a number of chip parts in the substrate, comprising, for each chip part, of arranging recesses in the substrate for containing fluid; arranging one or more breaking grooves in the substrate along individual chip parts; applying mechanical force to the substrate to break the substrate along the breaking grooves. The invention also relates to a substrate as well as a chip part.

Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.

Abstract: An anti-warpage backgrinding tape (11) is secured to the circuit side (12) of a semiconductor wafer (14). The backside (16) of the wafer is background. The backside of the wafer is secured to dicing tape (18) so that the anti-warpage backgrinding tape is exposed. The wafer is diced to create individual die structure (34). The die structure comprises semiconductor die (22) with anti-warpage tape elements (36) on circuit sides of the semiconductor die. A die structure is removed from the dicing tape. The backside of the die of the die structure is adhered to a substrate (24). The anti-warpage tape element is removed from the die. The anti-warpage backgrinding tape is preferably partially or fully transparent to permit sensing of guide markings on the wafer during wafer dicing. The adhesive is preferably a curable adhesive. The adhesion between the anti-warpage tape element and the chosen die may be reduced by the application of heat (38).

Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.

Abstract: A method of growing a crystal (for example, a GaN system compound semiconductor crystal) on a substrate at least includes forming a first crystalline layer (a GaN system buffer layer), forming a second crystalline layer (a GaN system intermediate layer) and forming a third crystalline layer (a GaN system thick film layer). The three crystalline layers are respectively reared on conditions different from one another.

Abstract: Embodiments of the present invention relate to an apparatus and method of annealing substrates in a thermal anneal chamber and/or a plasma anneal chamber before electroless deposition thereover. In one embodiment, annealing in a thermal anneal chamber includes heating the substrate in a vacuum environment while providing a gas, such as noble gases, hydrogen gas, other reducing gases, nitrogen gas, other non-reactive gases, and combinations thereof. In another embodiment, annealing in a plasma chamber comprises plasma annealing the substrate in a plasma, such as a plasma from an argon gas, helium gas, hydrogen gas, and combinations thereof.

Abstract: An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening.

Abstract: A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.

Abstract: A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are then exposed to an oxide deposition bath, thereby causing deposition of oxide on those surfaces. Deposition of oxide on the top surface causes growth of the cap layer in a vertical direction and deposition of oxide on the side surface causes growth of the cap layer in a horizontal direction, thereby forming the beanie structure.

Abstract: A method and apparatus are disclosed for forming a tapered contact structure over a contact pad. The tapered contact structure may be used to securely anchor an overlying solder bump or solder ball. Additionally, the tapered contact structure allows the use of either larger contact pads or, alternately, allows a greater density of contact pads to be achieved on an integrated circuit substrate.

Abstract: A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the die, forming a plurality of interconnect contacts on the redistribution contacts, and forming an insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming terminal contacts on the interconnect contacts, or alternately forming conductors in electrical communication with the interconnect contacts and then forming terminal contacts in electrical communication with the conductors.

Abstract: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is evaluated to determine whether a volume of last solidification for the solder is centrally located with respect to the die pad and is located at or near an interface of the solder and the die pad. If the last solidification volume is centrally located and is located at or near the interface of the solder and the die pad, and if the die pad is delaminated from the die, the structure design is modified so that less metal of the heat sink member is centrally located than before the modifying.

Abstract: A semiconductor element is formed over a surface of a semiconductor substrate. A first insulating film is formed over the surface of the semiconductor substrate, the first insulating film covering the semiconductor element. A second insulating film is formed over the first insulating film, the second insulating film having a dielectric constant lower than that of the first insulating film. A first wiring pattern is formed over the second insulating film. A conductive connection member buried in the second and first insulating films electrically interconnects the first wiring pattern and semiconductor element.

Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

Abstract: A method of forming a metal layer with reduced defects comprising providing a structure having a dielectric layer formed over it, forming a dielectric layer having an opening, lining the opening with a metal seed layer, treating the metal seed layer with a cleaning process to remove contaminates from it, and forming a metal layer upon the metal seed layer.

Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Abstract: The present invention provides a Cu line and method of forming the same, by which reliability (e.g., EM, BTS and the like) can be enhanced by replacing SiN by HfOx, which plays a role as a protective layer and/or an etch stop layer on a Cu line, prevents or inhibits galvanic corrosion due to Cu oxide, and inhibits or reduces additional formation of Cu oxide by gathering or scavenging oxygen atoms from —OH, O2, and H2O. The present method includes the steps of forming a trench in an insulating layer on a substrate, forming a planarized Cu layer in the trench, forming a HfOx layer on the planarized Cu layer, and thermally treating the substrate.

Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.