Abstract: A network analysis system and methods facilitate a match-corrected signal power measurement using a vector network analyzer (VNA). The network analysis system includes the VNA and a computer program stored in memory and executed by a controller. The computer program has instructions that implement one or both of calibrating a test port of the VNA to determine the match-corrected signal power measurement and correcting a power measured for a signal received at the test port of the VNA using corrected error terms of a port calibration of the test port to yield a corrected measured power. The corrected error terms are determined from error terms of the port calibration using a switch term and an incident power calibration, both of the test port. A method 100 determines the match-corrected signal power measurement and a method 300 calibrates the VNA test port to determine the measurement.

Abstract: The method and a device to measure the repeatable and non-repeatable runouts of a rotating component of a spindle motor with the aid of at least one probe measuring changes in the distance between the probe and the rotating component depending on the angle of rotation. The probe records a first test signal in a first test cycle from which a signal defining the RRO is determined and stored. In a second test cycle, a command signal proportional to the amplitude and phase of the RRO signal is generated and fed to an electromechanical actuator supporting the probe. Depending on the command signal derived from the first test signal, the actuator changes the distance between the probe and the outer perimeter of the rotating component, thus compensating the runout defined by the RRO signal, while the probe records a second test signal defining the NRRO.

Abstract: A multiple sensitivity stud sensing device for determining a location of objects behind a wall lining has a housing with a surface for moving over the wall lining. Within the housing are a capacitive sensor with first and second capacitances provided adjacent the surface and control circuitry. The control circuitry includes a detecting circuit connected to the sensor for providing a detection signal related to an imbalance between the first and second capacitances, a comparator having a reference signal for providing a comparator signal related to a difference between the detection signal and the reference signal, and a controller for receiving the comparator signal and providing a display signal. A display is provided on the housing for indicating a location of an object behind the wall lining. An input device is provided on the housing so that a user of the device can select a value for the reference signal.

Abstract: A method for non-contact measurement of a displacement between a surface and a capacitive sensor comprised of at least two superimposed conductive plates electrically insulated one from the other and a sensor circuit coupled to the plates including: positioning the capacitive sensor proximate to the surface such that the displacement is a distance of a gap between the surface and one of the plates; applying a high frequency signal to the plates; applying the high frequency signal and a sensor plate to control a voltage gain of an amplifier in the circuit, where the capacitance on the sensor is indicative of the displacement between the sensor and surface; differentiating an output of the amplifier and the high frequency signal, and determining a value of the displacement based on the difference between the output of the amplifier and the high frequency signal.

Abstract: A capacitance sensor system and method includes a capacitive sensor as an array of sensor electrodes near the surface of the integrated circuit and charge pump circuits for measuring the capacitance at each sensor electrode. Shield electrodes and unused sense electrodes are used for background capacitance cancellation at each array location. The shield electrodes are switched between the circuit supply potentials in a manner synchronous to the capacitance sensing at the sense electrodes. The improved background capacitance cancellation allows all circuitry to be located outside the sensor array. The capacitance data is used to determine the positions of fingerprint artifacts and other fingerprint features.

Abstract: A measuring apparatus having a probe that faces a surface of a target and is configured to supply AC current to the surface, measuring a voltage drop through a space between the probe and the surface, and obtaining a distance between the probe and the surface in accordance with the measured voltage drop. The apparatus includes a ground member facing, and apart from, the surface and configured to ground the surface by capacitive coupling, and a stage configured to hold either of the target and the probe and to move to define a measurement area on the surface. The ground member is configured so that the ground member faces all areas of the surface with respect to each of a plurality of measurement areas on the surface defined by a position of the stage.

Abstract: A probe card is used to test an electronic device. The probe card includes a base plate and a cantilever-type probe arranged on the base plate. The cantilever-type probe has an end that contacts the contacted body and moves when contacting the contacted body. A stopper arranged on the base plate restricts the movement of the cantilever-type probe.

Abstract: A probe is disclosed, comprising a beam, which has a front end, an intermediate portion and a base end. The leading end is a portion for contacting a test subject through a contactor, the base end being a portion for fixing the probe. The probe includes a substantially trapezoidal contactor, which is fixed to the leading end of the beam.

Abstract: A compliant electrical interconnect having a first component and a second component interlockingly engaged with the first component. Each component has two cantilever arms lockingly engaged and continuously biased against each other. Contact springs are captivated by the cantilever arms providing a contact force for the first and second components.

Abstract: A test system for a semiconductor device couples the device to the back side of a circuit board, thereby allowing the device to be tested under actual operating conditions while providing adequate clearance around the device to accommodate automatic handling equipment, and also reducing signal delay and distortion. A system in accordance with the present invention includes a circuit board having circuitry adapted to provide an actual operating environment for the semiconductor device, as for example, a low cost mother board for testing memory devices. The device is coupled to the back side of the circuit board through test terminals formed on the back side of the board. An interface board can be used to correct the pin arrangements, which are reversed because they protrude from the back side of the board, and to compensate for the environmental differences caused by use of sockets and additional equipment on the interface board.

Abstract: Test sockets, test systems, and methods for testing microfeature devices with a substrate and a plurality of conductive interconnect elements projecting from the substrate. In one embodiment, a test socket includes a support surface and a plurality of apertures in the support surface corresponding to at least some of the interconnect elements of the microfeature device. The individual apertures extend through the test socket and are sized to receive a portion of one of the interconnect elements so that the substrate is spaced apart from the support surface when the microfeature device is received in the test socket. In one aspect of this embodiment, the individual apertures have a cross-sectional dimension less than a cross-sectional dimension of the interconnect elements so that the apertures receive only a portion of the corresponding interconnect element.

Abstract: A method and apparatus allows adapting a standard flying prober system to manually or automatically determine the likelihood of error free probability of test point targets on Printed Circuit Assemblies (PCA's) which may have significant planarity irregularities. The method and apparatus provides a corrective function allowing error free probing of test target points on PCA's having planarity irregularities which otherwise make them impractical to test. The method and apparatus involves utilizing the camera system typically provided with a flying prober system and an auxiliary sighting system each having different optical axis angles, the use of which allows determination of height values.

Abstract: The invention includes a design for device design-for-test and a burn-in-board that reduce the number of external components per device on the board. Inputs to the I/Os of a device from input means are inverted between pairs of output pins. A single resister is coupled between an output that is true (e.g., not inverted) and an output that is inverted. Thus, instead of using one or more resistors per I/O from the DUT, a single resister can be coupled between inverted and non-inverted outputs.

Abstract: A hybrid non-abrasive electrical test contact element of a test socket is taught. Unlike cantilever contact elements of the prior art, the contact element of the present invention is able to contact a lead of an integrated circuit device under test without abrading the plating on the lead. This is achieved by the contact element possessing multiple loops to allow the tip of the contact element to move not only downwards, but also sideways in a rocking and non-sliding motion. The tip of the contact is also shaped to contact the lead at only a radius corner of each lead so as not to affect the solderability of the lead. In addition, tests have shown that the contact element of the present invention has at least twice the working life span compared to another contact element of the prior art.

Abstract: A protection circuit comprises: at least one shielded line arranged to cover an area to be protected over a semiconductor device, the at least one shielded line having only one route from a start point to an end point; a signal generator for applying a signal to the start point of the shielded line; a counter which starts measurement of time in response to application of the signal to the start point of the shielded line by the signal generator and which ends measurement of the time in response to arrival of the signal at the end point of the shielded line; and a comparator for comparing the time measured by the counter with a reference value to output a fraud detection signal according to a result of the comparison.

Abstract: A semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronics (PE) stage for producing an AC test signal to test a semiconductor device. A driver circuit is capable of providing a version of the DC test signal and a version of the AC test signal to the semiconductor device.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: An electrical circuit including a test circuit and a method of testing electrical circuits is disclosed. In one embodiment, the circuit includes a electrical short-circuit protective circuit according to the invention for protecting an input contact against short-circuit having an input which is intended for connection to a signal generator, and an output which is intended for connection to a input contact. The input contact can be decoupled from the region lying upstream of the input of the electrical short-circuit protective circuit by the electrical short-circuit protective circuit.

Abstract: An apparatus for measuring the static parameters of integrated circuit is disclosed. When the apparatus is operated, the output mode is determined automatically according to the load of the integrated circuit. When the apparatus is operated in voltage output mode, the apparatus automatically limits the current. When the apparatus is operated at current output mode, the apparatus automatically limits the voltage. Therefore, the operation voltage and the operation current are stabilized. When the tested integrated circuit fails, the apparatus of the present invention can protect itself according to the stable operation voltage and operation current, and doesn't damage the tested integrated circuit.

Abstract: A power supply potential and a ground potential are supplied to a test-use power supply pad and a test-use ground pad, respectively. The power supply potential supplied to the test-use power supply pad is transferred to power supply lines and then to each circuit block via a test-use power supply line and a potential transfer circuit including a diode device. A voltage drop is caused by each of the diode devices. To cope with the voltage drop, however, respective sizes of the diode devices and resistance components of the potential transfer circuits are configured so that a uniform voltage drop is generated at each of the power supply lines.

Abstract: In one embodiment, a diagnostic circuit is used to test the on-resistance of a transistor.

Abstract: The present invention provides a method of electron beam testing of liquid crystal displays comprising non-uniform electrodes having a conductive portion and a dielectric portion. In accordance with methods of the present invention, the diameter of the electron beam is increased so that the beam is less focused, i.e., enlarged or “blurred,” over a non-uniform electrode area. The diameter of the beam is increased so that the beam generates secondary electrons from the conductive portion of the non-uniform electrode area. The configured test beam may be circular, elliptical, or other suitable shapes.

Abstract: An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.

Abstract: There is provided a data acceleration device comprising a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a second node which is electrically coupled with the first node, in response to an output signal from the pull-up driver, a first pull-down circuit for pull-down driving the second node, in response to an output signal from the pull-down driver, a delay circuit for delaying a signal from the second node by a preset time to output a delayed signal, a first switch for switching an operation of the first pull-up circuit in response to an output signal from the delay circuit, and a second switch for switching an operation of the first pull-down circuit in response to the output signal from the delay circuit. Also, there is presented a data transmission apparatus including the data acceleration device.

Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log.

Abstract: A cross-bar matrix includes a plurality of matrix cells arranged in rows and columns wherein each row of cells is associated with a signal input and each column of cells is associated with a common signal output. An enable input controls whether at least a portion of the cells couple a signal on the associated common signal input to a signal output associated with a cell or couple an LCD signal to a signal output and exclude control of the at least portion of said plurality of cells by the control input.

Abstract: A programmable logic block provides programmable initialization values for carry chains traversing the logic block, without consuming user logic resources. An exemplary programmable logic block includes two or more carry multiplexers coupled together to form a carry chain for the programmable logic block. A carry initialization circuit has an output terminal coupled to a data input terminal of a first carry multiplexer in the carry chain. The carry initialization circuit is controlled by configuration memory cells of the programmable logic block to select one of a carry in signal, a power high signal, a ground signal, and (optionally) a signal from an interconnect structure of the logic block. Thus, an initialization value (e.g., power high or ground) can be provided to the carry chain without consuming other programmable resources within the logic block.

Abstract: In one embodiment of the invention, a programmable logic device (PLD) includes a plurality of programmable logic blocks arrayed in rows and columns, wherein each programmable logic block is coupled to a corresponding vertical routing resource and a corresponding horizontal routing resource, and wherein each vertical and horizontal routing resource includes a plurality of wires organized into wire groups and each programmable logic block has a set of inputs organized into input groups. The PLD also includes a plurality of connection boxes, each connection box corresponding to a programmable logic block and operable to couple a given wire group in one of the corresponding vertical and horizontal routing resources to a given input group independently of whether a given wire group in the remaining one of the corresponding vertical and horizontal routing resources is coupled through the connection box to the given input group.

Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors in each set of the second plurality of conductors substantially connect, through a second set of switches, to a third plurality of sets of conductors. Each conductor of a set of the third plurality sets of conductors either connects, physically, to one pin in each of a plurality of functional blocks or, through a third set of switches, to a subsequent fourth plurality sets of conductors. The SN is scalable for large sized sets of conductors and can be used hierarchically in, for example, an integrated circuit or in an electronic system.

Abstract: A high-side driver circuit for driving a load, including a low-side driver IC having a drive output and a feedback input, a first transistor coupled to the drive output, and a second transistor coupled between a power source and the load. The second transistor is configured to enter an “OFF” state when the first transistor is driven into an “OFF” state by the drive output, and to enter an “ON” state when the first transistor is driven into an “ON” state by the drive output.

Abstract: A magnetic transistor circuit has a first and a second magnetic transistor. These two magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The buffer and inverter logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: A driver circuit that outputs a data signal uses feedback of the data signal to the driver circuit to modulate a drive strength of the driver circuit. The driver circuit has a pull-up driver stage and a pull-down driver stage. The pull-up driver stage uses a pull-up control circuit to modulate a drive strength of the pull-up driver stage dependent on a voltage of the data signal. The pull-down driver stage uses a pull-down control circuit to modulate a drive strength of the pull-down driver stage dependent on the voltage of the data signal.

Abstract: A semiconductor integrated circuit device (1) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF64) of a shift register (SR1) and input of a flip-flop (FF65) of a shift register (SR2); and a transistor switch (SWB) for electrically connecting and disconnecting an input driver (Din2) and input of the flip-flop (FF65). Here, when the shift registers (SR1 and SR2) are connected, the transistor switch (SWA) is turned ON and the transistor switch (SWB) is turned OFF by a selection signal.

Abstract: A method and apparatus for shifting a dynamic circuit, driven by a one-shot clock, to a pre-charge mode, during a power-off mode, is provided. Under certain conditions, a floating node may be present in a dynamic circuit. One approach to prevent floating nodes involves the generation of a new one-shot clock signal that is supplied to the last dynamic circuit in the series of dynamic circuits before the output flop (“the final dynamic circuit”). The new one-shot clock signal is driven to a logical low value when the power-off signal has a logical high value. Another approach to prevent floating nodes involves modifying the final dynamic circuit to include a structure that, when the power-off signal has a logical high value, drives the dynamic node to either a logical high value or a logical low value to prevent the dynamic node from becoming a floating node.

Abstract: A selector circuit precisely outputs a signal selected from a plurality of signals. A latch circuit unit generates an internal selection control signal for controlling a selection operation of a selector circuit unit. When the levels of first and second data input signals do not match each other, the selector circuit unit maintains its selected state and does not perform a selecting operation based on the selection signal until the levels of the signals match each other in accordance with the internal selection control signal.

Abstract: Disclosed are keeper circuits for electronic circuits that selectively maintain the voltage level of an intermediate circuit node at a desired level. In one exemplary embodiment, a keeper transistor either provides current or drains current from the intermediate node to maintain the desired voltage level in response to a signal to do so. The keeper circuit works against a leakage current that either drains current from the node or supplies current to the node. A current-setting transistor is coupled in series with the keeper transistor to set the maximum current through the keeper circuit to a value that is related to this leakage current, preferably tracking the leakage current. With this construction, the current-setting transistor is able to track variations in the leakage current caused by variations in the manufacturing process, and thereby provide dynamic leakage compensation.

Abstract: A logic family consisting of four basic logical circuits performing AND, OR, NAND and NOR functions is disclosed. The AND and OR logic circuits function without a power supply and complementary input signals. The NAND and NOR logic circuits function without complementary input signals. The AND and OR logic circuits are constructed using two MOS (Metal Oxide Semiconductor) transistors, namely, one P-channel MOS transistor and one N-channel MOS transistor. The NAND and NOR logic circuits are constructed using four MOS transistors, namely, two P-channel MOS transistors and two N-channel MOS transistors. The logic circuits may have higher speed, occupy less area and consume less power because power supply is not needed, complementary input signals are not used and fewer transistors are used. The logic circuits may have increased performance relative to CMOS (Complementary MOS) logic circuits, CPL (Complementary Pass Logic) circuits and DPL (Dual Pass Logic) circuits.

Abstract: A frequency programmable feed forward oscillator and triangular wave generator is disclosed having a first input for receiving an input voltage and a second input for receiving an input current. Circuitry within the device responsive to the input voltage scales the amplitude of a triangle wave form according to the provided input voltage and provides the scaled output voltage at a first output. In conjunction, the circuitry also generates a scaled PWM frequency responsive to the provided input current and provides this at a second output.

Abstract: A combined output driver for TMDS signals and LVDS signals. First and second output drivers output first and second differential signals to a first external input unit and a second external input unit, respectively, through a pair of signal lines according to first and second input signals. In the second output driver, a driver buffer is coupled to a first voltage and a first node respectively to generate two control signals according to the second input signals. An output unit generates the second differential signal according to the two control signals. A power supply provides a second voltage higher than the first voltage to power the driver buffer and the output unit when the first output driver outputs the first differential signal to the first external input unit.

Abstract: A combined output driver for TMDS signals and LVDS signals. A first output driver includes a first differential unit generating a first differential according to first input signals in a first mode and a first clamping device coupled between the first node and the first differential unit to clamp potentials at two power terminals below a second power voltage. The second output driver includes a second differential unit generating a second differential signal according to second input signals in a second mode and a second clamping device to clamp potentials at two output terminals of the second differential unit below the second power voltage.

Abstract: A low-voltage differential signal driver with a pre-emphasis circuit having a current control circuit and a pre-emphasis circuit is provided. Wherein, the pre-emphasis circuit includes the current sourcing circuit and the current sinking circuit, both of which have similar circuit structure, coupled to the current control circuit, respectively. The current sourcing circuit and the current sinking circuit are controlled by two sets of driving signals, so that the pre-emphasis circuit provides an extra driving current to the current control circuit at an instant when the current control circuit switches the current direction. In addition, each set of driving signals contains two synchronous but phase-inversed driving signals. The time it takes for the current steering circuit to switch terminated resistor current between upward and downward directions is decreased.

Abstract: A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for outputting the local clock signal as a phase-adjusted local clock having a selected phase based on a phase selection value specified by the counter. The synchronizer is configured for digitally sampling the received reference clock relative to the phase-adjusted local clock, and outputting a digital phase bit identifying whether the phase-adjusted local clock has a later phase relative to the received reference clock. The counter selectively increments or decrements a counted value based on the digital phase bit, and outputs to the phase selection circuit a prescribed number of most significant bits from the counted value as the phase selection value.

Abstract: One embodiment of the present invention provides a system that matches speeds of asynchronous operation between a local chip and a neighboring chip. The system derives an internal frequency signal from an internal oscillator on the local chip, and receives an external frequency signal from a neighboring chip. The system then compares the internal frequency signal with the external frequency signal to generate a control signal, which is applied to the local chip to adjust the operating speed of the local chip, and applied to the internal oscillator to adjust the frequency of the internal oscillator.

Abstract: A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module further configured to multiply the control signal by a square root of the state information to provide a tuning signal.

Abstract: Systems and methods for reducing the effects of the operation of logic on a phase-locked loop (PLL) circuit are disclosed. These systems and methods may allow a PLL circuit to compensate for the anticipated effects of an instruction before, substantially simultaneously with, or after the execution of the instruction. More particularly, logic associated with the issue of instructions in a system may provide a signal to a PLL in the system based on an instruction. The PLL may then be adjusted to compensate for the anticipated effects of the instruction based on this control signal.

Abstract: A charge pump generates a first sub up current and a second sub up current that vary complementarily with a change in a voltage at an output terminal. The charge pump also generates a first sub down current and a second sub down current that vary complementarily with the change in the voltage at the output terminal. With such complementary relationships, the total up/down currents remain substantially constant and balanced with the change in the voltage at the output terminal.

Abstract: A pulse width modulation (PWM) controlling module, includes: a PWM controller, a load detector, and an adjusting module. The PWM controller generates a PWM signal that is utilized for controlling a supply voltage applied to an electronic system. The load detector, coupled to the PWM controller, detects a load of the electronic system according to the PWM signal and generates a decision value accordingly. The adjusting module, coupled to the PWM controller and the load detector, controls the PWM controller to adjust the PWM signal according to the decision value.

Abstract: Disclosed are methods and systems for implementing various circuitry within a high speed, high frequency signal environment such as an integrated circuit. In one embodiment, an improved clock tree mechanism utilizes multiple low power drivers to distribute a clock signal to various load cells. In another embodiment, a single circuitry in current mode logic is used to implement a combined multiplexer, buffer and level shifter. In other embodiments, improved static and partially static flip-flop circuitry is disclosed which uses fewer devices and less power than conventional circuitry while achieving the same functionality.

Abstract: An elastic pipelined latch. The latch includes a control input for configuring the latch into a repeater state or a latch state, a drive component responsive to the control input and for driving an input signal through as an output signal, and a pulse width/inhibit component coupled to the drive component. The latch further includes a reset threshold component coupled to the drive component for inhibiting oscillation of the drive component, and a latch component for passing the present state of the input signal to the output signal when configured as the repeater state and for maintaining the previous state of the output signal during transitions of a clock signal when configured as the latch state.

Abstract: The invention discloses a delay locked loop (DLL) architecture with a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit.