Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.

Abstract: A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate.

Abstract: In a thin-film field-effect transistor having a MIS structure, the insulator layer is formed of cyanoethylated dihydroxypropyl pullulan. The TFT is prepared by applying a cyanoethylated dihydroxypropyl pullulan solution onto a gate electrode in the form of a metal layer, drying the applied solution to form an insulator layer, and thereafter, forming a semiconductor layer thereon.

Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

Abstract: A capacitor including a first active layer capacitively coupled to a second active layer, the second active layer being capacitively coupled to a third layer, the third layer being capacitively coupled to a fourth layer, wherein an anode of the capacitor is connected to one of the first and second active layers, and a cathode of the capacitor is connected to the other one of the first and second active layers, and wherein the third layer is left floating. The fourth layer may be connected to a supply voltage, such as but not limited to, ground.

Abstract: According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench capacitor includes a node dielectric and a node conductor formed within the trench. Buried plate (BP) diffusions extend laterally outward from a lower portion of each trench of the array, the BP diffusions merging to form an at least substantially continuous BP diffusion region across the array. An isolation region extends over a portion of the BP diffusion region. A doped well region is formed within the substrate extending from a major surface of the substrate to a depth below a top level of the substantially continuous BP diffusion region. An electrical interconnection is also provided to the well region.

Abstract: A trench (12) of a semiconductor memory cell (1) has an insulation collar (44), which is open toward the substrate (42) on just one side (50). On the other side (52), the insulation collar (44, 47, 55) rises all the way up to the insulation cover (62). There is therefore no need for a shallow trench isolation. The contact (70) which is buried on one side is formed by oblique implantation, for example with N2 or argon, the implantation taking place from a fixedly predetermined direction with an angle of inclination of between 15 and 40°. The implantation substances effect different etching or oxidation properties, etc., of the implanted materials. In combination with this method, it becomes possible to realize a new layout for the semiconductor memory cell (1), in which the structures for forming the active areas form long lines (31) extending over a plurality of adjacent semiconductor memory cells.

Abstract: A dynamic random access memory (DRAM) cell structure (and method for making a DRAM cell structure) that is more suitable than current DRAM structures for implementation in ever decreasing semiconductor fabrication geometries. The DRAM cell structure comprises a deep trench (DT) capacitor formed in a substrate. A recess is formed in the substrate proximate the deep trench capacitor. A gate is formed that extends into the recess but does not completely occupy the recess. A source is formed in the substrate in a region beneath the recess. A drain is formed in the substrate in a region laterally and vertically offset from the source. A channel between the source and drain is created beneath the gate along a side wall of the recess. Thus, the depth of the recess determines the length of the channel region. With this DRAM cell structure, it is easier to avoid the high doping concentration issue and the short channel effect.

Abstract: A method for forming the lower electrode of a capacitor used for fabricating a 1-Gbit or above DRAM, using a material having a high dielectric constant, is used in a method for manufacturing a storage capacitor of a VLSI semiconductor device. The lower electrode, which is to be in contact with a high dielectric film, is formed to have a triple-structured storage node pattern. The lowest layer of the lower electrode is formed with TiN which serves as a barrier against the diffusion of impurities from a lower substrate. The middle layer of the lower electrode is formed with RuO2 which is easy to pattern. The uppermost layer of the lower electrode is formed with Pt which has excellent leakage current properties.

Abstract: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.

Abstract: Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.

Abstract: An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (?m)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

Abstract: This invention discloses a one-time programmable (OTP) memory cell. The OTP memory cell includes a dielectric layer disposed between two conductive polysilicon segments wherein the dielectric layer is ready to change from a non-conductive state to a conductive state through an induced voltage breakdown. In a preferred embodiment, one of the conductive polysilicon segments further includes an etch undercut configuration for conveniently inducing the voltage breakdown in the dielectric layer. In a preferred embodiment, the dielectric layer is further formed as sidewalls covering the edges and corners of a first polysilicon segments to conveniently induce a voltage breakdown in the dielectric layer by the edge and corner electrical field effects.

Abstract: Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

Abstract: A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer.

Abstract: An electrically erasable and programmable read only memory (EEPROM) device may include: a gate oxide layer on a semiconductor substrate, the gate oxide layer including a first segment of a first thickness, a second segment of a second thickness, and a tunneling third segment of a third thickness, the second thickness being thicker than the first thickness and the third thickness being thinner than the first thickness; a floating junction region formed under a portion of the gate oxide layer in the semiconductor substrate; and a floating gate, an insulating layer pattern, and a control gate which are sequentially formed, respectively, on the gate oxide layer.

Abstract: A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric is formed above the substrate. A polysilicon control gate is formed on top of the gate dielectric. The gate dielectric may have an oxide—high-k dielectric—oxide composite structure or an oxide oxide—high-k dielectric composite structure.

Abstract: A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric is formed above the substrate. A polysilicon control gate is formed on top of the gate dielectric. The gate dielectric may have an oxide-high-k dielectric-oxide composite structure or an oxide-oxide-high-k dielectric composite structure.

Abstract: A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric is formed above the substrate. A polysilicon control gate is formed on top of the gate dielectric. The gate dielectric may have an oxide—high-k dielectric—oxide composite structure or an oxide—oxide—high-k dielectric composite structure.

Abstract: A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n? channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

Abstract: An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate that includes a trench extending into a semiconductor material. The trench can include a ledge and a bottom, wherein the bottom lies at a depth deeper than the ledge. The electronic device can include discontinuous storage elements, wherein a trench portion of the discontinuous storage elements lies within the trench. Gate electrodes may lie adjacent to walls of the trench. In a particular embodiment, a portion of a channel region within a memory cell may not be covered by a gate electrode. In another embodiment, a doped region may underlie the ledge and allow for memory cells to be formed at different elevations within the trench. In other embodiment, a process can be used to form the electronic device.

Abstract: A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.

Abstract: A semiconductor IC device includes a base substrate comprising P?-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.

Abstract: A TFT device, a method of manufacturing the same, a TFT substrate and a display device, making it possible to decrease the photolithography steps, to improve the productivity and to decrease the cost of production. There are formed on the same substrate a first n-ch TFT having an LDD region which is entirely covered with a gate electrode, a second n-ch TFT having an LDD region partially covered with a gate electrode, and a p-ch TFT. Here, electrically conducting thin films and a gate electrode are formed on the electrically conducting thin film and on the insulating film, phosphorus ions are implanted into source/drain regions of the n-ch TFTs using the electrically conducting thin films and gate electrode as masks, and a gate electrode is formed by etching the electrically conducting thin film by using the electrically conducting thin film as a mask.

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions.

Abstract: A semiconductor memory device includes transistors, each including a first-conductivity-type semiconductor layer formed on a semiconductor substrate via a first insulating film, a second-conductivity-type source/drain regions formed in the semiconductor layer, a first-conductivity-type body region formed between the source region and the drain region in the semiconductor layer, the body region being electrically floating, and a gate electrode formed on a surface of a central portion of the body region via a second insulating film. In a section along a word line, which connects the gate electrodes together, a length of a boundary between the central portion of the body region and the second insulating film is smaller than a length of a boundary between the body region and the first insulating film. A second-conductivity-type counter impurity is doped in a surface portion of the central portion of the body region on which the second insulating film is formed.

Abstract: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60?) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion.

Abstract: The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance of a stack-gate voltage tolerant I/O.

Abstract: The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region. The semiconductor comprises a P-type Si substrate 109, a plurality of P-type wells 103a, 103b connected to each other via the bottom surface side of the P-type Si substrate 109, and an N-type well 101 provided so as to surround side portions of the plurality of P-type wells 103a, 103b. The semiconductor device also has NMOS transistors 107a, 107b provided on the P-type wells 103a, 103b, and PMOS transistors 105a, 105b, 105c provided on the N-type well 101. The semiconductor device still also has an N-type well 133 provided just under the N-type well 101 and connected therewith.

Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “-” functions as a gate electrode of an original MOS transistor.

Abstract: A metal oxide semiconductor transistor comprising a first doping type substrate, an isolation layer, a plurality of gates, a masking layer, a gate oxide layer, a plurality of second doping type source/drain regions and spacers. The first doping type substrate has a plurality of trenches patterning out a plurality of first doping type strips. The isolation layer is disposed within the trenches. The gates is disposed over the first doping type strips and oriented in a direction perpendicular to the first doping type strips. The masking layer is disposed over the first doping type substrate. The gate oxide layer is disposed between the sidewall of the first doping type strips and the gate. The second doping type source/drain regions are disposed in the first doping type strip on each side of the gate. The spacers are disposed on the sidewalls of the gates and the first doping type strips.

Abstract: An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region; forming a high-k dielectric overlying the surface channel; and, forming a gate electrode overlying the high-k dielectric. Typically, the surface channel is a metal oxide, and may be one of the following materials: indium oxide (In2O3), ZnO, RuO, ITO, or LaX-1SrXCoO3. In some aspects, the method further comprises: depositing a placeholder material overlying the surface channel; and, etching the placeholder material to form a gate region overlying the surface channel. In one aspect, the high-k dielectric is deposited prior to the deposition of the placeholder material. Alternately, the high-k dielectric is deposited following the etching of the placeholder material.

Abstract: Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized. Nanodetector devices are described.

Abstract: A micro-electromechanical device is formed on a substrate. The device has sliding, abrading or impacting surfaces. At least one of these surfaces is covered with an anti-stiction material. The anti-stiction material is provided from a slicon compound precursor (e.g. silane, silanol) or multiple silicon compound precursors. Preferably the precursor(s) is fluorinated—more preferably perfluorinated, and is deposited with a solvent as a low molecular weight oligomer or in monomeric form. Examples include silanes (fluorinated or not) with aromatic or polycyclic ring sturctures, and/or silanes (fluorinated or not) having alkenyl, alkynyl, epoxy or acrylate groups. Mixtures either or both of these groups with alkyl chain silanes (preferably fluorinated) are also contemplated.

Abstract: A light emitting device comprises a light emitting element, a metal package having a recess part for housing the light emitting element and a base part which has one or more through holes, and one or more lead electrode pins which penetrate the through holes and are separated from the through holes by an insulating member respectively. The bottom faces of the lead electrode pins project out from the bottom face of the base part and are positioned on a same plane including an outer bottom face of the recess part. With this configuration, the light emitting device has a good heat radiating characteristic and high mechanical strength.

Abstract: A solid-state image pickup device 10 has an arrangement in which a second conductivity type semiconductor region 14 is formed on the surface of a first conductivity type electric charge accumulation region 13 of a light-receiving sensor portion, a shallow trench isolation layer 20 formed of an insulating layer is buried into a trench formed on a semiconductor substrate 11, the shallow trench isolation layer 20 is composed of an upper wide portion 21 and a lower narrow portion 22 and a second conductivity type semiconductor region 23 is formed around the lower narrow portion 22 of the shallow trench isolation layer 20. The solid-state image pickup device can suppress the occurrence of a dark current and a white spot, it can produce an image with high image quality and it can sufficiently maintain a sufficiently large amount of electric charges that can be handled by the light-receiving sensor portion.

Abstract: The present invention is directed towards radiation detectors and methods of detecting incident radiation. In particular the present invention is directed towards photodiodes with controlled current leakage detector structures and a method of manufacturing photodiodes with controlled current leakage detector structures. The photodiodes of the present invention are advantageous in that they have special structures to substantially reduce detection of stray light. Additionally, the present invention gives special emphasis to the design, fabrication, and use of photodiodes with controlled leakage current.

Abstract: An antifuse element (102) having end corners (120, 122) of a gate electrode (104) positioned directly above an active area (106) or bottom electrode. The minimum programming voltage between the gate electrode (104) and the active area (106) creates a current path through an insulating layer (110) positioned therebetween. The high electric field created at the end corners (120, 122) of the gate electrode (104) results in a breakdown and rupture of the insulating layer (110) at points directly beneath the end corners (120, 122). This localization of the insulating layer (110) at the corners (120,122) provides for lower post program resistance and variation, and faster programming at a lower programming power. The antifuse elements (102) when integrated into an array (300, 320, 400, 550) provide for increased packing density. The array is fabricated to include multiple active areas (304) for individual antifuse element (302) programming or a common active area (324,405,426,506) for multi-element programming.

Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.

Abstract: A composite structure is disclosed that includes a support wafer and a layered structure on the support wafer. The layered structure includes at least one layer of a monocrystalline material and at least one layer of a dielectric material. In addition, the layered structure materials and the thickness of each layer are chosen such that the thermal impedance between ambient temperature and 600° K of the composite structure is a value that is no greater than about 1.3 times the thermal impedance of a monocrystalline bulk SiC wafer having the same dimensions as the composite structure. The composite structure provides sufficient heat dissipation properties for manufacturing optical, electronic, or optoelectronic components.

Abstract: A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.

Abstract: A semiconductor chip includes an active inner circuit; a die seal ring surrounding the active inner circuit; a first circuit structure fabricated at a first corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the first circuit structure has a first solder pad; and a second circuit structure fabricated at a second corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the second circuit structure has a second solder pad.

Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10] , or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].

Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].

Abstract: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].

Abstract: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

Abstract: A lead frame package structure with high density of lead pins arrangement is formed. The lead frame structure includes a die, a plurality of first lead pins and a plurality of second lead pins, wherein the first lead pins and the second lead pins are positioned on at least one side of the die, and are electrically connected to the die. The first lead pins and the second lead pins are selected from a group consisting of J-leads, L-leads and I-leads, and terminals of the first lead pins and terminals of the second lead pins are staggered so that the high density of lead pins arrangement is formed without risking a short circuit.

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.

Abstract: An integrated circuit chip packaging assembly having a first and second package side. An integrated circuit chip has a substrate side and an active circuit side. The chip includes integrated circuit devices formed on the active circuit side. The active circuit side of the chip is on the first package side. The die pad has at least one runner member extending therefrom, which may be bent toward the first package side. The active circuit side of the chip is attached to the die pad. The die pad is on the first package side relative to the chip. The package mold compound is formed over the die pad, at least part of the chip, and at least part of the runner member(s). At least part of the substrate side of the chip and/or at least part of the runner member(s) may not be covered by the package mold compound.

Abstract: LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and conductors leading to solderable package connections. The growth substrate is then removed. Because the delicate LED layers were bonded to the package substrate while attached to the growth substrate, no intermediate support substrate for the LED layers is needed. The relatively thick LED epitaxial layer that was adjacent the removed growth substrate is then thinned and its top surface processed to incorporate light extraction features.