Abstract: An NMR signal acquisition device that can increase the magnetic field homogeneity in a high frequency magnetic field by one of the following. (a) Current paths each having a different inductance are provided to adjust the diversion ratio of the current, (b) A current path branch point is provided in an intermediate part of the winding of a solenoidal coil so that there are more current paths in the intermediate part of the winding than in the current paths connected to the feeding points at both ends, (c) The radiuses of current paths are adjusted, (d) Winding pitches in the axis direction are adjusted, (e) Current path widths are adjusted, and (f) The solenoidal coil has both positive direction current paths and negative direction current paths.

Abstract: An improved magnetic resonance (MR) imaging system (10) is provided. A plurality of receiver coils (12) may be configured to supply respective coil output signals based on a plurality of magnetic resonance response signals sensed by the receiver coils. Each receiver coil defines an enclosure constituting a Faraday cage. At least one circuit device (22) is disposed in the enclosure (24) to condition the coil output signal. This enclosure enables the circuit device (22) to be shielded from electromagnetic interference.

Abstract: The invention relates to a measuring device (1) for detecting signals, particularly signals in an ignition system of an internal combustion engine, with a signal line (2) and a measuring electrode (3) connected to the signal line (2) for coupling a signal to be detected into the signal line (2). In order to simplify the detection of signals in inaccessible areas, the measuring device (1) has a flexible tip (4).

Abstract: A method of obtaining a material property of a pavement material from a microwave field generally includes generating a microwave frequency electromagnetic field of a first mode about the pavement material. The frequency response of the pavement material in the electromagnetic field can be measured, such as by a network analyzer. The measurement of the frequency response permits correlating the frequency response to a material property of the pavement material sample, such as the density. A method of correcting for the roughness of a pavement material divides the pavement into a shallow layer and a deep layer. Two planar microwave circuits measure the permittivity of the shallow and deep layer. The permittivities are correlated to correct for roughness. An apparatus for obtaining the density of a pavement sample includes a microwave circuit and a network analyzer. The network analyzer measures the frequency response to determine the density of the pavement material.

Abstract: An apparatus senses an object proximate to a laminar fluid flow by using the fluid as part of the sensing system. For more distant objects, an electrical system detects the capacitance between the proximate object and the flowing fluid via an impedance measurement. For objects touching the flow, an optical system detects the loss of total internal reflection. Together, the two systems allow the proximity to be determined over a wide range. A fluid flow is produced through a nozzle. An electrode is placed in the fluid. A complex impedance is measured between the electrode and an object due to capacitive coupling between the object and the fluid flow. The complex impedance is inversely proportional to a distance between the object and the fluid flow and proportional to an area of proximity of the object.

Abstract: The invention relates to a flexible, resilient capacitive sensor suitable for large-scale manufacturing. The sensor comprises a dielectric, an electrically conductive detector and trace layer on the first side of the dielectric layer comprising a detector and trace, an electrically conductive reference layer on a second side of the dielectric layer, and a capacitance meter electrically connected to the trace and to the conductive reference layer to detect changes in capacitance upon interaction with detector. The sensor is shielded to reduce the effects of outside interference.

Abstract: The invention relates to a flexible, resilient capacitive sensor suitable for large-scale manufacturing. The sensor comprises a dielectric, an electrically conductive detector and trace layer on the first side of the dielectric layer comprising a detector and trace, an electrically conductive reference layer on a second side of the dielectric layer, and a capacitance meter electrically connected to the trace and to the conductive reference layer to detect changes in capacitance upon interaction with detector. The sensor is shielded to reduce the effects of outside interference.

Abstract: A circuit configuration recognizes the occupancy of a seat and triggers a seatbelt warning in a motor vehicle. Resistance elements are disposed in a separated and flat manner on a motor vehicle seat, in particular on a sensor seating mat, which alters the resistance values when a force is exerted thereon, for example, perpendicular to the surface of the vehicle seat, or by bending. The weight-sensitive resistance elements contain first resistance elements and additional resistance elements, and the resistance values thereof can be measured in respectively different measuring circuits without the measuring results for the first resistance elements influencing the measuring results for the additional resistance elements.

Abstract: A probe includes a substrate and a tetragonal structure disposed on the substrate that has four end points. Three of the end points are disposed adjacent to the substrate. A fourth of the end points extends outwardly and substantially normal to the substrate. In a method of making a probe tip, a plurality of tetrapods are grown and at least one of the tetrapods is placed on a substrate at a selected location. The tetrapod is affixed to the substrate at the selected location.

Abstract: A secure memory card with encryption capabilities comprises various life cycle states that allow for testing of the hardware and software of the card in certain of the states. The testing mechanisms are disabled in certain other of the states thus closing potential back doors to secure data and cryptographic keys. Controlled availability and generation of the keys required for encryption and decryption of data is such that even if back doors are accessed that previously encrypted data is impossible to decrypt and thus worthless even if a back door is found and maliciously pried open.

Abstract: A system that determines power consumption on an IC chip. The system includes a test structure located within the IC chip variations which includes one or more gates which receives power from a power source, wherein each gate has a different drive strength, and wherein the output of each gate is coupled to a load through a corresponding switch. The system also includes a current-measuring mechanism coupled to the power supply which measures the current consumed by the gates. When a specific switch is activated, the output of a corresponding gate is coupled to the load, thereby causing the corresponding gate to drive the load. The current consumed by the corresponding gate is measured by the current measuring mechanism. The measured current can be used to determine the power consumption of the corresponding gate driving the load.

Abstract: A method of inspecting a leakage current of a dielectric layer on a substrate including a cell array region having a plurality of cell blocks including a patterned structure, the dielectric layer formed on the patterned structure, and a peripheral circuit region includes depositing a corona ion charge on a cell block selected from the plurality of cell blocks and measuring a variance of a surface voltage caused by a leakage current through the dielectric layer on the selected cell block. The variance of the surface voltage is compared with reference data to determine a leakage current characteristic of the dielectric layer.

Abstract: Systems and methods for reducing power consumed by digital circuits using an off-chip controller to selectively provide power to individual portions of the circuitry. One embodiment comprises an IC and an off-chip power controller. The circuitry constructed on the IC chip includes two or more independently powered regions. The power controller is configured to selectively power on (or off) each of the regions. The regions that are powered off have no leakage current, and therefore eliminate power use. In one embodiment, the regions comprise SPE's in a multiprocessor. The power controller may be configured to provide power to the SPE's at different voltages. The power controller may identify the SPE's to be powered on and off in various ways, such as reading a memory that stores the information, and may provide/inhibit power to each SPE in various ways, such as switching relays that couple the SPE's to a power source.

Abstract: Impedance matching and trimming apparatuses and methods using programmable resistance devices. According to one exemplary embodiment, the impedance matching circuit includes a programmable resistance element, a comparator, a resistor divider having a common node coupled to a first input of the comparator, and an impedance element control circuit coupled between an output of the comparator and the programmable resistance element. The programmable resistance element includes one or more programmable resistance devices (PRDs). Programmed resistances of the programmable resistance element combine with the resistance of an external reference resistor to provide an impedance matched termination. A change in the resistance of the termination impedance causes a change in the output of the comparator.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.

Abstract: In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.

Abstract: An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.

Abstract: Circuitry for preventing damage to bipolar transistors in integrated circuit amplifier circuitry during slew-limited operation includes first and second transistors, each having first, second, and third electrodes, a first one of the first and second electrodes of the first transistor being coupled to receive a first signal, and a first one of the first and second electrodes of the second transistor being coupled to receive a second signal.

Abstract: To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second inverters 300 and 200 of a CMOS type in which a gate of each MOS transistor is individually driven are provided and the first inverter 300 is used as a level converting unit. A voltage level of a first control signal CS1 output from an output node no1 of the first inverter 300 is forcibly dropped down by a voltage dropping circuit CONT1 so as to accelerate the operation of the second inverter 200. As a result, the inversion of the level of an output signal of the first inverter 300 is accelerated. Further, the balance between current capabilities of the individual transistors is optimized and, in particular, the sizes of the transistors constituting the second inverter 200 are reduced so as to suppress an increase in a circuit area.

Abstract: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.

Abstract: A level shifter circuit and method thereof are provided. The example level shifter circuit may include a pull-up drive unit driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage and a pull-down drive unit driving the output node to the third voltage in response to the input signal, the pull-up and pull-down drive units adjusting current levels of at least one of a pull-up current flowing through the pull-up drive unit and a pull-down current flowing through the pull-down drive unit based on whether the pull-up drive unit and the pull-down drive unit are operating concurrently.

Abstract: A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.

Abstract: A bootstrap inverter circuit, consisting of transistors of the same type, comprises a first transistor, a second transistor, a voltage clamp circuit and an output end. The voltage clamp circuit, having a first node and a second node, controls the voltage of a gate of the second transistor. A gate and a first end of the first transistor are connected to a power source. A gate of the second transistor is connected to the second node of the voltage clamp circuit. A first end of the second transistor is connected to the power source. A second end of the second transistor is connected to the output end. The first node of the voltage clamp circuit is connected to the power source. The second node of the voltage clamp circuit is connected to a second end of the first transistor.

Abstract: In a flip-flop circuit where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the conductivity of a first load transistor connected to the first output terminal is controlled by the signal from the second output terminal, and the conductivity of a second load transistor connected to the second output terminal is controlled by the signal from the first output terminal.

Abstract: A device and system for controlling current from plural parallel power sources having inrush current hot-swapping capabilities to a load are disclosed. The current controlling device includes a load line for delivering currents from the outputs of the power sources; a current sensor for measuring the load current; and a common sense element for adjusting the load current levels.

Abstract: An X-Y stage driver having a locking device and a data storage system having the X-Y stage driver. The X-Y stage driver includes an X-Y stage; a supporting unit that supports the X-Y stage and has elastic beams that support corners of the X-Y stage; a driving unit that drives the X-Y stage in a first direction and a second direction which is perpendicular to the first direction; a stiffener that prevents the X-Y stage from rotating; and a locking device that fixes the stiffener by an electrostatic force.

Abstract: Disclosed are an input buffer, and more particularly, a technique that is capable of improving the operation speed of the input buffer by improving response speed with respect to an input signal. The input buffer includes a buffer unit that operates when an activation control signal is activated, compares the voltage of an input signal to a preset reference voltage, and outputs the result of the comparison to an output node, a driving unit that performs driving control on an output of the buffer unit, and outputs an output signal, and a pull-down control unit that outputs a pull-down control signal that has a high pulse for a predetermined time when transition of a potential of the input signal occurs.

Abstract: A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.

Abstract: An exemplary power control circuit includes a voltage divider, a switching circuit, and a detecting circuit. The voltage divider receives power from a first power supply which is connected to a microprocessor. The switching circuit is connected between a second power supply and the microprocessor. The detecting circuit is connected between the switching circuit and the voltage divider, the switching circuit is turned on when a divided voltage of the voltage divider is greater than a turn-on voltage of the detecting circuit, and power from the second power supply is supplied to the microprocessor through the switching circuit.

Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Abstract: Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sampling clock. A multiplexer in communication with the first and second sampling circuits selects one of the samples as a retimed version of the frequency-divided clock. The particular sample selected is preferably the sample less likely to produce an erroneous retimed version of the frequency-divided clock.

Abstract: A differential charge pump includes a differential charge pump unit, current adjusting device, and common mode voltage control circuit. The differential charge pump unit is used for generating a output voltage signal according to a pump-up signal and a pump-down signal. The current adjusting device is coupled to the differential charge pump unit for providing an adjusting current signal to the differential charge pump unit as the pump-up signal and pump-down signal are both enabled or disabled. The control circuit is coupled to the differential charge pump unit for outputting a feedback signal to the differential charge pump unit according to the output voltage signal.

Abstract: A Delay Locked Loop (DLL) having a function of periodically executing a locking operation during a power down mode and a locking operation method of the same, which includes a global clock generator, a clock delay unit, and a power down control unit. The power down control unit, in response to some of a plurality of global clock signals, a phase detection signal, and a power down signal, outputs an input clock signal to each of the global clock generator and the clock delay unit. During the power down mode, the clock delay unit is enabled to periodically carry out the locking operation whenever it receives the input clock signal. Therefore, a consumed power of the DLL can be decreased during the power down mode, and a phase difference between an external clock signal and an internal clock signal during the power down mode can be decreased by the periodical locking operation of the clock delay unit, so that the DLL can operate at a fast speed after the power down mode.

Abstract: A circuit and method for controlling a slew rate of an output buffer. A pre-driver is provided that drives an input of an output pad driver of the output buffer. An output slew rate of the pre-driver is electronically selected among at least two electronically selectable slew rates. An output amplitude of the pre-driver is controlled such that the output amplitude is not greater than an amplitude that is generally minimally sufficient to cause the output pad driver to produce an output signal having a desired dynamic range.

Abstract: In a semiconductor integrated circuit including first and second circuits whose inputs/outputs are in cross-connection, an output node of the first circuit is driven on the basis of a first input signal, and an output node of the second circuit is driven on the basis of a second input signal. At this time, there are provided a first driving transistor capable of driving the output node of the first circuit on the basis of the second input signal, and a second driving transistor capable of driving the output node of the second circuit on the basis of the first input signal. The output nodes are driven using the first and second driving transistors, respectively.

Abstract: A phase adjustor circuit and a phase adjusting method are capable of preventing a phase shift amount from fluctuating even in the case where a frequency of a transmission carrier wave of a sensor signal fluctuates. A chopping wave converter circuit converts a pulse string signal into a chopping wave. A chopping wave amplitude control circuit compares the amplitude value of the chopping wave with an amplitude reference value, and outputs an adjustment signal corresponding to a difference between those values to the chopping wave converter circuit. The chopping wave converter circuit changes a slope of the chopping wave according to the adjustment signal to adjust the amplitude value of the chopping wave. As a result, a feedback group is structured, and the amplitude value of the chopping wave is maintained to a constant value according to the amplitude reference value.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and generates a pulse signal with a high level that may be converted into a second level higher than the first level. The flip-flop may further include a latch that latches input data with a high level equal to a third level lower than the second level and outputs output data with a high level that may be converted into the second level in response to the pulse signal. The third level may be equal to the first level. A supply voltage of the second level may be used as a supply voltage to the latch.

Abstract: A disclosed semiconductor integrated circuit device includes a selection circuit that is supplied with a first clock signal and a second clock signal, a selection signal, and a switching signal, and configured to select one of the first clock signal and the second clock signal according to the selection signal and to change the selected one of the first clock signal and the second clock signal to the other one of the first clock signal and the second clock signal according to the switching signal. The disclosed semiconductor integrated circuit device also includes an output fixing circuit configured to generate a pulse that is maintained at a high level or a low level during a certain period, to perform an OR operation on the output signal from the selection circuit and the generated pulse, and to output a result of the OR operation as the output clock signal.

Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.

Abstract: A rectifier circuit configured with a conventional configuration using an operational amplifier and a diode by a thin film transistor over an insulating substrate cannot exhibit the performance of a rectifier circuit due to the low stability of operational amplifier and the low high-frequency characteristic. Therefore, the rectifier circuit requires to be configured by using an IC outside of the insulating substrate in order to rectify a high-frequency signal. According to the invention, an amplifier circuit and a waveform shaping circuit are configured with a thin film transistor and a non-rectified signal is switched by a signal thereof, so that a rectifier circuit with the excellent high-frequency characteristic can be realized.

Abstract: A transconductor including circuitry for automatically selecting a non-linear class A operation or a linear class AB operation based on an input signal to be processed to generate an output signal, and for automatically adjusting current from a power supply to a level needed for operation of the transconductor.

Abstract: A constant current circuit includes first and second depression type MOS transistors having drains connected to a high electric potential side; and first, second, and third enhanced type MOS transistors having sources connected to a low electric potential side.

Abstract: A signal output circuit is disclosed that supplies a signal from a first circuit that is driven based on a first reference voltage to a second circuit that is driven based on a second reference voltage. The signal output circuit includes a first control circuit that draws a current to the first reference voltage according to an output signal from the first circuit and supplies a signal to the second circuit according to the drawn current, and a second control circuit that draws a current from the second circuit to the second reference voltage.

Abstract: A peak power suppressor for facilitating realization of a desired peak factor without increasing the device scale and without degrading the use efficiency of the storage area. A clipping section (102) suppresses the peak power of the transmission signal according to the clipping coefficient (a). A filter section (103) limits the frequency band of the transmission signal the peak power of which has been suppressed. A coefficient correction signal generating section (111) detects the instantaneous input power (Pin) of the transmission signal inputted into the clipping section (102) and the instantaneous output power (Pout) outputted from the filter section (103). The coefficient correction signal generating section (111) computes the variation (?a) of the clipping coefficient (a) from the instantaneous input and output powers (Pin, Pout). A coefficient setting section (108) changes the clipping coefficient (a) according to the computed coefficient variation (?a).

Abstract: A current sense amplifier for a voltage converter wherein the voltage converter has at least one channel providing an output current through an output inductor, the current sense amplifier monitoring the current in the at least one channel through the output inductor, the current sense amplifier comprising a plurality of variable gain amplifiers, there being at least one more variable gain amplifier than channels in the voltage converter, whereby at least one variable gain amplifier is in a calibration mode for a preset period of time during which the variable gain amplifier is compensated for an offset error and the gain of the variable gain amplifier is calibrated to compensate for temperature of the output inductor, while during said preset period of time any remaining variable gain amplifiers are connected to monitor the channel current in each output inductor.

Abstract: A digital amplifier apparatus includes a gain-adjusting section operable to adjust a gain of a digital audio signal; a dither-superposing section operable to superpose a predetermined dither on the digital audio signal; a pulse-width-modulated signal generating section operable to generate a pulse-width-modulated signal corresponding to the digital audio signal; an amplifying section operable to cause a switching element to perform a switching operation in accordance with the pulse-width-modulated signal; a pulse-width changing section operable to change a ratio between a “high” state and a “low” state of the pulse-width modulated signal; and a control section operable to perform a muting process by causing the gain-adjusting section to set the gain of the digital audio signal to a zero level, the dither-superposing section to stop superposing the dither, and the pulse-width changing section to change, step by step, the ratio between the “high” state and the “low” state of the pulse-width modulated signal tow

Abstract: A digital amplifier apparatus includes a gain-adjusting section operable to adjust a gain of a digital audio signal; a dither-superposing section operable to superpose a predetermined dither on the digital audio signal; a pulse-width-modulated signal generating section operable to generate a pulse-width-modulated signal corresponding to the digital audio signal; an amplifying section operable to cause a switching element to perform a switching operation in accordance with the pulse-width-modulated signal; a pulse-width changing section operable to change a ratio between a “high” state and a “low” state of the pulse-width modulated signal; a synchronizing section operable to synchronize the pulse-width modulated signal with a reset signal that resets the digital audio signal; and a control section operable to perform a resetting operation by setting the gain of the digital audio signal to a zero level upon receiving the reset signal, stopping the superposing of the dither to thereby generate the pulse-width mo

Abstract: A self-oscillating switching amplifier having an error amplifier output combined with the output of an output signal differentiator according predetermined weighing factors to force a small oscillation around the averaged output signal at a high frequency. The feedback voltage is sensed at the output of the switching amplifier. Additional feedback can be derived from a switching node of the power switch. The switching of the power switch can be dynamically changed from binary switching when the amplitude of the audio signal is low, to ternary switching when the amplitude of the input signal is high to minimize distortion of the output signal. The amplifier can be supplied with a pulsing voltage. In certain embodiments the output signal differentiator is simply a capacitor or a LC resonance circuit coupled directly to an appropriate speaker terminal for the highest possible self-oscillating frequency of the switching amplifier.

Abstract: An operational amplifier for canceling an offset and continuously generating an output signal. The operational amplifier includes a first operational amplification unit and a second operational amplification unit each having at least one electrical characteristic that is substantially the same as one another. One of the operational amplification units performs a canceling operation (holding operation and compensation operation) of the offset voltage while the other operational amplification unit performs a non-canceling operation and generates the output voltage by amplifying an input voltage. Both operational amplification units alternately perform the canceling operation and the non-canceling operation.