Abstract: A light-emitting element is disclosed that can drive at a low driving voltage and that has a longer lifetime than the conventional light-emitting element, and a method is disclosed for manufacturing the light-emitting element. The disclosed light-emitting element includes a plurality of layers between a pair of electrodes; and at least one layer among the plurality of layers contains one compound selected from the group consisting of oxide semiconductor and a metal oxide, and a compound having high hole transportation properties. Such the light-emitting element can suppress the crystallization of a layer containing one compound selected from the group consisting of oxide semiconductor and a metal oxide, and a compound having high hole transportation properties. As a result, a lifetime of the light-emitting element can be extended.

Abstract: An object is to provide a method of manufacturing a nitride semiconductor light emitting device having high light emission output and allowing decrease in forward voltage (Vf). The invention is directed to a method of manufacturing a nitride semiconductor light emitting device including at least an n-type nitride semiconductor, a p-type nitride semiconductor and an active layer formed between the n-type nitride semiconductor and the p-type nitride semiconductor, wherein the n-type nitride semiconductor includes at least an n-type contact layer and an n-side GaN layer, the n-side GaN layer consists of a single or a plurality of undoped and/or n-type layers, and the method includes the step of forming the n-side GaN layer by organic metal vapor deposition with the growth temperature set within the range of 500 to 1000° C., such that the n-side GaN layer is formed between the n-type contact layer and the active layer.

Abstract: A light emitting die package is provided which includes a metal substrate having a first surface and a first conductive lead on the first surface. The first conductive lead is insulated from the substrate by an insulating film. The first conductive lead forms a mounting pad for mounting a light emitting device. The package includes a metal lead electrically connected to the first conductive lead and extending away from the first surface.

Abstract: A light emitting apparatus 10 includes an aluminum nitride co-fired substrate 11 and a light emitting device 12 arranged on a front surface of the co-fired substrate, in which the front surface of the aluminum nitride substrate 11 bearing the light emitting device 12 is mirror-polished so as to have a surface roughness of 0.3 ?m Ra or less, and the light emitting apparatus 10 further includes a vapor-deposited metal film 14 and via holes 15. The vapor-deposited metal film 14 is arranged on the front surface of the aluminum nitride substrate 11 around the light emitting device 12 and has a reflectivity of 90% or more with respect to light emitted from the light emitting device 12. The via holes 15 penetrates the aluminum nitride substrate 11 from the front surface bearing the light emitting device 12 to the rear surface to thereby allow conduction to the light emitting device 12 from the rear surface.

Abstract: An object of the present invention is to provide a positive electrode having high transparency, low contact resistance and excellent current diffusibility and not requiring electron beam irradiation, high-temperature annealing or heat treatment, for alloying, in an oxygen atmosphere. The inventive transparent positive electrode for gallium nitride-based compound semiconductor light-emitting devices comprises a contact metal layer in contact with a p-type semiconductor layer, a current diffusing layer on the contact metal layer, the current diffusing layer having an electrical conductivity larger than that of the contact metal layer, and a bonding pad layer on the current diffusing layer.

Abstract: An electronic device according to the invention includes a housing, a recess containing an optoelectronic component, and a film including a polyimide, which is over the recess covering the optoelectronic component.

Abstract: A light emitting device package and a method of manufacturing the same are disclosed. The light emitting device package includes a package structure, two diffusion layers formed on the package structure such that the two diffusion layers are electrically separated from each other, and first and second electrodes insulated from the package structure by an insulation film. The first and second electrodes are electrically connected with the two diffusion layers, respectively.

Abstract: A structure having an optical element thereon has a portion of the structure extending beyond a region having the optical element in at least one direction. The structure may include an active optical element, with the different dimensions of the substrates forming the structure allowing access for the electrical interconnections for the active optical elements. Different dicing techniques may be used to realize the uneven structures.

Abstract: An LED assembly including a wiring substrate with an opening at its center; a heat sink housed inside the opening; an LED chip mounted on the heat sink; a connecting section for electrically coupling the LED chip and wiring substrate; and a transparent resin covering the LED chip and connecting section. Heat generated from the LED chip is efficiently dissipated, and high productivity is also achievable.

Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

Abstract: A III-V group compound semiconductor light-emitting diode, containing a substrate 1 having plural crystal planes, and a grown layer formed on the substrate by epitaxial growth, the grown layer at least including a barrier layer 2 and 3 and an active layer 8, wherein at least the active layer of the grown layer has plural crystal planes each having a different bandgap energy in the in-plane direction, and an Ohmic electrode 4 for current injection is formed on a crystal plane (3) having a higher bandgap energy among the plural crystal planes.

Abstract: The present disclosure relates to isolated Zener diodes (100) that are substantially free of substrate current injection when forward biased. In particular, the Zener diodes (100) include an “isolation tub” structure that includes surrounding walls (150, 195) and a base (130) formed of semiconductor regions. In addition, the diodes (100) include silicide block (260) extending between anode (210) and cathode (220) regions. The reduction or elimination of substrate current injection overcomes a significant shortcoming of conventional Zener diodes that generally all suffer from substrate current injection when they are forward biased. Due to this substrate current injection, the current from each of a conventional diode's two terminals is not the same.

Abstract: The acquisition of seismic data is increasingly more important in today's modern world. There are many forms of seismic data. Seismic data records are acquired and analyzed for applications ranging from subsurface engineering, environmental and/or water exploration, to deep oil-gas applications. It is very important to understand that for the acquisition of this seismic data “signal-stacking” is a crucial part of the data acquisition process. This allows the data to be “stacked”, the seismic signals are mathematically summed, in order to eliminate unwanted noise from the data such as wind energy, airplanes . . . etc. A precise, reliable and durable triggering mechanism capable of enduring heavy repeatable shock's had to be developed in order to facilitate this requirement. There have been many attempts to create the ideal triggering device or apparatus, but until now, not one was inexpensive and not one proved to be durable, reliable & precise.

Abstract: A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.

Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.

Abstract: An electrostatic protection device for a semiconductor circuit for protecting an internal circuit from static electricity applied to the pad includes a first conductivity type semiconductor substrate; second conductivity type diffusion regions formed on the surface of the semiconductor substrate at regular intervals into a dot type; isolation structures formed on the surface of the semiconductor substrate to respectively surround the second conductivity type diffusion regions; and first conductivity type diffusion regions formed on the surface of the semiconductor substrate outside of the second conductivity type diffusion regions and the isolation regions.

Abstract: An ultra high speed APD capable of realizing reduction in an operating voltage and quantum efficiency enhancement at the same time is provided. Under operating conditions APD, a doping concentration distribution of each light absorbing layer is determined so that a p-type light absorbing layer (16) maintains a p-type neutrality except a part thereof, and a low concentration light absorbing layer (15) is depleted. Moreover, a ratio between a layer thickness WAN of the p-type light absorbing layer (16) and a layer thickness WAD of the low concentration light absorbing layer (15) is determined so that WAD>0.3 ?m and a delay time of an element response accompanying a transit of carriers generated in the light absorbing layer by light absorption takes on a local minimum under a condition that a layer thickness WA (=WAN+WAD) of the light absorbing layer is constant.

Abstract: The present invention relates to a high linear enhancement-mode heterostructure field-effect transistor. More, the present invention uses an InGaAs channel structure with a linear change, and integrates an adjusting effect of working region corresponding to the threshold voltage of the element. It not only directly provides a complementary structure for the conventional depletion-mode element to select, but also increases the range of the gate voltage swing. More, some important characteristics, such as current driving capacity, transconductance gain, linear amplification, and high speed operation can be largely improved. More particularly, E-mode working element has a low static power. Further, the present invention also has a high stop frequency characteristic of the high speed element from the composite semiconductor, and it can be applied to the microwave push-pull amplification circuit.

Abstract: A nitride semiconductor device comprises: a laminated body; a first and second main electrode provided in a second and third region, respectively, adjacent to either end of the first region on the major surface of the laminated body; and a third main electrode. The laminated body includes a first semiconductor layer of a nitride semiconductor and a second semiconductor layer of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer, the second semiconductor layer being provided on the first semiconductor layer. The third main electrode is provided on the major surface of the laminated body and opposite to the control electrode across the second main electrode.

Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.

Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

Abstract: An electronic device according to the present invention includes a functional element acting as a predetermined circuit packaged using a resin member. The electronic device comprises a wiring substrate having a wiring member for electric connection with an external circuit; the functional element mounted on one main surface of the wiring substrate so as to be electrically connected to the wiring member; and the resin member provided on the one main surface of the wiring substrate having the functional element, so as to package the functional element. The resin member includes a filler formed of a magnetic material.

Abstract: A method for manufacturing an optical film comprising a transparent substrate and at least one functional layer on or above the transparent substrate, wherein said at least one functional layer to be laminated on the transparent substrate is formed by a layer-forming method comprising the following steps (1) and (2): (1) step of applying a coated layer on the transparent substrate, and (2) step of curing the coated layer by irradiating ionizing radiation in an oxygen environment in which the oxygen concentration is lower than an atmospheric oxygen concentration.

Abstract: In an element for a MOS type solid-state imaging device, a leakage current caused by a stress generated in a vicinity of an element isolation region having an STI structure is reduced. The element for the MOS type solid-state imaging device comprises: a signal accumulation region 102, of a second conductivity type, provided in an interior of a semiconductor substrate or well 101 of a first conductivity type, for accumulating a signal charge generated by performing photoelectric convention; agate electrode 104 provided on the semiconductor substrate or well 101; a drain region 105, of a second conductivity type, provided on a surface portion, of the semiconductor substrate or well 101, on which the gate electrode is formed; and an element isolation region 201 provided on the surface portion, of the semiconductor substrate or well 101, on which the gate electrode is formed. The element isolation region 201 has the STI structure, and a cavity 202 is formed in an interior of the element isolation region 201.

Abstract: A layer sequence with lateral boundaries, especially a gate electrode stack, comprises a cover layer between a metal layer and a top layer that is provided as a hardmask. The cover layer, which is preferably polysilicon, enables the application of a cleaning agent to remove a resist layer, clean the hardmask and remove deposits of the material of the top layer produced in the structuring of the hardmask, before the layer sequence is structured using the hardmask. The cover layer protects the metal layer, which could otherwise be damaged by the cleaning agent.

Abstract: SiC-IGBTs, which have an inversion-type channel with high channel resistance and have high on-voltage due to an influence from the surface state of the interface between a gate insulating film and a base layer, are required to decrease the on-voltage. An embedded collector region is partially formed in a base layer which is formed on an emitter layer of a SiC semiconductor. A channel layer is formed on the base layer and the embedded collector region to constitute an accumulation-type channel. Consequently, at on time, holes are accumulated in the upper layer portion of the channel layer so that a low-resistant channel is formed. Current by the holes flows to the emitter layer through a channel from the collector region and becomes a base current for an npn transistor composed of the embedded collector region, the base region and the emitter region.

Abstract: A semiconductor device capable of suppressing reduction of the electric characteristics and fluctuation of the threshold voltage resulting from ion implantation is obtained. This semiconductor device comprises a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween and a gate electrode formed on the channel region through a gate insulating film, and the gate electrode includes a first metal-containing layer, a second metal-containing layer formed on the first metal-containing layer and an intermediate layer formed between the first metal-containing layer and the second metal-containing layer.

Abstract: An image sensor with a plurality of photodiodes that each have a first region constructed from a first type of material and a second region constructed from a second type of material. Located adjacent to the first region and between second regions of adjacent photodiodes is a barrier region. The photodiodes are reversed biased to create depletion regions within the first regions. The barrier region limits the lateral growth of the depletions regions and inhibits depletion merger between adjacent photodiodes.

Abstract: According to one embodiment, an electronic device includes a housing including an opening, a button disposed in the opening, a switch contained in the housing and operated by using the button, a wall extending in the housing from that part of the housing which surrounds the opening, a sealing member interposed between the button and the switch, covering the opening, and including an edge part extending along a peripheral surface of the wall, and a holder which presses the edge part of the sealing member against the peripheral surface of the wall.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; a first interlayer dielectric layer formed on the field effect transistor; a first contact plug connected to the field effect transistor through the first interlayer dielectric layer; a ferroelectric capacitor disposed on the first interlayer dielectric layer and connected to the first contact plug; a second interlayer dielectric layer that is formed on the ferroelectric capacitor and includes a silicon nitride film at least in a portion thereof in a film thickness direction; a second contact plug connected to the ferroelectric capacitor through the second interlayer dielectric layer; and a wiring layer that is formed on the second interlayer dielectric layer and connected to the ferroelectric capacitor through the second contact plug.

Abstract: Method of fabricating an integrated electronic circuit with programmable resistance cells, which comprises providing a substrate; forming an inert electrode; forming a solid electrolyte on the inert electrode; forming an interlayer on the solid electrolyte, the interlayer comprising an active electrode material and nitrogen; and forming an active electrode on the interlayer, the active electrode comprising the active electrode material.

Abstract: A single-electron transistor (1) has an elongate conductive channel (2) and a side gate (3) formed in a 5 nm-thick layer (4) of Ga0.98Mn0.02As. The single-electron transistor (1) is operable, in a first mode, as a transistor and, in a second mode, as non-volatile memory.

Abstract: This disclosure concerns a semiconductor memory device comprising a supporting substrate including semiconductor materials; an insulation film provided above the supporting substrate; a first diffusion layer provided on the insulation film; a second diffusion layer provided on the insulation film; a body region provided between the first diffusion layer and the second diffusion layer, the body region being in an electrically floating state and accumulating or releasing electric charges for storing data; a semiconductor layer connected to the second diffusion layer to release electric charges from the second diffusion layer; a gate insulation film provided on the body region; and a gate electrode provided on the gate insulation film.

Abstract: An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide layer formed on the lower electrode, a second oxide layer formed on the first oxide layer and an upper electrode formed on the second oxide layer wherein at least one of the first and second oxide layers may be formed of a resistance-varying material. The first oxide layer may be formed of an oxide having a variable oxidation state.

Abstract: A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate comprising an active area where a first conductive channel is formed, a gate electrode formed on the active area formed on the semiconductor substrate and a gate dielectric layer interposed between the active area and the gate electrode. The semiconductor device further includes a charge generating layer formed along the interface between the active area and the gate dielectric layer on the semiconductor substrate so that fixed charges are generated around the interface.

Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.

Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.

Abstract: A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably formed by a Damascene process, in which a first polysilicon is removed after forming two floating gates, and a second polysilicon is placed between these two floating gates. An anisotropic etching is later done on the second polysilicon to form two control gates.

Abstract: A single poly embedded memory structure comprises an access transistor and a storage device formed on a silicon substrate. The access transistor comprises source and drain diffusion regions implanted in the silicon substrate and a polysilicon control gate formed over the silicon substrate between the source and drain diffusion regions. The storage structure comprises a source and drain diffusion regions implanted in the silicon substrate and a polysilicon floating gate formed over the silicon substrate between the source and drain diffusion region; however, the source diffusion region comprises a double diffusion structure.

Abstract: Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.

Abstract: Disclosed is a method of manufacturing a semiconductor device, including the steps of: forming on a second insulating film a first resist pattern having a first window; employing the first resist pattern as an etching mask to form first openings exposed from contact regions CR; forming, on a second conductive film, a second resist pattern having first resist portions; employing the second resist pattern as an etching mask to form first and second conductors, a floating gate and a control gate; forming a third resist pattern in regions I, II and III; and employing the third resist pattern as an etching mask to remove the portions of the second conductors under second windows.

Abstract: An object of the present invention is to provide a nonvolatile semiconductor storage device with a superior charge holding characteristic in which highly-efficient writing is possible at low voltage, and to provide a manufacturing method thereof. The nonvolatile semiconductor storage device includes a semiconductor film having a pair of impurity regions formed apart from each other and a channel formation region provided between the impurity regions; and a first insulating film, a charge accumulating layer, a second insulating film, and a conductive film functioning as a gate electrode layer which are provided over the channel formation region. In the nonvolatile semiconductor storage device, a second barrier formed by the first insulating film against a charge of the charge accumulating layer is higher in energy than a first barrier formed by the first insulating film against a charge of the semiconductor film.

Abstract: A MONOS type nonvolatile memory cell is structured such that a laminated insulating film which is formed by sequentially laminating a tunnel insulating layer, a charge storage insulating layer, and a charge block insulating layer is provided on a convex curved surface portion of a semiconductor substrate, and a control gate electrode is further formed thereon. A thickness of the tunnel insulating layer is set to be 4 to 10 nm, and data writing/data erasing operations are carried out by making an F-N tunneling current flow in the tunnel insulating layer.

Abstract: A gate electrode of a semiconductor device according to the present invention includes a substrate, a bulb type recess with an upper recess and a bottom recess, the bottom recess formed in a round shape and having a larger width than the upper recess, a gate insulation layer formed over the substrate and in the bulb type recess, and a polysilicon electrode in the bulb type recess, wherein the polysilicon electrode is formed using two different methods including a growth method

Abstract: A semiconductor device includes an isolation region, a semiconductor element region defined by the isolation region, and having a channel forming portion and a recessed portion, the recessed portion being formed between the isolation region and the channel forming portion, and an epitaxial semiconductor portion formed in the recessed portion, wherein the semiconductor element region has a wall portion between the isolation region and the epitaxial semiconductor portion.

Abstract: The invention provides a high voltage MOS transistor having a high gate breakdown voltage and a high source/drain breakdown voltage and having a low on-resistance. A gate electrode is formed on an epitaxial silicon layer with a LOCOS film being interposed therebetween. A P-type first drift layer is formed on the left side of the LOCOS film, and a P+-type source layer is disposed on the surface of the epitaxial silicon layer on the right side of the LOCOS film, being opposed to the first drift layer over the gate electrode. A P-type second drift layer is formed by being diffused in the epitaxial silicon layer deeper than the first drift layer, extending from under the first drift layer to under the left side of the LOCOS film. A recess is formed in a bottom portion of the second drift layer under the left end of the LOCOS film.

Abstract: A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the substrate. The thin film power transistor further includes a dielectric layer, at least a portion of which is disposed between (i) the gate and (ii) the first and second doped regions. In addition, the thin film power transistor includes a plurality of contacts contacting the plurality of first doped regions, where the plurality of first doped regions forms a source and a drain of the thin film power transistor. The first doped regions could represent n-type regions (such as N? regions), and the second doped region could represent a p-type region (such as a P? region). The first doped regions could also represent p-type regions, and the second doped region could represent an n-type region.

Abstract: A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

Abstract: The invention provides an SOI substrate 10 comprising on one major surface of a silicon single crystal 13 a silicon thin-film layer 11 via a buried silicon oxide film 12, characterized in that a substrate warp preventive layer 14 is provided on another major surface of the silicon single crystal 13. The invention also provides a charged particle beam exposure mask blank and a charged particle beam exposure mask having high mask pattern alignment precision, each using that SOI substrate. The invention has the advantages of being easy to fabricate, and capable of preventing a warp in the substrate.