Patents Issued in August 30, 2007
-
Publication number: 20070200175Abstract: A functional device which is composed of a nanometer-sized functional structure, which can reduce connection resistance in connecting the functional structure to an external electrode, and which includes a wiring section capable of minimizing constraints given to structural designs of various functional structures, and a method of manufacturing it are provided. A functional device in which a functional structure having contained sections in positions spaced from each other is retained by a carbon nanotube. A gap is formed in the carbon nanotube, and the carbon nanotube is segmented into a first carbon nanotube and a second carbon nanotube by the gap. One of the contained sections is contained in the first carbon nanotube at an opening of the first carbon nanotube facing the gap, and the other of the contained sections is contained in the second carbon nanotube at an opening of the second carbon nanotube facing the gap.Type: ApplicationFiled: October 3, 2006Publication date: August 30, 2007Applicants: SONY CORPORATIOIN, SONY DEUTSCHLAND GMBHInventors: Eriko Matsui, William Ford, Jurina Wessels, Akio Yasuda, Ryuichiro Maruyama, Tsuyonobu Hatazawa
-
Publication number: 20070200176Abstract: Formation of a silicide layer on the source/drain regions of a field effect transistor with a channel under tensile strain is disclosed. The strain is originated by the silicon/carbon source/drain regions which are grown by CVD deposition. In order to form the silicide layer, a silicon cap layer is deposited in situ by CVD. The silicon cap layer is then employed to form a silicide layer made of a silicon/cobalt compound. This method allows the formation of a silicide cobalt layer in silicon/carbon source/drain regions, which was until the present time not possible.Type: ApplicationFiled: October 18, 2006Publication date: August 30, 2007Inventors: Thorsten Kammler, Patrick Press, Rolf Stephan, Sven Beyer
-
Publication number: 20070200177Abstract: A semiconductor laser device comprising: an active layer, a semiconductor layer formed on the active layer and having a wurtzite structure, wherein a principal surface of the active layer is substantially perpendicular to a (0001) surface of the semiconductor layer, a current path portion in the semiconductor layer extends along a crystal orientation substantially parallel to the (0001) surface of the semiconductor layer, and an inner angle of the principal surface to a first side surface is different from an inner angle of the principal surface to a second side surface, the first side surface is a side surface of the current path portion and the second side surface is opposite to the first side surface.Type: ApplicationFiled: February 27, 2007Publication date: August 30, 2007Applicant: Sanyo Electric Co., Ltd.Inventors: Masayuki Hata, Takashi Kano
-
Publication number: 20070200178Abstract: A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region.Type: ApplicationFiled: April 10, 2007Publication date: August 30, 2007Inventors: Eun-jung Yun, Sung-min Kim, Sung-young Lee
-
Publication number: 20070200179Abstract: A strain enhanced CMOS device using amorphous carbon films and fabrication methods of forming the same. The amorphous carbon (a-C) film, such as fluorinated amorphous carbon (a-C:F), is formed of a tensile film or a compressive film to act a stress capping film on the pMOS device region or the nMOS device region. The amorphous carbon film also acts a contact etching stop layer during a contact hole etching process.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventor: Cheng-Ku Chen
-
Publication number: 20070200180Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.Type: ApplicationFiled: December 28, 2006Publication date: August 30, 2007Inventors: Rustom Irani, Boaz Eitan, Ilan Bloom, Assaf Shappir
-
Publication number: 20070200181Abstract: A pixel cell having a photo-conversion device at a surface of a substrate and at least one contact area from which charge or a signal is output or received. A first insulating layer is located over the photo-conversion device and the at least one contact area. The pixel cell further includes at least one conductor in contact with the at least one contact area. The conductor includes a polysilicon material extending through the first insulating layer and in contact with the at least one contact area. Further, a conductive material, which includes at least one of a silicide and a refractory metal, can be over and in contact with the polysilicon material.Type: ApplicationFiled: May 1, 2007Publication date: August 30, 2007Inventor: Howard Rhodes
-
Publication number: 20070200182Abstract: A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+strap between N+active areas of two memory cells in a column and provide an N+strap between P+active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventor: Jhon-Jhy Liaw
-
Publication number: 20070200183Abstract: A power semiconductor component includes a drift zone in a semiconductor body, a component junction and a compensation zone. The component junction is disposed between the drift zone and a further component zone, which is configured such that when a blocking voltage is applied to the component junction, a space charge zone forms extending generally in a first direction in the drift zone. The compensation zone is disposed adjacent to the drift zone in a second direction and includes at least one high-dielectric material having a temperature-dependent dielectric constant. The temperature dependence of the compensation zone varies in the second direction.Type: ApplicationFiled: January 31, 2007Publication date: August 30, 2007Applicant: Infineon Technologies Austria AGInventors: Michael Rueb, Franz Hirler
-
Publication number: 20070200184Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET) (100) incorporates a stepped drift region including a shallow trench insulator (STI) (112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Ronghua Zhu, Amitava Bose, Vishnu Khemka, Todd Roggenbauer
-
Publication number: 20070200185Abstract: A high dielectric constant gate insulating film is formed on an active region of a substrate, and a gate electrode is formed on the high dielectric constant gate insulating film. A high dielectric constant insulating sidewall is formed on a side face of the gate electrode.Type: ApplicationFiled: October 6, 2006Publication date: August 30, 2007Inventors: Junji Hirase, Naoki Kotani, Shinji Takeoka, Gen Okazaki, Akio Sebe, Kazuhiko Aida
-
Publication number: 20070200186Abstract: A semiconductor device capable of reducing a threshold voltage is obtained. The semiconductor device includes a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween, and a gate electrode formed on the channel region through a gate insulating film and including a metal-containing layer arranged in the vicinity of an interface between the gate insulating film and the gate electrode, wherein the metal-containing layer is so formed in the form of dots as to partially cover the surface of the gate insulating film, and the average distance between dots forming the metal-containing layer is set to not more than a diameter of the dot of the metal-containing layer.Type: ApplicationFiled: February 28, 2007Publication date: August 30, 2007Inventor: Hideaki Fujiwara
-
Publication number: 20070200187Abstract: A method (40) for fabricating a nanoscale device, includes nano-imprinting (44) a one dimensional nanostructure (20) on a material (12), forming (46) a patterning layer (22, 26) over the one dimensional nanostructure (20) and the material (12), patterning (48) the patterning layer (22, 26) to differentiate an area over the one dimensional nanostructure (20), and etching (52, 56) the differentiated area and a portion of the material (12) to create a trench (24) under the one dimensional nanostructure (20). The one dimensional nanostructure (20) is coupled to circuitry (30) formed in the material (12).Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Inventors: Islamshah Amlani, Pawitter Mangat
-
Publication number: 20070200188Abstract: A magnetic random access memory having reference magnetic resistance is provided. The memory includes at least one magnetic memory cell having an antiferromagnet layer, a pinned layer formed thereon, a tunnel barrier layer formed thereon, and a free layer formed thereon. The pinned layer and free layer are arranged orthogonally to form a reference magnetic resistance state. Through the provided MRAM structure, the access accuracy is greatly increased and the access speed is accelerated.Type: ApplicationFiled: May 1, 2007Publication date: August 30, 2007Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Chung Hung, Yung-Hsiang Chen, Ming-Jer Kao, Kuo-Lung Chen, Lien-Chang Wang, Yung-Hung Wang
-
Publication number: 20070200189Abstract: Provided is a semiconductor device for performing photoelectric conversion of incident light, including: a p-type substrate (1), an n-type well (2) having a predetermined depth and formed in a predetermined region of the p-type substrate (1), and a depletion layer generated at a junction interface between the p-type substrate (1) and the n-type well (2). In the trenches (22) having a depth larger than that of a depletion layer (K1) generated on a bottom side of the n-type well (2) and a width larger than that of depletion layers (K2, K3) generated on sides of the n-type well (2) are provided so as to remove junction interfaces (J2, J3) on the sides of the n-type well (2), and an insulating layer (21) is buried in the trenches (22).Type: ApplicationFiled: February 22, 2007Publication date: August 30, 2007Inventors: Atsushi Iwasaki, Hiroaki Takasu
-
Publication number: 20070200190Abstract: According to one embodiment, a substrate unit of the present invention comprises a first substrate, a second substrate and a coupling member. The first substrate has a first substrate main body and a circuit component. The second substrate has a second substrate main body, an opening portion provided at the second substrate main body, and a cooling module which cools the circuit component. The circuit component is mounted on a face of the first substrate main body which is opposite to the second substrate. The cooling module has a main body and a projecting portion. The coupling member fixes the main body to a second face of the second substrate main body, and couples the first substrate and the second substrate so as to fit the projecting portion in the opening portion and press the projecting portion against the circuit component.Type: ApplicationFiled: February 1, 2007Publication date: August 30, 2007Inventor: Yuuichi Koga
-
Publication number: 20070200191Abstract: Provided are a semiconductor device having a multilayer wiring structure and a method of manufacturing the semiconductor device having the multilayer wiring structure, including a method of forming an antireflection film. According to the method, no crown is produced in a contact hole, long-term reliability is high, productivity and cost efficiency are excellent, and a via hole resistance is sufficient low. A stack film which is composed of a refractory metal film and an antireflection film made of Si or a Si compound is located on a lower-layer aluminum alloy film.Type: ApplicationFiled: February 13, 2007Publication date: August 30, 2007Inventor: Kazuhiro Sugiura
-
Publication number: 20070200192Abstract: A photovoltaic apparatus includes a first photoelectric conversion portion so formed on an insulating surface of a substrate as to cover a first substrate electrode and a second substrate electrode isolated from each other by a first groove, a second photoelectric conversion portion formed on the surface of the first photoelectric conversion portion through a conductive intermediate layer, a first back electrode and a second back electrode formed on the surface of said second photoelectric conversion portion and a connecting passage portion for electrically connecting the first substrate electrode and the second back electrode, provided at a prescribed interval from the side surface of said intermediate layer.Type: ApplicationFiled: February 20, 2007Publication date: August 30, 2007Applicant: Sanyo Electric Co., Ltd.Inventor: Mataru Shinohara
-
Publication number: 20070200193Abstract: The invention relates to a component arrangement comprising a semiconductor component having a semiconductor body (100), and comprising a temperature measuring arrangement for determining a temperature at a specific position (20) in the semiconductor body, which comprises the following features: a temperature sensor (10) integrated in the semiconductor body (100), said temperature sensor being designed to generate a first temperature signal (V10) dependent on a temperature in the semiconductor body (100), a control device comprising a control amplifier (40), which has a first and a second input (41, 42) and an output (43), and comprising a low-pass filter (50) having an input (51) and an output (52), the input (51) of the low-pass filter (50) being coupled to the output (43) of the control amplifier (40), the first input of the control amplifier (40) being coupled to the temperature sensor (10) and the second input (42) of the control amplifier (40) being coupled to the output (52) of the low-pass filter (5Type: ApplicationFiled: January 19, 2007Publication date: August 30, 2007Applicant: Infineon Technologies AGInventor: Wolfgang Horn
-
Publication number: 20070200194Abstract: A current load of an electric device having a current inlet or current outlet can be protected cost-effectively and efficiently via a contact pad in the current inlet or current outlet when a first conductive material and the second conductive material are connected conductively in the contact pad such that the first conductive material and the second conductive material can form an eutectic mixture which has a fusion temperature below the fusion temperature of the individual materials and when the contact pad is additionally implemented such that the conductive connection between the first and second materials is interrupted when a fused eutectic mixture occurs.Type: ApplicationFiled: February 28, 2007Publication date: August 30, 2007Inventors: Alfons Graf, Josef Hoeglauer, Martin Schneider-Ramelow, Stefan Schmitz, Klaus-Dieter Lang
-
Publication number: 20070200195Abstract: The invention provides a high voltage MOS transistor having a high source/drain breakdown voltage of about 300V and a low on-resistance. An N-type body layer is formed extending from a source layer side to under a gate electrode. A P-type second drift layer is formed in an epitaxial semiconductor layer by being diffused deeper than a first drift layer, extending from under the first drift layer to under the gate electrode and forming a PN junction with the body layer under the gate electrode. A surface of the body layer between this second drift layer and the source layer serves as a channel region. The first drift layer is formed at a distance from a left end of the gate electrode where electric field concentration easily occurs.Type: ApplicationFiled: February 21, 2007Publication date: August 30, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Shuji Tanaka, Shuichi Kikuchi, Kiyofumi Nakaya, Kazuhiro Yoshitake
-
Publication number: 20070200196Abstract: Improved shallow trench isolation (STI) techniques are provided for semiconductor devices. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a substrate, a first trench in the substrate, and a second trench in the substrate. A first transistor region in the substrate is adjacent to and between the first and second trenches. A silicon dioxide liner substantially lines the first and second trenches. A silicon nitride liner is on the silicon dioxide liner in the first trench but not on the silicon dioxide liner in the second trench. A dielectric material fills the first and second trenches.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Anish Kumar, Moshe Agam, Gary Kwon
-
Publication number: 20070200197Abstract: A capacitor formed in an insulating porous material.Type: ApplicationFiled: February 13, 2007Publication date: August 30, 2007Applicant: STMicroelectronics Crolles 2 SASInventors: Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
-
Publication number: 20070200198Abstract: A microelectronic device is provided with at least one transistor or triode with Fowler-Nordheim tunneling current modulation, and supported on a substrate. The triode or the transistor includes at least one first block forming a cathode and at least one second block that forming an anode. The first block and the second block are supported on the substrate, and are separated from each other by a channel insulating zone also supported on the substrate. A gate dielectric zone is supported on at least the channel insulating zone, and a gate is supported on the gate dielectric zone.Type: ApplicationFiled: February 7, 2007Publication date: August 30, 2007Applicant: STMicroelectronics (Crolles 2) SASInventors: Thomas Skotnicki, Stephane Monfray
-
Publication number: 20070200199Abstract: Providing a technology capable of obtaining a desired resistance value through preferable controllability, and improving linearity between voltage and current.Type: ApplicationFiled: January 19, 2007Publication date: August 30, 2007Inventors: Susumu Murakami, Takeo Nonaka, Shinji Naito, Minoru Nakamura, Hiroshi Hozoji
-
Publication number: 20070200200Abstract: Provided are a semiconductor device including a highly precise resistor formed of a polycrystalline silicon film and a method of manufacturing the same, in which: a portion of a base insulating film below a portion of the polycrystalline silicon film which becomes a resistance region into a convex shape; and the polycrystalline silicon film which becomes the resistor is selectively formed into a thin film, while an electrode lead-out region remains thick so as to obtain the resistor with high precision, high resistivity, and a preferable temperature coefficient while preventing penetration in an opening for contact.Type: ApplicationFiled: February 13, 2007Publication date: August 30, 2007Inventor: Yuichiro Kitajima
-
Publication number: 20070200201Abstract: A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.Type: ApplicationFiled: April 27, 2007Publication date: August 30, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James DUNN, David HARAME, Jeffrey JOHNSON, Alvin JOSEPH
-
Publication number: 20070200202Abstract: A PCM structure configurable for use as a nonvolatile storage element includes a first electrode, a first phase change material layer formed on at least a portion of an upper surface of the first electrode, at least one insulating layer formed on an upper surface of the first phase change material layer, at least a second phase change material layer formed on an upper surface of the at least first insulating layer, and a second electrode formed on at least a portion of an upper surface of the at least second phase change material layer. The insulating layer is configurable for forming an aperture therethrough in response to a first signal of a prescribed level applied between the first and second electrodes, the aperture constricting a flow of current in the PCM structure to thereby create a region of localized heating in the first and second phase change material layers in response to a second signal applied between the first and second electrodes.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Applicant: International Business Machines CorporationInventors: Janusz Nowak, Yu Lu
-
Publication number: 20070200203Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.Type: ApplicationFiled: March 13, 2007Publication date: August 30, 2007Applicant: FUJITSU LIMITEDInventors: Masahiro Fukuda, Yosuke Shimamune, Masaaki Koizuka, Katsuaki Ookoshi
-
Publication number: 20070200204Abstract: A transmission line substrate includes a spurious-wave suppression circuit in which a divider divides a signal line of a driving control signal connected to a semiconductor device into two signal lines of the same phase. A delay unit is connected to one of the two signal lines, and includes a signal line with a length of substantially one half of an in-substrate effective wavelength of a spurious wave. Two parallel lines that include two parallel signal lines, on which spurious waves are in opposite phases, are connected to the delay unit and the other one of the two signal lines, respectively. A resistor is arranged on the two parallel lines, and connects between the two parallel signal lines. A combiner includes a signal line that combines the two parallel signal lines, and outputs a combined signal to the outside.Type: ApplicationFiled: June 24, 2005Publication date: August 30, 2007Inventors: Takuya Suzuki, Teruo Furuya
-
Publication number: 20070200205Abstract: An integrated circuit package system including a leadframe with an aperture formed therein. An integrated circuit package is mounted on the leadframe over or under the aperture and a die is mounted within the aperture to the integrated circuit package.Type: ApplicationFiled: February 25, 2006Publication date: August 30, 2007Applicant: STATS CHIPPAC LTD.Inventors: Dario Filoteo, Tsz Yin Ho
-
Publication number: 20070200206Abstract: A lead frame (10) for a semiconductor device includes a first row of terminals (12) surrounding a die receiving area (14) and a second row of terminals (16) spaced from and surrounding the first row of terminals (12). The first and second rows of terminals (12, 16) have a first height (H1). The terminals (12) of the first row include a step (26) that has a greater height (H2). Bond wires (36) connecting die pads (34) to the first row terminals (12) extend over the second height H2 part of the terminal (12) and are attached to the first height H1 part of the terminal (12). The step (26) insures that the bond wires (36) attached to the stepped terminals (12) have a high wire kink profile so that they are less susceptible to damage in later process steps.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Inventors: Fei Wong, Wai Ho, Ho Wong
-
Publication number: 20070200207Abstract: A no-lead electronic package including a heat spreader and method of manufacturing the same. This method includes the steps of selecting a matrix or mapped no-lead lead frame with die receiving area and leads for interconnect; positioning an integrated circuit device within the central aperture and electrically interconnecting the integrated circuit device to the leads; positioning a heat spreader in non-contact proximity to the integrated circuit device such that the integrated circuit device is disposed between the leads and the heat spreader; and encapsulating the integrated device and at least a portion of the heat spreader and leads in a molding resin.Type: ApplicationFiled: February 2, 2007Publication date: August 30, 2007Inventors: Mary Ramos, Romarico Antonio, Anang Subagio
-
Publication number: 20070200208Abstract: A variable-tooth gear with sliding-sheet deforming teeth pertains to the technical fields of gearing, and continuously variable mechanical transmissions. The variable-tooth gear is designed in accordance with “the principle of configuring variable-teeth through infinitely deforming sliding-sheets”. The working surface is composed of a large number of thin sliding-sheets (sliding-needles) superposed on one another. The meshing tooth profiles of arbitrary shapes can be configured by the free and infinite sliding of the sliding-sheets. Since the direction of sliding of the sliding-sheets is different from the direction of forces acting thereupon, the sliding-sheets can freely deform with the current tooth profiles. The direction of the force acting upon the sliding-sheet when transmitting power is perpendicular to the free-sliding direction, or the angle therebetween is within the equivalent friction angle, therefore the sliding-sheet possesses the self-locking property.Type: ApplicationFiled: March 20, 2007Publication date: August 30, 2007Inventor: Guobin Wang
-
Publication number: 20070200209Abstract: A semiconductor device includes a semiconductor element mounted on a substrate; at least one electronic part arranged around the semiconductor element; and a heat radiation member bonded to a backside of the semiconductor element by a bonding material. The heat radiation member has an isolation part extending between an outer circumference of the semiconductor element and the electronic part.Type: ApplicationFiled: August 9, 2006Publication date: August 30, 2007Applicant: FUJITSU LIMITEDInventor: Kenji Fukuzono
-
Publication number: 20070200210Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMT) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. A planar rim portion of the cap that surrounds the cavity is coupled to the leadframe. The cap and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Applicant: Broadcom CorporationInventors: Sam Zhao, Rezaur Khan
-
Publication number: 20070200211Abstract: In the case in which an electrical connection between upper and lower layers is to be carried out through a via opening portion 16 provided on an insulating layer 14 of a wiring substrate constituting a multilayer wiring substrate, the electrical connection between the upper and lower layers is performed through a conductive material 30 while exposing a part of wall surfaces of the via opening portion 16 of the insulating layer without covering all of the wall surfaces of the via opening portion 16 with the conductive material 30.Type: ApplicationFiled: February 13, 2007Publication date: August 30, 2007Inventors: Tsuyoshi Kobayashi, Shigetsugu Muramatsu
-
Publication number: 20070200212Abstract: An image sensor package includes a substrate, a lens module and a bottom cover. Herein the substrate has an upper surface and a lower surface, a plurality of passive components is fabricated on the lower surface and a chip is disposed on the upper surface. The lens module is mounted on the substrate and covers the chip. The bottom cover is connected to the lower surface of the substrate to enclose the passive components.Type: ApplicationFiled: December 27, 2006Publication date: August 30, 2007Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Ming-Hsiang Cheng
-
Publication number: 20070200213Abstract: An integrated circuit chip and a package supported by a device or a semiconductor chip are provided. The integrated circuit chip comprises a substrate, a device part, and a first integrated circuit chip. The device part is formed over the substrate, and the first integrated circuit chip is formed over the device part. The area occupied by the integrated circuit chip can be reduced. This reduction in area allows miniaturization of devices, cost reduction, improvement in productivity, and minimization of an occurrence of electrical interference between integrated circuit chips. As a result, it is possible to prevent degradation of the performance.Type: ApplicationFiled: February 6, 2007Publication date: August 30, 2007Inventors: Seok Phyo TCHUN, Kyung Oh Kim, Bo-Eun Kim
-
Publication number: 20070200214Abstract: Provided is a board strip that includes a base substrate that has at least one hole and a plurality of functional portions in which at least one semiconductor chip is packaged; a circuit layer having a circuit pattern formed on the functional portions and dummy patterns formed on non-functional portions which are formed on a surface of the base substrate respectively; a protective layer formed on the circuit layer; and at least one vacuuming hole seating unit that is formed in a portion of the non-functional portions, is disposed on a portion that contacts a vacuuming hole, and is flat without a step difference.Type: ApplicationFiled: February 20, 2007Publication date: August 30, 2007Applicant: Samsung Techwin Co., Ltd.Inventor: Bong-hui Lee
-
Publication number: 20070200215Abstract: A chip card module including a substrate with a first side and an opposite second side. Contact areas are arranged on the first side, and a first conductor structure is arranged on the second side, the first conductor structure runs from one contact region to one of a another contact region and a second conductor structure, which is connected to the contact areas by means of a through connection in the substrate, so that the first conductor structure runs at least partly in a central region. The chip card module also includes a chip with connections which are arranged over the central region on the second side of the substrate, one of the connections being connected to the one contact region.Type: ApplicationFiled: February 27, 2007Publication date: August 30, 2007Applicant: INFINEON TECHNOLOGIES AGInventors: Marcus Janke, Peter Laackmann
-
Publication number: 20070200216Abstract: Provided is a chip stack package that may include a lower semiconductor chip, an upper semiconductor chip stacked on the lower semiconductor chip, and at least one adhesive formed in space between the lower semiconductor chip and the upper semiconductor chip. The at least one adhesive may include a first adhesive and a second adhesive. The first adhesive may be formed in a portion of the space, and the second adhesive may be formed in the space except for a region in which the first adhesive is provided. The space between adjacent semiconductor chips may be completely filled with the at least one adhesive. Therefore, a chip stack package according to the exemplary embodiments of the present invention may exhibit improved mechanical stability and reliability.Type: ApplicationFiled: December 19, 2006Publication date: August 30, 2007Inventors: Soon-Bum Kim, Ung-Kwang Kim, Kang-Wook Lee, Se-Young Jeong, Young-Hee Song, Sung-Min Sim
-
Publication number: 20070200217Abstract: After a first electronic component is inserted into a base substrate, first circuit patterns are formed on the inserted first electronic component, and then a second electronic component is mounted on the first circuit patterns to complete an electronic component-mounted component. According to the above method, a thickness of a module may be decreased by a thickness of the base substrate. Further, since electronic components are surface-mounted, electronic components of arbitrary sizes and types may be used.Type: ApplicationFiled: January 16, 2007Publication date: August 30, 2007Inventors: Norihito Tsukahara, Daisuke Sakurai
-
Publication number: 20070200218Abstract: An IC which includes a first circuit and a plurality of first paired terminals each including a first power supply terminal and a first GND terminal which are connected to the first circuit, and a second circuit and a plurality of second paired terminals each including a second power supply terminal and a second GND terminal which are connected to the second circuit. The first and second paired terminals are isolated inside. A printed board with the IC mounted has an inductor which is provided in a route that guides a wiring line from the first GND terminal to the second GND terminal and the GND of the printed board. The printed board has a portion where each of the first GND terminals is arranged inside the terminal array of the IC. The inductor suppresses a high-frequency potential variation generated by the operation of the first circuit.Type: ApplicationFiled: February 13, 2007Publication date: August 30, 2007Applicant: CANON KABUSHIKI KAISHAInventor: Takuya Mukaibara
-
Publication number: 20070200219Abstract: A power semiconductor device (1; 37) has a leadframe (4), at least one vertical power semiconductor component (2) and at least one further electronic device (3) which is arranged on the power semiconductor component (2). The chip carrier (5) of the leadframe (4) has at least two separate parts (7, 8) on which the power semiconductor component (2) is arranged. The power semiconductor component (2) is embodied such that the lower surface (28) of the first part (7) of the chip carrier (5) provides a ground contact area (36) of the power semiconductor component (2).Type: ApplicationFiled: February 21, 2007Publication date: August 30, 2007Inventor: Ralf Otremba
-
Publication number: 20070200220Abstract: A flexible substrate is provided which contains not only flexibility but also rigidity and hear resistance. A flexible substrate includes a first wiring layer, an insulating resin layer, a glass cloth and a second wiring layer. The insulating layer is formed by an insulating material, such as a BT resin, epoxy resin or the like that contains a high elastic modulus, heat resistance and moisture resistance. The film thickness of the insulating resin layer is thinned down to about 60 ?m. As a reinforcing material, the glass cloth is embedded in the insulating resin layer. With this structure, the flexible substrate attains flexibility and at the same time in any of the first wiring layer and the second wiring layer, circuit elements can be mounted both on a curved area and a non-curved area of the wiring layers.Type: ApplicationFiled: February 23, 2007Publication date: August 30, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Makoto Murai, Ryosuke Usui
-
Publication number: 20070200221Abstract: An electronic component module is provided with a ceramic substrate and a plurality of bonding material applying lands. The ceramic substrate has a rear surface that is substantially rectangular. The plurality of bonding material applying lands are arranged on the rear surface. The plurality of bonding material applying lands includes outer peripheral land rows, each of which is arranged in a line along each side of the rear surface with the exception of corner portions of the rear surface. The plurality of bonding material applying lands includes corner portion inner lands, each of which is arranged on the rear surface at a location that is shifted inwardly in a substantially diagonal direction from the corner portion and is adjacent to the bonding material applying lands closest to the corner portion at ends of the outer peripheral land rows that are arranged in lines along two sides that are connected by the corner portion.Type: ApplicationFiled: May 2, 2007Publication date: August 30, 2007Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Tsuyoshi SUESADA, Kazuaki HIGASHIBATA, Toshihiro HOSOKAWA, Masaki KAWATA
-
Publication number: 20070200222Abstract: A MEMS (micro electro-mechanical system) semiconductor device and a method for producing such a device. A preferred embodiment of the present invention comprises the a wafer having a continuous BCS (bondline control structure) surrounding a MEMS active area that is affixed to an interposer layer, which is in turn affixed to a cover to form a sealed cavity over the surface of the MEMS. To fabricate this device, a wafer is populated with MEMS devices. The BCS is formed in the same process step as a device structure, for example a spacer layer. The BCS remains, however, even if all or a portion of this spacer layer is removed. In this way when the reflecting surface of the MEMS device has been formed, an interposer layer may be mounted to the BCS using a filler-less adhesive, and a cover can likewise be affixed to the interposer layer.Type: ApplicationFiled: February 27, 2006Publication date: August 30, 2007Inventors: John Ehmke, James Hall
-
Publication number: 20070200223Abstract: A semiconductor device capable of dissipating heat with a high degree of efficiency without impairing the strength thereof is provided. The semiconductor device includes a semiconductor chip 2, a heatsink plate 1 overlapping a rear face of the semiconductor chip 2, and an adhesive 4 for adhesively fixing the semiconductor chip 2 and the heatsink plate 1 to each other. In the rear face of the semiconductor chip 2, there is formed a depressed portion 7 right under a heat generating portion 6 of the semiconductor chip 2. On the front face of the heatsink plate 1, there is formed a protruding portion 8 that is to fit in the depressed portion 7.Type: ApplicationFiled: January 31, 2007Publication date: August 30, 2007Applicant: SHARP KABUSHIKI KAISHAInventor: Atsuo Konishi
-
Publication number: 20070200224Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.Type: ApplicationFiled: February 20, 2007Publication date: August 30, 2007Applicant: STMicroelectronics, Inc.Inventors: Tiao Zhou, Michael Hundt