Abstract: A heat sink (10) for a semiconductor package (38) includes a top surface (12) having a recessed hole (16) at its center. A sidewall (14) formed around the top surface (12) of the heat sink (10) has gaps (18) formed in the sidewall (14). An air vent (22) is formed at a corner of the heat sink (10). The heat sink (10) is used for center gate molding. Mold compound (24) enters the recessed hole (16), covers an IC die 30, and exits via the gaps (18). During mold injection, air escapes through the air vent (22).

Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing micro-channels or micro-trenches, and a technique for fabricating the same.

Abstract: A power semiconductor arrangement has a heat-removing base with at least one planar exterior. The base consists of a metal material or is provided with a metal coat. The exterior is at least partially provided with an electrically insulating oxide layer on top of the metal material. The power semiconductor arrangement also has a power semiconductor component that is disposed on the one exterior of the base in such a manner that it is electrically insulated from the base by the oxide layer. An electrically insulated film is at least partially laminated onto the one exterior across the power semiconductor component. The film, in the area of the power semiconductor component, is provided with recesses for contacting the power semiconductor component. An upper metallization layer is applied to the power semiconductor component on top of the film and its recesses across a large area thereof or in a structured manner.

Abstract: A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package.

Abstract: A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.

Abstract: A stackable integrated circuit package system is provided placing a first integrated circuit die having an interconnect provided thereon in a substrate having a cavity, encapsulating the first integrated circuit die, having the interconnect exposed, in the cavity and along a first side of the substrate, mounting a second integrated circuit die to the first integrated circuit die, and encapsulating the second integrated circuit die along a second side of the substrate.

Abstract: According to one embodiment, there is provided a printed-wiring board with a built-in component including a first base material including a pattern forming surface on which a plurality of conductive patterns are formed. A circuit component is mounted on the pattern forming surface of the first base material, and is connected to the conductive patterns of the first base material. A filling material is stacked on the pattern forming surface of the first base material, and fills in a gap between the circuit component and the pattern forming surface. A second base material is stacked on the pattern forming surface of the first base material by interposing the filling material between the pattern forming surface and the second base material.

Abstract: A bond pad structure with reduced coupling noise is provided. An exemplary embodiment of the bond pad structure comprises a first dielectric layer with a first conductive layer therein, wherein the first conductive layer is grounded. A second dielectric layer with a second conductive layer, a plurality of conductive contacts and a conductive line therein is formed to overly the first dielectric layer. A bond pad layer is formed over the second conductive layer, wherein the second conductive layer and the first conductive layer are superimposed, the bond pad layer and the second conductive layer have a surface area less than that of the first conductive layer, and the conductive contacts electrically connect the first conductive layer to form a noise shield from the sides and bottom of the bond pad layer.

Abstract: A flip-chip and underfilled device, which includes a semiconductor chip (101) with contact pads and a workpiece (102) with contact pads in matching locations; the workpiece may be an insulating substrate or another semiconductor chip. The workpiece and the chip are spaced by a gap (103) of substantially uniform average width. Attached to each chip contact pad is a column-shaped spacer (140), which includes two or more deformed spheres of non-reflow metals, preferably gold, bonded together to a height about equal to the gap width. The spacer is attached to the contact pad (110) substantially normal to the chip surface and extends from the chip pad to the matching workpiece pad (120); it is bonded to the workpiece pad by reflow metals (141) such as tin or tin alloy, which covers at least portions of the workpiece pad and the spacer. The gap may be filled with a polymer material (105) surrounding the reflow metal and spacers.

Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.

Abstract: A semiconductor integrated circuit device includes: a semiconductor substrate; a semiconductor chip including a plurality of functional blocks formed independently from each other in predetermined regions of the semiconductor substrate and each including a pad for transmitting a signal; and a plurality of inter-pad interconnects being connected to the pads and being capable of being cut. Signal transmission between the respective functional blocks is performed through the respective inter-pad interconnects.

Abstract: An interlayer insulator includes a first interlayer insulator and a second interlayer insulator formed on the first interlayer insulator and having a property of preventing diffusion of copper. A barrier metal film is formed on an inner wall in the wiring trench except an upper end and operative to prevent copper contained in the Cu wiring from diffusing into the interlayer insulator. The Cu wiring is brought into contact with the second interlayer insulator at the upper end and covered with the barrier metal film at a lower portion below the upper end.

Abstract: In a semiconductor integrated circuit apparatus formed by a core cell constituting a circuit function and a power wiring cell including a power wiring, a metal of a power wiring unit cell constituting the power wiring cell is formed to take a shape of T, and the power wiring unit cell is disposed adjacently, thereby forming a serial power wiring. The core cell and the power wiring cell are connected to each other through a metal wiring in the core cell in which coordinates in a horizontal direction are preset, and a power signal is thus supplied.

Abstract: A redistribution connecting structure for solder balls is disclosed. A substrate includes a plurality of bonding pads. A plurality of dielectric layers, a redistribution conductive layer between the dielectric layer, and a plurality of solder balls are formed on the substrate. The redistribution layer has a redistribution pad disposed adjacent to one of the bonding pads without electrical connection with the redistribution pad. One of the dielectric layers covering the redistribution conductive layer has an opening to partially expose the redistribution pad, in which the opening is approximately circular and has a cut-off portion so that the opening is adjacent to an opening of another of the dielectric layers exposing one of the bonding pads without overlapping. Accordingly, bonding area of the redistribution pad for a bonding pad under one of the solder balls can be expanded to reduce stress effect.

Abstract: A semiconductor device includes a lower pad layer, an insulating layer and an upper pad layer. The lower pad layer is provided on a semiconductor substrate. The insulating layer is away from a surrounding of the lower pad layer so that a space having a recess on a surface between the lower pad layer and the insulating layer is formed. The upper pad layer covers over the lower pad layer and the space, extends to an upper face of the insulating layer, and has an area larger than that of the lower pad layer.

Abstract: A non-ESL semiconductor interconnection structure and a method of forming the same are provided. The non-ESL semiconductor interconnection structure includes a first low-k dielectric layer comprising a first region and a second region overlying the substrate, a plurality of conductive features in the first low-k dielectric layer, a cap layer on at least a portion of the conductive features, and a dielectric capping layer overlying the first low-k dielectric layer in the second region but not in the first region. The conductive features in the second region have a substantially greater spacing than the conductive features in the first region. The dielectric capping layer preferably has an inherent compressive stress.

Abstract: In a semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus includes a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-layer plug wire. The first-layer plug wire may include a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern.

Abstract: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-containing precursor chemical such as TDEAT, followed by a mixture of ammonia and carbon monoxide or carbon monoxide alone, and repeating to form a sequentially deposited TiN structure. Such a TiN layer may be used as a diffusion barrier underneath another conductor such as aluminum or copper, or as an electro-migration preventing layer on top of an aluminum conductor. ALD deposited TiN layers have low resistivity, smooth topology, high deposition rates, and excellent step coverage and electrical continuity.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: Capacitance generated by a dummy pattern can be reduced without lowering wiring density by arranging the dummy pattern on one wiring layer in a manner responding to an actual pattern or the dummy pattern on the other wiring layer, whereby at least one of the following can be improved: distances between dummy patterns on different wiring layers, overlapped areas of dummy patterns, and such side length of the dummy pattern as opposed to the actual pattern on the same wiring layer.

Abstract: A chip package including a flexible substrate, a plurality of conductive plugs, a wiring layer, and a chip is provided. The flexible substrate has a first surface and a second surface opposite to the first surface. The conductive plugs pass through the flexible substrate. The wiring layer is located on the first surface and has a plurality of inner leads electrically connected to the conductive plugs respectively. The chip has an active surface and a plurality of bumps on the active surface, wherein the chip is disposed on the second surface of the flexible substrate and connected with the conductive plugs by the bumps. As bumps on the chip are electrically connected to the conductive plugs by hot pressing, the chip is quickly and reliably electrically connected to the inner leads.

Abstract: An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

Abstract: A stacked integrated circuit package system is provided forming a lead and a die paddle from a lead frame, forming a first integrated circuit die having an interconnect provided thereon, placing a second integrated circuit die over the first integrated circuit die and the die paddle, connecting the second integrated circuit die and the lead, and encapsulating the first integrated circuit die and the second integrated circuit die with a portion of the lead and the interconnect exposed.

Abstract: The invention provides a wiring board (2,15) to which a semiconductor chip (3) is to be bonded while directing a surface of the semiconductor chip toward the wiring board. The wiring board includes a connection electrode (14) that is formed on a bonding surface (2a, 15a) to which the semiconductor chip is to be bonded and that is used to make a connection with the semiconductor chip, an insulating film (6) that is formed on the bonding surface and that has an opening (6a) to expose the connection electrode, and a low-melting-point metallic part (16) that is provided on the connection electrode in the opening and that is made of a low-melting-point metallic material whose solidus temperature is lower than that of the connection electrode.

Abstract: A semiconductor device using lead technology includes a semiconductor chip with external side electrodes of semiconductor components disposed on its top side. On its rear side, the semiconductor chip is connected to a rear side internal lead adapted to the rear side of semiconductor chip. On its top side, the semiconductor chip is connected a plurality of top side internal leads. The top side internal leads are electrically connected to external leads of the semiconductor device.

Abstract: Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film. each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to complete a flip-chip package. According to the present invention, by employing the three-dimensional structured solder bumps, it is possible to lower the height of the solder bumps, thereby improving the reliability of an ultra thin flip-chip package.

Abstract: According to one embodiment, a circuit board apparatus includes a substrate mounting a semiconductor component. A circuit board mounts the substrate. A solder bonding portion is provided in a side surface of the substrate. A pad is provided on the circuit board and solder bonded to the solder bonding portion.

Abstract: Methods are provided for forming an electronic assembly (54). At least one depression (38) is formed in a surface of a substrate (20). A contact formation (44) is placed in the depression. A microelectronic die (46) is attached to the substrate using the contact formation. An electronic assembly is also provided. The invention further provides an electronic assembly. The electronic assembly includes a substrate having a plurality of depressions formed thereon, a microelectronic die having a microelectronic device formed therein, and a plurality of contact formations bonded to and interconnecting the substrate and the microelectronic die. Each of the contact formations are positioned within a respective depression on the substrate.

Abstract: A method of creating an active electrode that may include providing a flex circuit having an electrode made of a first material and providing a first mask over the flex circuit, the first mask having an offset region and an opening that exposes the electrode. The method may also include depositing a second material over the offset region and the opening, the second material being different from the first material and providing a second mask over the second material, the second mask having an opening over a portion of the second material that is over the offset region.

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.

Abstract: In a wiring configuration for a semiconductor component, an unused terminal is insulated from a third land via an insulating film, and thus no connecting member (solder) is required for the unused terminal. With this, the third land is not accidentally removed from a circuit board during exchange of the semiconductor component, and the number of defective circuit boards can be reduced. Moreover, the third land for the unused terminal is included in a wiring pattern due to the connection thereof to other lands or other traces for signals and for grounding with a connecting trace. Thus, the widths of lines can be increased, and furthermore, the insusceptibility of transmission lines in high-frequency circuits to noise can be increased.

Abstract: A stackable integrated circuit package system is provided forming a first integrated circuit die having an interconnect provided thereon, forming an external interconnect, having an upper tip and a lower tip, from a lead frame, mounting the first integrated circuit die on the external interconnect with the interconnect on the lower tip and below the upper tip, and encapsulating around the interconnect with an exposed surface.

Abstract: A semiconductor device includes semiconductor device components embedded in plastic package compound, with a buffer layer being arranged on surfaces of the semiconductor device components of the semiconductor device. The buffer layer includes a thermoplastic material.

Abstract: The touch panel of the invention includes an optically transparent upper substrate having an upper conductive layer formed on an undersurface thereof, an optically transparent lower substrate having a lower conductive layer formed on an upper surface thereof and facing the upper conductive layer with a predetermined space, a spacer in a frame shape disposed between the upper substrate and the lower substrate, and a polarizing plate adhered to an upper surface of the upper substrate, in which the polarizing plate is adhered to the upper surface of the upper substrate within the outer periphery of the spacer.

Abstract: The invention is a method and apparatus for generating vortex rings in a fluid medium. The apparatus is immersed in a body of water and includes first and second bodies. Gas is fed into a concave surface of the first body via a conduit from a finite or infinite supply source. As gas is supplied to the concave surface a single unitary bubble is formed therein. When the volume of the gas in the concave surface has attained the volume of the concave surface, the unitary bubble travels as a single unit to an exit aperture. A vacuum is formed between the two bodies when the unitary bubble enters the exit aperture. This vacuum functions to pull the entire unitary bubble through the aperture. Following departure from the exit aperture, a toroidal shaped bubble is formed.

Abstract: A surface aerator for mixing gas and liquid is disclosed. The surface aerator has an upwardly pumping impeller located within a draft tube. A flow diverter redirects pumped liquid from the impeller traveling in an upward direction to a radially outward direction where it impacts and aerates the remaining liquid in a vessel. A baffle extends radially at a shallow depth to a point beyond the impact area of the liquid to provide separation of the impact area from the rest of the liquid and promote aeration.

Abstract: An apparatus for mixing gas and liquid is disclosed. The apparatus can comprise a draft tube having a gas conduit, a liquid inlet and a gas-liquid outlet, an impeller rotatably mounted within the draft tube. The gas can be entrained into the liquid by rotation of an impeller having relatively high angular velocity, which generates relatively low axial velocity of the liquid and relatively low angular velocity of the liquid. Floats may support the impeller and the impeller may have means for maximizing aeration of the liquid.

Abstract: A light diffusion plate obtained by injection molding of a thermoplastic resin and having an approximately rectangular shape having a length of a diagonal line of 400 mm or longer, wherein the fluctuation in the thickness is 200 ?m or smaller, the warp is 2 mm or smaller, the fluctuation in the transmittance is 8% or smaller and the dispersion in the y-value of the reflected light is 0.004 or smaller, and a process for producing the light diffusion plate are provided. The light diffusion plate exhibits the high luminance and the small unevenness in the luminance and provides a display of images having an excellent quality on liquid display devices.

Abstract: The present invention is directed to apparatus and a method for reshaping a footwear shell, the apparatus includes a support structure, a drive mechanism and external mold arrangement that drives the external mold toward or away from the shell being reshaped; and an internal mold assembly that includes an angled support arm having a first leg adapted to couple to one of a selection of couplings provided in the support structure and a second leg offset from the first leg at an angle ?. The internal mold assembly also includes an adapter that is rotatably fixed to the second leg of the angled support arm, and a static mold removably fixed to the adapter and coaxially aligned with a common axis extending through the external mold and static mold, the support arm angle ? provides an improved support shape that improves placement of the static mold within the footwear shell during reshaping.

Abstract: A method of making a non-pneumatic tire comprising a toroidal-shaped tube having inner and outer circumferential surfaces and opposite side surfaces collectively forming a hollow chamber therebetween, the tube having at least two openings proximate the inner circumferential surface, and a solid fill composition disposed in the hollow chamber of the tube. The non-pneumatic tire provides the benefits of a smooth, comfortable ride, durability, and lightweight with good load-carrying capability.

Abstract: A method for producing a cross-linked PVC rigid-foam body from a starting mixture containing PVC, an isocyanate or polyisocyanate, an organic anhydride and a chemical expanding agent by: converting the starting mixture into a molded article inside a compacting device under the action of pressure and heat; removing the article from the mold, and; expanding and hardening the obtained molded article in an expanding device while supplying heat and water and/or water vapor whereby forming a cross-linked PVC foam body. The starting mixture contains epoxidized compounds in amounts greater than 3% by weight, preferably greater than 5% by weight, and less than 15% by weight with regard to the starting mixture.

Abstract: The present disclosure provides a method and apparatus for coating a medical device.

Abstract: A biocompatible material may be configured into any number of implantable medical devices including intraluminal stents. Polymeric materials may be utilized to fabricate any of these devices, including stents. The stents may be balloon expandable or self-expanding. The polymeric materials may include additives such as drugs or other bioactive agents as well as radiopaque agents. By preferential mechanical deformation of the polymer, the polymer chains may be oriented to achieve certain desirable performance characteristics.

Abstract: A method of molding a toner bottle including separating polyethylene terephthalate (PET) bottles that have not accommodated oily or colored materials from retrieved PET bottles grinding the separated PET bottles to obtain a flake PET material of which not less than 80% has a form from a triangle to an octagon with a size not greater than 8 mm 8 mm, washing and drying the flake PET material to obtain a flake PET molding material and molding the flake PET molding material to make a toner bottles

Abstract: A process for the production of tapes from a web of polymeric material, as well as an apparatus for carrying out the process, in which a polymer melt is extruded to form the web, which is then cooled, and drawn off. The web is then cut to form a tape sheet composed of a plurality of tapes. According to the invention, before its drawing, the sheet of tapes is divided into several groups of tapes and drawn separately. For this, a drawing device is provided with which the tapes are drawn separately after division of the sheet of tapes.

Abstract: A biocompatible material may be configured into any number of implantable medical devices including intraluminal stents. Polymeric materials may be utilized to fabricate any of these devices, including stents. The stents may be balloon expandable or self-expanding. The polymeric materials may include additives such as drugs or other bioactive agents as well as radiopaque agents. By preferential mechanical deformation of the polymer, the polymer chains may be oriented to achieve certain desirable performance characteristics.

Abstract: Disclosed is a method for viscosity breaking of a polypropylene polymer, a polypropylene copolymer or a polypropylene polymer blend, which process comprises adding a chain transfer agent and an initiator to a polypropylene polymer, polypropylene copolymer or polypropylene polymer blend and heating the resultant composition. The chain transfer agent has a Cs value of greater than or equal to about 0.04 as measured in ethylene polymerization at 130° C. The initiator is for example an organic or inorganic peroxide, a carbon based radical generator, a bis azo compound, a stable nitroxyl compound, a sterically hindered NO-acyl compound or a sterically hindered alkoxyamine compound.

Abstract: In a vibration welding structure for fixing an attachment to an instrument panel (12), a first projection (70) resiliently deformable in a predetermined vibrating direction is provided on the instruction panel (12) so as to project from the instrument panel (12) toward an air conditioner duct (15). First fitting groove portion (72) is formed in the air conditioner duct (15) for fitting engagement with a distal end portion (70a) of the first projection (70). Further, a first positioning mechanism (74) is provided between the instrument panel (12) and the air conditioner duct (15) for positioning the air conditioner duct 15 in a direction perpendicular to the vibrating direction.

Abstract: The present invention provides fluoropolymer laminates having isotropic properties. For example, an embodiment in which multiple fluoropolymer sheets having an liquid crystalline polymer oriented in the fibrous state in the melt processible fluoropolymer are laminated, despite having the fibrous LCP oriented in one direction in each single extruded sheet, makes it possible to laminate in such a way as to compensate for their orientation directions, the laminate thereby becoming isotropic as regards physical properties. The laminates also have low linear coefficient of expansion and low thermal shrinkage as well as elevated tensile modulus and low dielectric constant.

Abstract: The present invention relates to a process for obtaining at least one abrasive portion for a substantially blade-like cutting tool for cutting building materials comprising the steps of: prearranging a mixture comprising at least one abrasive component and at least one filling matrix component based on a mouldable pasty material, and injection molding said mixture in at least one seat (2, 2a, 2b, 2c) of a mold (1, 1a, 1b, 1c).