Patents Issued in August 30, 2007
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Publication number: 20070200576Abstract: A probe for a probe card assembly is provided. The probe has a post structure supported by a substrate, a plurality of stacked beam elements disposed on the post structure, and a tip attached to a surface of a top beam element, of the plurality of stacked beam elements, that opposes the substrate. The tip is configured to be electrically connected to a semiconductor device to be tested. The probe may be bent so that the tip is further away from the substrate than the height the post structure. The effective maximum force exerted by the tips of a multi-beamed probe against, for example, DUT pads may be increased when compared to prior probes.Type: ApplicationFiled: February 7, 2007Publication date: August 30, 2007Inventors: Edward Laurent, Edward Malantonio, Richard Sadler, Bahadir Tunaboylu, Brian McHugh, Dov Chartarifsky
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Publication number: 20070200577Abstract: A method and apparatus for repairing a probe on a probe card is provided. A plurality of beams is formed on a beam panel. The plurality of beams includes a replacement beam. After identifying a damaged beam on the probe card, the damaged beam is removed from the probe card. The beam panel is aligned with the probe card. After the beam panel is aligned, the aligned beam panel is temporarily affixed to the probe card. After the beam panel is temporarily affixed to the probe card, the replacement beam is affixed at a location previously occupied by the damaged beam. After the replacement beam is affixed at the location, the beam panel is removed from the probe card.Type: ApplicationFiled: February 7, 2007Publication date: August 30, 2007Inventors: Bahadir Tunaboylu, John McGlory, Horst Clauberg, Bruce Griffing, Robert Werner, Edward Laurent, Edward Malantonio, Alan Slopey, Paul Berenycky
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Publication number: 20070200578Abstract: A probe assembly for performing circuit inspection of semiconductor chips according to which a resin film with copper foil attached thereto is used to form a conductive portion including a vertical probe on the resin film by etching the copper foil, plural sheets of the resin film with the vertical probe are laminated, and end portions of the vertical probes are brought into contact with electrode pads of the chips.Type: ApplicationFiled: February 15, 2007Publication date: August 30, 2007Inventor: Gunsei Kimoto
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Publication number: 20070200579Abstract: An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated test circuit also receives response signals from the integrated circuit sockets indicative of the manner in which integrated circuits in the sockets responded to the test signals. Several of the load boards may be placed on a test head that may be coupled to a host.Type: ApplicationFiled: April 6, 2007Publication date: August 30, 2007Applicant: Micron Technology, Inc.Inventors: Joseph Jeddeloh, Robert Totorica
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Publication number: 20070200580Abstract: The present invention relates to a probe for testing of integrated circuits or other microelectronic devices.Type: ApplicationFiled: April 26, 2007Publication date: August 30, 2007Inventors: Leonard Hayden, John Martin, Mike Andrews
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Publication number: 20070200581Abstract: A temperature-controlled system for testing a laser die mounted on a submount is disclosed. The testing system comprises a base having a motor-driven translation platform. The translation platform includes a first testing site having a two-stage temperature control system mounted on a base portion. The temperature control system includes a thermoelectric cooler and a fluid system for circulating a cooling/heating fluid in a circulation block. A mounting portion is also included on the first testing site on which the submount is positioned. The temperature of the mounting portion is controlled by the temperature control system. A probe card having an arm and an electrical contact portion attached to the arm provides a power supply to the submount when the first testing site is aligned with the probe card. An aligner having a lens assembly that is alignable with the first testing site receives an optical signal produced by the laser.Type: ApplicationFiled: February 13, 2007Publication date: August 30, 2007Applicant: Finisar CorporationInventors: Ting Shi, Daniel Tran, Pavel Ploscariu
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Publication number: 20070200582Abstract: A probe 10 to be used when inspecting characteristics of an object of inspection includes: a bar-shaped base member 3 forming a main body; a nickel plating layer 4 constituting a ground layer and a gold plating layer 5 constituting an outermost layer formed on a surface of the base member 3; and a plurality of square-pyramidal 1 protrusions formed in a lattice-like fashion at one end of the base member 3 and brought into contact with the object of inspection.Type: ApplicationFiled: July 10, 2006Publication date: August 30, 2007Applicant: FUJITSU LIMITEDInventor: Toshihiro Ishizuka
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Publication number: 20070200583Abstract: A plunger is suitable for a chip-testing module having a probe card, which has a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, conductive through-vias penetrating the membrane, and bumps disposed on a second membrane surface opposite to the first membrane surface, located in a pushed area of the membrane, and electrically connected to the circuit layer through the conductive through-vias. The plunger includes a body having a pushing part and a base part and a conductive layer disposed on a surface of the pushing part and the base part. Part of the circuit layer located in the pushed area is suitable for contacting and being electrically connected to part of the conductive layer located on the pushing part. The bumps are electrically connected to the conductive layer through the conductive through-vias.Type: ApplicationFiled: July 10, 2006Publication date: August 30, 2007Inventors: Hsin-Kuan Wu, Hsing-Chou Hsu
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Publication number: 20070200584Abstract: A cantilever-type probe card includes a circuit board having a first surface on which a plurality of signal contact pads and grounding contact pads are formed, a locating ring mounted on the first surface of the circuit board, and a plurality of probe pins, each of which is partially supported by the locating ring. Each of the probe pins has an electrically conducting core having an exposed first end electrically connected to one of the signal contact pads of the circuit board, and an exposed second end suspending outside the locating ring for probing a test contact, and a metal film insulatively spaced from the electrically conducting core and electrically connected to one of the grounding contact pads of the circuit board.Type: ApplicationFiled: February 9, 2007Publication date: August 30, 2007Applicant: MJC Probe Inc.Inventor: Wei-Cheng Ku
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Publication number: 20070200585Abstract: A semiconductor wafer of the present invention includes switch circuits each connecting a corresponding internal circuit formed in the semiconductor chip and the test pad. The semiconductor wafer also includes switch control pads which are provided in the scribing region or the semiconductor chips. Voltages of the switch control pads are pulled up or down to a voltage that is equal to a substrate voltage of the semiconductor wafer. The switch control pads are provided with signals whose voltages are different from the substrate voltage so that the switch circuits are turned on. Moreover, each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to at least one of said switch circuits of each of the adjacent semiconductor chips.Type: ApplicationFiled: February 5, 2007Publication date: August 30, 2007Inventors: Noboru Takeuchi, Takahiro Inoue
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Publication number: 20070200586Abstract: A method of testing for power and ground continuity of a semiconductor device having Input and Output (IO) pins and at least a pair of power and ground pins includes identifying the power and ground pins of the device. A victim pin is selected from the IO pins of the device for each pair of the power and ground pins, and an aggressor pin for each victim pin is selected from the remaining IO pins. The aggressor pins are toggled between a high state and a low state. A level of switching noise on each victim pin is measured, and the measured levels of switching noise are compared with predetermined data to determine power and ground continuity of the device.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Inventors: Wai Phoon, Vivien Wong, Wah Tan
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Publication number: 20070200587Abstract: This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUTs) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.Type: ApplicationFiled: September 15, 2006Publication date: August 30, 2007Inventor: Yih-Yuh Doong
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Publication number: 20070200588Abstract: Methods for qualifying the accuracy of a circuit board may include providing a printing mask pattern for first and second sides of the circuit board with a first sequence of spaced indicia parallel to a first edge of the printed circuit board, and a second sequence of spaced indicia parallel to a second edge of the printed circuit board opposite the first edge. A layer of visually conspicuous material may be printed on the board using the mask patterns. The board may be separated or cut to a predetermined size thereby removing, at least a portion of the spaced indicia of each sequence. The number of indicia printed on the first and second sides respectively of the circuit board may be determined after the circuit board is cut to the predetermined size. The circuit board may be accepted or rejected based upon the numerical determination against a qualification criteria.Type: ApplicationFiled: May 1, 2007Publication date: August 30, 2007Inventors: Edmond Lau, Xiaozhong Wang, Robert Mosebar
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Publication number: 20070200589Abstract: A test apparatus for a Liquid Crystal Display (LCD) device receives a mode input signal representing whether the LCD device is driven in a normal voltage driving mode or a high voltage driving mode. The test apparatus transmits a voltage to the LCD device and transmits a control signal to a high voltage applying module, which turns on to transmit a high voltage to the LCD device or turns off according to a level of the control signal. The LCD device may remain coupled with the high voltage applying module while the LCD device operation is shifted between a high voltage driving mode and a normal voltage driving mode during a manufacturing process thereof, so manufacturing time for the LCD device may be reduced.Type: ApplicationFiled: November 14, 2006Publication date: August 30, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Woo JEONG, Hyun-Min JANG
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Publication number: 20070200590Abstract: This invention generally relates to saturation detection circuits, in embodiments for substantially lossless detection of saturation of power switches in power integrated circuits. We describe a saturation detection circuit for detecting saturation of a power semiconductor device, the circuit including a said power semiconductor device having an input terminal and an output terminal, a second semiconductor device connected across said input and output terminals of said power semiconductor device, and a circuit responsive to a current flowing through said second semiconductor device to detect said saturation of said power semiconductor device.Type: ApplicationFiled: December 19, 2006Publication date: August 30, 2007Inventors: Vinod Lalithambika, Niek van der Schouten, A. Schiff
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Publication number: 20070200591Abstract: A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed.Type: ApplicationFiled: December 12, 2005Publication date: August 30, 2007Inventor: Kang Kim
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Publication number: 20070200592Abstract: A dynamic output buffer circuit performs an impedance matching function and a pre-emphasis function by using input and output signals, and consumes relatively less power, occupies a relatively smaller layout area, and dynamically varies an output impedance. The dynamic output buffer circuit dynamically matches an output impedance to the characteristic impedance of a metal line connected to an external circuit, pre-emphasizes at least one input signal, and includes a control circuit and an output circuit. The control circuit matches the output impedance of the dynamic output circuit to the characteristic impedance of the metal line in response to at least one output signal, and outputs a plurality of resistor control signals which are used to pre-emphasize at least one input signal in response to the input signal. The output circuit controls the output impedance and pre-emphasizes the input signal in response to the resistor control signals, and outputs the output signal.Type: ApplicationFiled: February 12, 2007Publication date: August 30, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-Kwan Kim, Joo-sun Choi
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Publication number: 20070200593Abstract: A digital circuit with dynamic power and performance control via per-block selectable operating voltage level permits dynamic tailoring of operating power to processing demand and/or compensation for process variation. A set of processing blocks having a power supply selectable from two different power supply voltage levels is provided. The power level of the overall circuit is set by selecting the power supply voltage for each block to yield a combination of blocks that meets operating requirements. Alternatively, one circuit per pair from a set of pairs of redundant logic blocks supplied by the different power supply voltage levels can be selected to meet the operating requirements. The unselected blocks can be disabled by disabling foot devices or disabling transitions at the inputs to the unselected blocks. Performance measurement and feedback circuits can be included to tune the power consumption and performance level of the circuit to meet an expected level.Type: ApplicationFiled: December 13, 2005Publication date: August 30, 2007Inventors: Kanak Agarwal, Damir Jamsek, Kevin Nowka
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Publication number: 20070200594Abstract: A crossbar switch is implemented in a reconfigurable circuit, such as a FPGA, instantiated with a number of modules, the crossbar switch providing communication links between the modules. The modules and crossbar switch can be easily updated in a partial reconfiguration process changing only portions of modules and the crossbar switch while other portions remain active. The crossbar switch uses individual wiring to independently connect module outputs and inputs so that asynchronous communications can be used. The crossbar switch can be implemented in different embodiments including a Clos crossbar switch, and a crossbar switch connecting each module output only to a corresponding module input, allowing for a reduction in the amount of FPGA resources required to create the crossbar switches.Type: ApplicationFiled: April 25, 2007Publication date: August 30, 2007Applicant: Xilinx, Inc.Inventors: Delon Levi, Tobias Becker
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Publication number: 20070200595Abstract: An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal based on the switch values. The clock control signal controls a macrocell buffer used for compensating for distortion of clock signals inputted to the macrocell. The macrocell buffer is disabled if the clock signals are not being used by the corresponding macrocell, thereby preventing unnecessary toggling and power consumption.Type: ApplicationFiled: February 27, 2006Publication date: August 30, 2007Applicant: ATMEL CORPORATIONInventor: Oliver Kao
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Publication number: 20070200596Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Andy Lee, Christopher Lane, Ketan Zaveri, Richard Cliff, Cameron McClintock, Srinivas Reddy, David Lewis
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Publication number: 20070200597Abstract: Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, differences in delay time, referred to as skew, are minimized. An embodiment of the clock generation circuit incorporates a waveform generator and a timing-improved deskewer. The waveform generator is clocked by a clock-in signal. The deskewer comprises a flip-flop, a level-sensitive latch, and a multiplexer. The flip-flop and latch are connected in parallel and each receives waveform signals from the waveform generator as well as the clock-in signal in order to generate output signals. The multiplexer gates the flip-flop and latch output signals with the clock-in signal in order to generate the clock-out signal. A testable deskewer for edge-sensitive multiplexer scan designs is also disclosed.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Inventor: Steven Oakland
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Publication number: 20070200598Abstract: Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer (12) having first and second inputs and an output and at least one N-type isolation transistor (13, 19) having a source coupled to one or both of the second input and the output. The first input receives the data signal, the second input receives a supply potential, and the output couples to the low voltage logic device. The isolation transistor has a drain for receiving a first potential and is configured to supply a a second potential to the output buffer when the gate receives a bias potential. The second potential based on the first potential. The bias potential is greater than the supply potential.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Paul Bennett, John Pigott
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Publication number: 20070200599Abstract: A differential threshold voltage level detection circuit receives a differential voltage pair as an input, applying each component of the differential pair to an individual voltage shifting circuit. Each voltage shifting circuit is configured with a regulated current producing a shifted and a non-shifted version in-phase. For a shifted set of output differential voltages, the shift magnitude is proportional to the current entering a shifting circuit and is configured to be less than a peak-to-peak magnitude of the differential voltage to be detected. A current mirror within the detector contains a current reference configured to produce a current to be passed through a voltage generator. The current magnitude is sufficient to generate a regulated voltage output to the two current regulating devices that supply the voltage shifting circuits. An overlap detector receiving both differential voltage pairs produces a signal indicating an input is at a detection threshold.Type: ApplicationFiled: May 3, 2007Publication date: August 30, 2007Applicant: ATMEL CORPORATIONInventors: Sami Ajram, Franck Strazzieri, Florent Garcia
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Publication number: 20070200600Abstract: A bulk voltage (VBB) level sensor for a semiconductor memory apparatus is disclosed. The VBB level detector includes a reference voltage generator for generating a first reference voltage of which level varies with temperature, a reference voltage comparator for receiving a second reference voltage and the first reference voltage to generate a third reference voltage, a bias generator for receiving the third reference voltage to generate a specific bias level, and a VBB sensor for receiving the bias level to detect VBB level.Type: ApplicationFiled: December 29, 2006Publication date: August 30, 2007Applicant: Hynix Semiconductor Inc.Inventor: Dong Keum Kang
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Publication number: 20070200601Abstract: The differential drive circuit generates a differential drive signal having a root mean square value defined by a digital input value. The differential drive signal includes a first differential component and a second differential component. The circuit comprises a first differential component generator and a second differential component generator. The first differential component generator is for counting the clock signal to generate successive values of a periodic count. Each of the values includes a most-significant bit. The first differential component generator is additionally for generating the first differential component in response to successive ones of the most-significant bit of the count. The second differential component generator is for generating the second differential component in response to the digital input value and the successive values of the count.Type: ApplicationFiled: March 13, 2007Publication date: August 30, 2007Inventors: Oliver LANDOLT, Ken Nishimura
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Publication number: 20070200602Abstract: A gate driving circuit for a voltage-driven power semiconductor switching device has (a) the voltage-driven power semiconductor switching device, (b) a driving circuit for supplying a drive signal to the gate electrode of the switching device, and (c) an inductance between the emitter control terminal or source control terminal of the switching device and the emitter main terminal or source main terminal of a semiconductor module. A voltage produced across the inductance is detected. The gate-driving voltage or gate drive resistance is made variable based on the detected value.Type: ApplicationFiled: January 19, 2007Publication date: August 30, 2007Inventors: Katsumi Ishikawa, Hideki Miyazaki, Masahiro Nagasu, Yasuhiko Kono
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Publication number: 20070200603Abstract: A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the voltage regulator. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the interconnect. In an embodiment of the present invention, a voltage regulator includes an AMP having a bias-generating device, such as a p-type transistor, acting as a current source, having a source coupled to Vdd and a drain coupled to the interconnect. The gate of the bias-generating device is coupled to the gate of four other p-type devices. Each of the four p-type devices has a source coupled to Vdd. The drains of the first and second p-type transistors are coupled to an output providing Ild.Type: ApplicationFiled: May 2, 2007Publication date: August 30, 2007Applicant: RAMBUS INC.Inventors: Xudong Shi, Kun-Yung Chang
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Publication number: 20070200604Abstract: The present invention relates to a delay locked loop (DLL) apparatus. The DLL apparatus includes: a first delay means converting a reference clock into a rising clock; a second delay means converting the reference clock into a falling clock by delaying the reference clock; a replica delay unit replica-delaying the rising clock delayed by the first delay means; a first phase detection means comparing the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases; a control means synchronizing the rising edge of the rising clock with the rising edge of the reference clock in accordance with the first detection signal of the first phase detection means; and a second phase detection means comparing the phases of the rising clock synchronized by the control means and the synchronization clock to output a second detection signal corresponding to the compared phases.Type: ApplicationFiled: February 22, 2007Publication date: August 30, 2007Inventors: Won Joo YUN, Hyun Woo LEE
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Publication number: 20070200605Abstract: A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph Marsh, Joseph Natonio, James Wilson
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Publication number: 20070200606Abstract: A pulsed flip-flop capable of adjusting a pulse width according to an operating voltage includes: a flip-flop operating in synchronization with a pulse signal; a pulse generating circuit generating the pulse signal in response to a clock signal; and a pulse width control circuit reducing a width of the pulse signal generated by the pulse generating circuit when the operating voltage is lower than a reference voltage.Type: ApplicationFiled: February 23, 2007Publication date: August 30, 2007Inventor: KWANG-IL KIM
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Publication number: 20070200607Abstract: A three-phase voltage-fed AC/DC converter includes a conversion circuit which converts power from a DC voltage source to three-phase AC power. The converter further includes a UM conversion circuit which carries out dq conversion of the three-phase output voltage, a superior voltage control circuit which outputs a voltage reference vector based on a superior reference vector and an output voltage vector obtained by the UM conversion circuit, an inferior voltage control circuit which outputs a PWM reference based on the voltage reference vector and the output voltage vector, and a frequency control circuit which synchronizes a value generated based on a q-axis component from the UM conversion circuit with a rotation angle of a conversion matrix in the UM conversion circuit.Type: ApplicationFiled: February 27, 2007Publication date: August 30, 2007Applicants: Origin ELECTRIC CO., LTD., The Tokyo Electric Power Company, IncorporatedInventors: Masaaki Ohshima, Hirokazu Shimizu, Shuichi Ushiki, Jirou Fukui
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Publication number: 20070200608Abstract: Apparatus and methods for regulating gate delays of synchronous and asynchronous digital circuits. Thermally-sensitive circuits include, generally, temperature sensitive voltage sources outputting a voltage signal indicative of the temperature of the digital circuit, where the voltage signal reflects non-linear temperature sensitivity above a predetermined threshold temperature, and delay mechanisms receiving said temperature sensitive voltage signal(s) as input and being configured to automatically continuously modulate the speed of signal propagation through the circuit in response to said voltage signal, thereby causing circuit elements within the circuits to switch less frequently and consequently causing the circuit elements to generate less heat with increasing circuit temperature.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Applicant: Cornell Research Foundation, Inc.Inventors: David Fang, Filipp Akopyan, Rajit Manohar
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Publication number: 20070200609Abstract: An integrated circuit device which internally generates a plurality of drowsy clock signals having different phases is provided. The integrated circuit device includes a phase synchronizer configured to output a plurality of clock signals having different phases in response to an external clock signal and a drowsy clock signal output unit configured to divide frequencies of the plurality of clock signals by a first factor, align the frequency-divided clock signals so that each consecutive clock signal has a constant phase difference relative to a phase difference of a preceding clock signal, and output the drowsy clock signals having lower frequencies and different phases. The integrated circuit device also includes a feedback unit configured to divide frequency of a clock signal with a phase angle of 0 output by the phase synchronizer by the first factor and output the frequency-divided clock signal having a phase angle of 0 degrees to an input port of the phase synchronizer.Type: ApplicationFiled: January 17, 2007Publication date: August 30, 2007Inventor: Uk-Song Kang
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Publication number: 20070200610Abstract: The invention concerns a circuit for detecting an overload in a load supplied by a switched-mode power supply, comprising: a first comparator of a first voltage based on the supply voltage of the load relative to a first threshold, supplying a regulating signal to a pulse generator controlling the switched-mode power supply; a second comparator of a second voltage relative to a second threshold, supplying a signal indicating the presence of an overload; and means for automatically controlling said second voltage by a third threshold lower than the second and higher than the first, and for deactivating the second comparator as long as said automatic control is maintained.Type: ApplicationFiled: February 6, 2007Publication date: August 30, 2007Applicant: STMicroelectronics S.A.Inventor: Alain Bailly
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Publication number: 20070200611Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.Type: ApplicationFiled: February 2, 2007Publication date: August 30, 2007Inventors: Richard Foss, Peter Gillingham, Robert Harland, Valerie Lines
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Publication number: 20070200612Abstract: The apparatus may include a non-pumping power supply unit configured to generate a supply voltage from a power source voltage and/or configured to output the supply voltage. The apparatus may include a pumping power supply unit and/or a control circuit. The pumping power supply unit may be configured to generate a pump voltage based on the power source voltage and/or configured to output the pump voltage. The control circuit may boost the supply voltage with the pump voltage after a level of the supply voltage reaches the first target voltage level.Type: ApplicationFiled: February 21, 2007Publication date: August 30, 2007Inventor: Bu-Il Jung
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Publication number: 20070200613Abstract: A gate driver circuit of a voltage drive type power semiconductor switching device capable of speeding up di/dt and dv/dt even during large-current driving to thereby reduce the switching loss is disclosed. This power semiconductor switching device gate driving circuit includes a drive circuit which applies a drive signal to the gate electrode of the power semiconductor switching device and a measurement unit for measuring a flow current of the power semiconductor switching device. Based on a detected value of the flow current of the power semiconductor switching device, the gate is made variable in mirror voltage thereof.Type: ApplicationFiled: January 19, 2007Publication date: August 30, 2007Inventors: Katsumi Ishikawa, Yutaka Sato, Masahiro Nagasu, Seiji Ishida
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Publication number: 20070200614Abstract: Provided are an apparatus and method of reducing a glitch in a switching device. The apparatus includes a latch latching a digital input signal and providing a digital output signal, a switching device segment unit including at least two switching device segment units, each one of the at least two switching device segment units switching a portion of the digital signal output, a glitch detection unit detecting a glitch generated within the switching device segment unit; and a voltage/current converter generating a latch control signal in response to an output from the glitch detection unit associated with a detected glitch, the latch control signal controlling an overlap of the digital output signal to reduce the glitch.Type: ApplicationFiled: February 20, 2007Publication date: August 30, 2007Inventor: Jin-hyuk Jeung
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Publication number: 20070200615Abstract: A driver circuit for powering an electronic device has a voltage source, two charge pump arrangements each having a diode connected in series with a capacitor. The charge pump arrangements are connected to the voltage source and the capacitors are charged, during a first phase, to a positive voltage level approximately equal to the voltage level of the voltage source. Furthermore, a switch is provided for switching the charge pump arrangements to a second phase, whereby they are charged simultaneously, one of the capacitors to a positive voltage approximately twice the voltage level provided by the voltage source and another one of the capacitors to a negative voltage level having a magnitude, which is approximately equal to a magnitude of the voltage source. An improved and cost-efficient driver circuit is thereby provided, having only few components.Type: ApplicationFiled: February 28, 2007Publication date: August 30, 2007Inventors: Jan-Erik Eklund, Joakim Alvbrant
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Publication number: 20070200616Abstract: A band-gap reference voltage generating apparatus is disclosed. The band-gap reference voltage generating apparatus according to the present invention includes an operational amplifier unit that is driven by a bias voltage and outputs an operational amplifying signal using a first voltage and a second voltage as input voltages; a voltage generating unit that generates the first voltage and the second voltage in response to the operational amplifying signal; a reference voltage generating unit that outputs a reference voltage in response to the operational amplifying signal; and a unit that feedbacks the reference voltage to generate as the bias voltage.Type: ApplicationFiled: December 13, 2006Publication date: August 30, 2007Applicant: Hynix Semiconductor Inc.Inventor: Yoon-Jae Shin
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Publication number: 20070200617Abstract: An architecture for reducing leakage component in semiconductor devices using a gated power supply is based on the supply being split into two parts. An alternate inverter is connected to a different power rail derived from the same single power rail. The power rails are enabled and disabled according to the value of a standby signal and an input signal. The standby signal is high in the standby mode and low in the active mode.Type: ApplicationFiled: December 29, 2006Publication date: August 30, 2007Applicant: STMicroelectronics Pvt. Ltd.Inventor: Ashish Kumar
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Publication number: 20070200618Abstract: A method and apparatus for the demodulation, filtering, decimation and optional voltage multiplication of modulated signals to produce in-phase and quadrature outputs using a discrete time architecture.Type: ApplicationFiled: February 15, 2007Publication date: August 30, 2007Inventor: Alon Konchitsky
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Publication number: 20070200619Abstract: A preamplifier circuit includes a differential amplifying unit, an offset detection unit and a reference signal generation unit. The differential amplifying unit compares an input signal pair with a reference signal pair to generate an output signal pair. The offset detection unit detects an offset of the output signal pair received from the differential amplifying unit to generate a calibration signal in an offset calibration mode. The reference signal generation unit adjusts the reference signal pair based on the calibration signal, and the reference signal pair is fed-back to the differential amplifying unit.Type: ApplicationFiled: February 27, 2007Publication date: August 30, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Young-Chan JANG
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Publication number: 20070200620Abstract: Disclosed is an offset cancellation amplifier which includes a first differential pair, second differential pair, a common load circuit for the two differential pairs, current sources, an amplifier stage, and first and second capacitors. The first capacitor is connected to the gate of one transistor of the first differential pair. During a first period of a data output period, an output voltage and the reference voltage are supplied to the gates of the first differential pair, the second capacitor is disconnected from the gate of the other transistor of the first differential pair. In this state, the output voltage is accumulated in the first and second capacitors. An input voltage is supplied in common to the gates of the second differential pair During the second period, the second capacitor is disconnected from the first capacitor and connected to the gate of the other transistor of the first differential pair.Type: ApplicationFiled: February 22, 2007Publication date: August 30, 2007Applicant: NEC CorporationInventor: Masao Iriguchi
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Publication number: 20070200621Abstract: An improved PWM amplifier is disclosed that uses multiple integrators in the loop filter to provide high loop gain across the frequency band-of-interest. The frequency characteristics of the loop filter are optimized to distribute large loop gains across the entire band to provide large suppression of noise and distortions generated in the modulation and output stages.Type: ApplicationFiled: March 2, 2006Publication date: August 30, 2007Inventor: WAI LEE
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Publication number: 20070200622Abstract: A modulator apparatus operating at a low supply voltage, configured for receiving an input-voltage signal in base band and supplying an output-voltage signal at a given modulation frequency under control of a signal generated by a local oscillator and comprising a transconductor stage that carries out a voltage-to-current conversion of said input-voltage signal. A voltage-to-current conversion module is coupled to a current-mirror module configured for mirroring a current in a Gilbert-cell stage, which supplies an output-voltage signal under the control of said signal generated by the local oscillator. The Gilbert-cell stage further comprises an output load for carrying out a current-to-voltage conversion and supplying the output-voltage signal. Said transconductor stage further comprises a differential feedback network configured for reproducing said input-voltage signal on a differential load included in said voltage-to-current conversion module.Type: ApplicationFiled: January 4, 2007Publication date: August 30, 2007Applicant: STMICROELECTRONICS S.R.L.Inventors: Pietro Filoramo, Alberto Cavallaro, Tiziano Chiarillo
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Publication number: 20070200623Abstract: An amplifier has an input stage amplifying circuit, an output stage amplifying circuit, and a negative feedback circuit. The input stage amplifying circuit differential-amplifies a first input voltage inputted to a positive phase input node and a second input voltage inputted to an opposite phase input node, and outputs from a positive phase output node. The output stage amplifying circuit amplifies output voltage from a node and outputs it from an output terminal, and generates the second input voltage corresponding to output voltage and feedback-inputs it to the opposite phase input node. The negative feedback circuit has a first PMOS for a current source whose output current fluctuates due to output voltage of the positive phase output node, and a differential amplifying section to which the output current of the first PMOS is supplied and which is formed from a second and third PMOS which differential-amplify the first input voltage and the second input voltage.Type: ApplicationFiled: January 9, 2007Publication date: August 30, 2007Inventor: Koji Suzuki
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Publication number: 20070200624Abstract: An architecture and method for improving efficiency of a Class-A power amplifier by dynamically scaling biasing current thereof as well as synchronously compensating gain thereof in order to maintain overall constant gain of the Class-A power amplifier at all biasing configurations thereof. A biasing-current switching-network is operatively connected to the back-end block of the Class-A power amplifier. A gain-control switching-network is operatively connected to a front-end block of the Class-A power amplifier. A detector-and-control block is operatively connected to an output of the back-end block of the Class-A power amplifier, and samples a signal that is then compared with reference signals to determine switching configurations in the biasing-current switching-network and the gain-control switching network when the signal is processed through the front-end block of the Class-A power amplifier followed by the back-end block of the Class-A power amplifier.Type: ApplicationFiled: February 27, 2007Publication date: August 30, 2007Inventors: Xinghao Chen, Yanbo Tian, Norman Scheinberg
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Publication number: 20070200625Abstract: The distortion compensating apparatus which adaptively updates a distortion compensation coefficient for an amplifier based on a difference between input and output signals of the amplifier, comprises: a distortion amount detector which detects the amount of distort of an output signal of the amplifier; a parameter holder which holds a parameter having been set therein; a parameter corrector which corrects the parameter in such a manner that the distortion amount detected by the detector is improved; and a distortion amount corrector which corrects the distortion amount detected by the detector in such a manner that the distortion amount is reduced by an offset amount according to an detection error. This arrangement makes it possible to accurately set the parameter relating to difference detection which is a factor of updating of distortion compensation coefficients of the distortion compensating apparatus.Type: ApplicationFiled: May 19, 2006Publication date: August 30, 2007Inventors: Hideharu Shako, Yasuhito Funyu, Takeshi Ohba